KR20160015841A - Light emitting diode - Google Patents

Abstract

The present invention relates to a light emitting diode with improved reliability. According to the present invention, the light emitting diode includes: a substrate; a light emitting cell placed on a substrate, and including a lower semiconductor layer, an upper semiconductor layer placed on an area of the lower semiconductor layer, and an active layer placed between the lower semiconductor layer and the upper semiconductor layer; a first electrode placed on the upper semiconductor layer; a second electrode placed on the lower semiconductor layer; a first insulating layer including a first opening area to expose a part of the first electrode; a second insulating layer placed on the first insulating layer; and a first bump making ohmic contact with the first electrode through the first opening area. The first bump includes a first convex part and a first concave part in the upper part. The first bump includes a first area, including a bottom part of the first concave part in the upper surface, and a second area including an upper surface of the first convex part in the upper surface. At least part of the first area is placed on the first opening area, and at least part of the second area is placed on the second insulating layer.

Description

[0001] LIGHT EMITTING DIODE [0002]

The present invention relates to light emitting diodes. More particularly, the present invention relates to a light emitting diode with improved reliability.

BACKGROUND ART Light emitting diodes (LEDs) are inorganic semiconductor devices that emit light generated by the recombination of electrons and holes. Recently, they have been used in various fields such as displays, automobile lamps, and general lighting.

1 is a cross-sectional view illustrating a light emitting diode according to a related art.

The prior art light emitting diode includes an H-shaped contact layer 14. Then, a bump for applying a current may be formed on the contact layer 14, and an insulating layer may be formed on the upper layer 16 except for the bump forming region. However, in the bump and insulating layer forming process according to the related art, there is a certain gap between the bump and the insulating layer. Such an interval exists for reasons of the manufacturing process of the LED, but the reliability of the LED may be a problem. Light emitting diodes, especially ultraviolet light emitting diodes, are susceptible to high temperature and / or high humidity, and thus the reliability of light emitting diodes is a problem. However, the gap existing in the LED according to the prior art can be used as a path for moisture and / or outside air.

On the other hand, the light emitting diodes have n-type and p-type bumps, and the bumps are mounted on the submount substrate. However, when a load is repeatedly applied to the bonding region between the n-type and p-type bumps and the submount substrate, the bonding force between the bumps and the submount substrate may be weakened, and the LED and the substrate may be separated from each other. Therefore, there is a demand for development of light emitting diodes that overcome the above-mentioned problems and have improved reliability and structural stability.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode having improved reliability and structural stability.

Another problem to be solved by the present invention is to provide a light emitting diode in which deterioration in luminescence properties is prevented in a high temperature and / or high humidity environment.

Another object of the present invention is to provide a light emitting diode having enhanced bonding force between a substrate and a bump.

A light emitting diode according to an embodiment of the present invention includes a substrate; A light emitting cell located on the substrate and including a lower semiconductor layer, an upper semiconductor layer disposed on one region of the lower semiconductor layer, and an active layer disposed between the lower semiconductor layer and the upper semiconductor layer; A first electrode disposed on the upper semiconductor layer; A second electrode disposed on the lower semiconductor layer; A first insulating layer including a first open region for exposing a portion of the first electrode; A second insulating layer disposed on the first insulating layer; And a first bump that is in ohmic contact with the first electrode through the first open area, wherein the first bump includes a first concave portion and a first convex portion at an upper portion thereof, A first region including a bottom surface of a concave portion and a second region including an upper surface of the first convex portion on an upper surface thereof, at least a portion of the first region being disposed on the first open region, At least a portion of the second region may be disposed on the second insulating layer.

Furthermore, the area of the bottom surface of the first concave portion may be proportional to the area of the first electrode exposed through the first open area.

The depth of the first concave portion may be proportional to the thickness of the first insulating layer and the second insulating layer disposed on the first electrode.

In some embodiments, the sum of the area of the top surface of the first convex portion and the bottom surface area of the first concave portion may be larger than the area of the first electrode exposed through at least the first open area.

A portion of the first insulating layer and the second insulating layer may be disposed between the first electrode and the first bump.

At least a portion of the side surfaces of the first insulating layer and the second insulating layer surrounding the first open area and the lower side surfaces of the first bump may be in contact.

Furthermore, the first convex portion may surround the first concave portion.

The first insulating layer may include a second open region that exposes a portion of the second electrode and a second bump that makes an ohmic contact with the second electrode through the second open region, Wherein the second bump includes a third region including a bottom surface of the second concave portion on an upper surface thereof and a second region including a top surface of the second convex portion on an upper surface thereof, 4 region, at least a portion of the third region may be disposed on the second open region, and at least a portion of the fourth region may be disposed on the second insulating layer.

The area of the bottom surface of the second concave portion may be proportional to the area of the second electrode exposed through the second open area.

The depth of the second concave portion may be proportional to the thickness of the first insulating layer and the second insulating layer disposed on the second electrode.

The sum of the area of the upper surface of the second convex portion and the area of the bottom surface of the second concave portion may be larger than the area of the second electrode exposed through the second open area.

In some embodiments, the first insulating layer and a portion of the second insulating layer may be disposed between the second electrode and the second bump.

Further, at least a part of the side surfaces of the first insulating layer and the second insulating layer surrounding the second open area and the side surfaces of the lower end of the second bump may be in contact with each other.

The second convex portion may surround the second concave portion.

The second insulating layer may include a silicon nitride layer.

Meanwhile, the light emitting cell may emit light in the ultraviolet wavelength region.

The substrate may include one surface on which the light emitting cells are disposed and another surface opposite to the one surface, and the other surface may include concave and convex portions.

The substrate may be a transparent sapphire substrate.

In addition, the first insulating layer may include a distributed Bragg reflector.

The light emitting diode according to the present invention improves the reliability in a high-temperature and / or high-humidity environment as well as a room temperature, so that deterioration of the luminescence characteristics can be prevented. In addition, the bonding force between the substrate and the bump is enhanced in the light emitting diode, so that separation between the light emitting diode and the substrate can be prevented even when the load is repeatedly applied to the bonding region of the substrate and the bump.

1 is a plan view and a cross-sectional view illustrating a light emitting diode according to a related art.
2 is a plan view and a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present invention.
4 is a plan view and a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
5 is a perspective view illustrating a light emitting diode package according to an embodiment of the present invention.
6 is a graph for explaining the improved effect of the present invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

2 is a plan view and a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

2 (a) is a plan view of the LED, and FIG. 2 (b) is a sectional view taken along line A-A in FIG. 2 (a).

Referring to FIG. 2, the light emitting diode includes a growth substrate 100, a lower semiconductor layer 115, an active layer 113, and an upper semiconductor layer 111. A contact layer 121, a pad layer 123, and an electrode layer 125 are disposed on the lower semiconductor layer 115. The second electrode 120b may include a contact layer 121, a pad layer 123, and an electrode layer 125.

The second electrode 120b is disposed and the second bump 130b is disposed on the second electrode 120b. The first electrode 120a may be formed through the reflective layer 127 and the barrier layer 129 when the reflective layer 127 and the barrier layer 129 are disposed on the upper semiconductor layer 111. [ A first bump 130a is disposed on the first electrode 120a. The front surface of the light emitting diode may be covered with a first insulating layer 128 and a second insulating layer 129 except for the region where the first bump 130a and the second bump 130b are disposed. The light emitting cells 110 may be formed on the lower semiconductor layer 115, the active layer 113, and the upper semiconductor layer 111.

The growth substrate 100 is a substrate having a hexagonal crystal structure, and may be a growth substrate for growing a gallium nitride-based epitaxial layer, for example, a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate. In particular, the growth substrate 100 may be a sapphire substrate to provide a deep ultraviolet light emitting diode. The growth substrate 100 includes a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. The one surface is a surface on which semiconductor layers are grown, and the other surface is a surface on which light generated in the active layer 113 is emitted to the outside. The side surface of the growth substrate 100 may be a plane perpendicular to the one surface and the other surface, but may include an inclined surface. A buffer layer (not shown) containing AlN or GaN may be formed to reduce lattice mismatching with the sapphire substrate before the lower semiconductor layer 115 is formed on one surface of the growth substrate 100.

In addition, the growth substrate 100 may have a rectangular shape as a whole, but the shape of the substrate is not limited thereto. Meanwhile, in the present embodiment, the thickness of the growth substrate 100 may be greater than 100 m, and more particularly, in the range of 150 m to 400 m. As the growth substrate 100 is thicker, the light extraction efficiency is improved. On the other hand, the side surface of the growth substrate 100 may include a breaking surface.

The lower semiconductor layer 115 is located on one side of the growth substrate 100. The lower semiconductor layer 115 may cover the entire surface of one side of the growth substrate 100. The lower semiconductor layer 115 may be formed on the growth substrate 100 so as to expose one side along the edge of the growth substrate 100, 0.0 > 100). ≪ / RTI >

The upper semiconductor layer 111 is located above one region of the lower semiconductor layer 115 and the active layer 113 is located between the lower semiconductor layer 115 and the upper semiconductor layer 111. Since the upper semiconductor layer 111 has a dumbbell shape having an H shape or a narrow waist, it can exhibit excellent light output characteristics under high current density conditions.

The lower semiconductor layer 115 and the upper semiconductor layer 111 may include a III-V compound semiconductor, for example, a nitride semiconductor such as (Al, Ga, In) N. The lower semiconductor layer 115 may include an n-type semiconductor layer doped with an n-type impurity (e.g., Si), and the upper semiconductor layer 111 may include a p-type dopant (e.g., Mg) and may include a p-type semiconductor layer. It may also be the opposite. Further, the lower semiconductor layer 115 and / or the upper semiconductor layer 111 may be a single layer and may also include multiple layers. For example, the lower semiconductor layer 115 and / or the upper semiconductor layer 111 may include a cladding layer and a contact layer, and may include a superlattice layer.

The active layer 113 may include a multiple quantum well structure (MQW), and an element forming the multiple quantum well structure and its composition may be adjusted to emit light having a desired peak wavelength in the multiple quantum well structure. For example, the well layer of the active layer 113 is _{In x Ga (1-x)} N (0 = x = 1) may be a semiconductor layer ternary, or Al _x In _y Ga _(1-xy) such as N ( Component semiconductor layers such as 0 = x = 1, 0 = y = 1, 0 = x + y = 1, and the value of x or y may be adjusted to emit light of a desired peak wavelength . However, the present invention is not limited thereto.

The semiconductor layers 111, 113, and 115 may be formed using a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition (PCVD) method, , Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like.

Hereinafter, a description of the well-known semiconductor layer related to the semiconductor layers 111, 113, and 115 including the III-V compound semiconductor is omitted.

The second electrode 120b including the contact layer 121, the pad layer 123 and the electrode layer 125 may surround the upper semiconductor layer 111. [ 2, the second electrode 120b surrounds the entire periphery of the upper semiconductor layer 111, but the present invention is not limited thereto. The second electrode 120b may extend to both sides of the upper semiconductor layer 111 from the position where the second bump 130b is located and surround about 50% or more of the upper semiconductor layer 111. [ The contact layer 121 may include at least one of Cr, Ti, Al, and Au, or may be a Cr / Ti / Al / Ti / Au multilayer structure. The pad layer 123 may comprise Ti or Au, or may be a Ti / Au multilayer structure. The electrode layer 125 may include Ti or Au, or may be a Ti / Au multilayer structure.

The second electrode 120b may also be located evenly spaced from the upper semiconductor layer 111. [ Thus, concentration of current can be prevented. Further, a recessed portion (not shown) may be formed on the surface of the lower semiconductor layer 115 between the second electrode 120b and the upper semiconductor layer 111. [ The current can be prevented from flowing along the surface of the upper semiconductor layer 111 by the concave-convex portion, and the current can be further dispersed.

The reflective layer 127 and the barrier layer 129 may form the first electrode 120a and the first electrode 120a may be disposed on the upper semiconductor layer 111 and may be formed on the upper semiconductor layer 111 And is electrically connected. The reflective layer 127 may include at least one of Ni, Au, and Al, or may be a Ni / Au multi-layer structure. The barrier layer 129 may comprise Ti or Au, or may be a Ti / Au multilayer structure. The first electrode 120a may have ohmic contact with the upper semiconductor layer 111 while having a high reflectivity.

And the second bump 130b is located on the second electrode 120b. The second bump 130b is spaced apart from the upper semiconductor layer 111. The first bump 130a is positioned on the first electrode 120a including the reflective layer 127 and the barrier layer 129. [

The first bump 130a may include a first area A1 and a second area A2. The first bump 130a may include a first concave portion and a first convex portion at an upper portion thereof. The first region A1 may include the first concavity, and therefore the top surface of the first region A1 may correspond to the bottom surface of the first concavity. The second region A2 may include the first convex portion, and thus the upper surface of the second region A2 may correspond to the upper surface of the first convex portion.

The second bump 130b may include a third area A3 and a fourth area A4. The second bump 130b may include a second concave portion and a second convex portion at an upper portion thereof. The third region A3 may include the second recessed portion, and therefore the upper surface of the third region A3 may correspond to the bottom surface of the second recessed portion. The fourth region A4 may include the second convex portion, and therefore the upper surface of the fourth region A4 may correspond to the upper surface of the second convex portion.

The second bump 130b and the first bump 130a may be formed of the same metal material. In addition, the first and second bumps 130a and 130b may be formed in a multi-layer structure, and may include, for example, an adhesive layer, a diffusion preventing layer, and a bonding layer. The adhesion layer may include, for example, Ti, Cr, or Ni, and the diffusion barrier layer may be formed of Cr, Ni, Ti, W, TiW, Mo, Pt, or a composite layer thereof. AuSn. ≪ / RTI >

The first insulating layer 128 is formed on the lower semiconductor layer 115, the active layer 113, the upper semiconductor layer 111, and the lower semiconductor layer 115, except for the region where the first bump 130a and the second bump 130b are disposed. The second electrode 120b, the reflective layer 127, and the barrier layer 129, as shown in FIG. The first insulating layer 128 may be formed of a single layer of a silicon oxide layer or a silicon nitride layer. Further, the first insulating layer 128 may be formed of a distributed Bragg reflector (DBR) in which oxide layers having different refractive indexes are stacked. Therefore, light can be reflected in the region between the first electrode 121 and the upper semiconductor layer 111, and the light extraction efficiency of the light emitting diode can be further improved. In addition, a second insulating layer 129 may be disposed on the first insulating layer 128. The second insulating layer 129 may be formed of a single layer of a silicon oxide layer or a silicon nitride layer, and in this embodiment, the second insulating layer 129 may be a silicon nitride layer. The moisture barrier property of the silicon nitride layer is relatively superior to that of the silicon oxide layer, so that when the second insulating layer 129 is a silicon nitride layer, the moisture barrier property of the light emitting diode can be improved.

 The first insulating layer 128 and the second insulating layer 129 may each have a thickness of 2000 to 7000 ANGSTROM. When the thickness of each of the first insulating layer 128 and the second insulating layer 129 is less than 2000 angstroms, it is difficult to improve the moisture-proof property. When the thickness of each of the insulating layers 127 and 129 exceeds 7000 angstroms, It becomes thick. In addition, the total thickness of the first insulating layer 128 and the second insulating layer 129 may be 1 占 퐉 or less, but is not limited thereto.

In this embodiment, the first and second bumps 130a and 130b may be formed to cover a part of the first and second insulating layers 128 and 129. Thus, at least a portion of the second region A2 of the first bump 130a may be disposed on the second insulating layer 129. [ Further, at least a portion of the fourth region A4 of the second bump 130b may be disposed on the second insulating layer 129. [ That is, a portion of the first and second insulating layers 128 and 129 may be disposed between the first bump 130a and the first electrode 120a or between the second bump 130b and the second electrode 120b have.

2, the first and second open regions 140a and 140b are formed by opening a portion of the first and second insulating layers 128 and 129 to form first and second open regions 140a and 140b, The side surfaces of the first and second insulating layers 128 and 129 may be exposed and the side surfaces of the exposed first and second insulating layers 128 and 129 may be exposed to the first bump 130a and / Or the second bump 130b.

2 (a), it can be seen that the area of the first open area 140a is smaller than the sum of the bottom surface of the first concave portion of the first bump 130a and the top surface of the first convex portion have. It is also understood that the area of the second open area 140b is smaller than the sum of the bottom surface of the second concave portion of the second bump 130b and the top surface of the second convex portion. That is, in this embodiment, the first and second bumps 130a and 130b may completely cover the first open area 140a or the second open area 140b, respectively.

The length of the upper surface of the first bump 130b is 14 to 18 占 퐉 longer than the length of the upper surface of the first electrode 120b exposed in the second open area 140b. The length of the upper surface of the first electrode 120b exposed in the second open region 140b may be a length overlapping with each other.

In addition, the light emitting diode may further include a resin (not shown) that encloses the first bump 130b and the second bump 130a. When the light emitting diode further includes the resin, the first bump 130b and the second bump 130a may be disposed in a state embedded in the resin. In this case, the first bump 130b and the second bump 130a The upper surface of the upper surface 130a may be exposed.

The present invention has no gap between the first and second insulating layers 128, 129 and the first and second bumps 130a, 130b in comparison with the prior art. Accordingly, the first and second electrodes 120a and 120b of the present invention can be completely sealed. Accordingly, it is possible to prevent external moisture or the like from penetrating into the light emitting diode, thereby improving the reliability of the light emitting diode. Further, in the present embodiment, since the entire surface of the light emitting diode is covered with the multiple layers of the first and second insulating layers 123 and 125, the inflow of moisture and the like can be blocked more effectively.

The area of the bottom surface of the concave portion of each of the first and second bumps 130a and 130b is larger than the area of the first electrode 120a and the second electrode 120b exposed in the first and second open regions 140a and 140b And the depth of the concave portion may be proportional to the thickness of the first and second insulating layers 128 and 129 disposed on the first electrode 120a or the second electrode 120b .

In the present embodiment, due to the concave portions and the convex portions disposed on the upper portions of the first and second bumps 130a and 130b, a stronger bonding force is exerted on the printed circuit board or the submount substrate, Lt; / RTI >

3 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present invention.

Referring to FIG. 3, the light emitting diode 400 is a light emitting diode according to an embodiment of the present invention, and the light emitting diode 400 is mounted on the submount substrate 200.

The submount substrate 200 includes a substrate 230 and an electrode pattern 220 disposed on the substrate 230. The substrate 230 may be any one of BeO, SiC, Si, Ge, SiGe, AlN and a ceramic substrate having excellent thermal conductivity. However, the present invention is not limited to this, and may be a substrate including a metallic material having a high thermal conductivity and an excellent electrical conductivity as well as an insulating material having a high thermal conductivity.

The second bump 130a and the first bump 130b are respectively bonded to the electrode patterns 220 in correspondence with the shapes of the second bump 130a and the first bump 130b, do. At this time, heat or ultrasonic waves can be used, or heat and ultrasonic wave can be simultaneously used. Alternatively, it can be bonded using a solder paste.

The first and second bumps 130a and 130b and the electrode pattern 220 may be bonded through the bonding region 210 through various bonding methods as described above.

4 is a plan view and a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention. The embodiment of Fig. 4 is the same as the embodiment of Fig. 2 except for the form of the first and second open regions. Therefore, redundant description is omitted.

Referring to FIG. 4, each of the first open area 140a and the second open area 140b may include a plurality of open areas. That is, as shown, the first open region 140a includes a plurality of open regions that expose a portion of the first electrode 130a, and the second open region 140b includes a portion of the second electrode 130b And a plurality of open areas that expose the openings. In this embodiment, the driving voltage of the light emitting diode can be lowered through the open regions 140a and 140b having the above-described shape.

In the present embodiment, the first open area 140a includes five open areas, and the second open area 140b includes three open areas, but the number and arrangement of the open areas are not limited thereto Do not.

5 is a perspective view illustrating a light emitting diode package according to an embodiment of the present invention.

5, the light emitting device package includes a first frame 311, a second frame 313, and an insulating layer 315 disposed between the first and second frames 311 and 313. A light emitting diode 400 and a submount substrate 200 and a wire 330 mounted in a cavity 317 formed on an upper surface of the substrate 300.

The light emitting diode 400 is a light emitting diode according to the embodiments of the present invention described above.

The first and second frames 311 may be a metal frame or a ceramic frame. When the first and second frames 311 are metal frames, the first and second frames 311 may include a single metal or an alloy including Al, Ag, Cu, Ni, and the like, which are excellent in electrical characteristics and heat dissipation.

The insulating layer 315 may include a bonding portion and has a function of fixing the first and second frames 311 and 313 on both sides. Power can be supplied to the light emitting diode 400 by connecting the pads and the power source through the wire 330.

6 is a graph for explaining the improved effect of the present invention.

Figure 6 is a graph showing the results after a 1000 hour reliability test. Conventional light emitting diodes and light emitting diodes according to the present invention are of the same size and have been subjected to ultrasonic bonding using a TDK flip bonder on a Si substrate. At the time of ultrasonic bonding, the bonding table temperature was 200 占 폚 and the nozzle temperature was 150 占 폚.

Referring to FIG. 6, the Y axis represents the power retention (Po retention) of the LED. R 1, R 2 and R 3 of the X axis are average values of the results of the conventional light emitting diode, and are represented by a dotted line. L1, L2 and L3 in the X-axis represent average values of the results of the light emitting diode according to the present invention, and are represented by solid lines.

R1 and L1 are the measurement results at room temperature and are shown in a circle. R2 and L2 are the results of measurement at high temperature (60 DEG C) and are indicated by triangles. R3 and L3 are the results of measurement at high temperature and humidity (60 ° C, 90%) and are indicated by squares. 6, it can be seen that the light emitting diode of the present invention has a high power retention rate in all cases.

The light emitting diode according to the embodiments of the present invention is excellent in the moisture-proof property, so that not only reliability is improved but also strong flip bonding is possible, so that the structural stability is high.

It will be apparent to those skilled in the art that various modifications, substitutions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. will be. Therefore, the embodiments disclosed in the present invention and the accompanying drawings are intended to illustrate and not to limit the technical spirit of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments and the accompanying drawings . The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: substrate
110: light emitting cell
111: upper semiconductor layer
113:
115: lower semiconductor layer
121: contact layer
123: pad layer
125: electrode layer
120a: first electrode
120b: second electrode
127: reflective layer
129: barrier layer
130a: first bump
130b: second bump
128: first insulating layer
129: second insulating layer
140a: first open area
140b: second open area
200: Sub-mount substrate
210: bonding area
220: electrode pattern
311: 1st frame
313: Second frame
315: Insulation layer
317: Cavity
330: Wire
400: light emitting diode

Claims (19)

Board;
A light emitting cell located on the substrate and including a lower semiconductor layer, an upper semiconductor layer disposed on one region of the lower semiconductor layer, and an active layer disposed between the lower semiconductor layer and the upper semiconductor layer;
A first electrode disposed on the upper semiconductor layer;
A second electrode disposed on the lower semiconductor layer;
A first insulating layer including a first open region for exposing a portion of the first electrode;
A second insulating layer disposed on the first insulating layer; And
And a first bump that is in ohmic contact with the first electrode through the first open area,
Wherein the first bump includes a first concave portion and a first convex portion at an upper portion thereof,
Wherein the first bump includes a first region including a bottom surface of the first concave portion on an upper surface thereof and a second region including an upper surface of the first convex portion on an upper surface thereof,
Wherein at least a portion of the first region is disposed on the first open region, and at least a portion of the second region is disposed on the second insulating layer. The method according to claim 1,
Wherein the area of the bottom surface of the first concave portion is proportional to the area of the first electrode exposed through the first open area. The method according to claim 1,
Wherein a depth of the first concave portion is proportional to a thickness of the first insulating layer and the second insulating layer disposed on the first electrode. The method according to claim 1,
Wherein the sum of the area of the upper surface of the first convex portion and the area of the bottom surface of the first concave portion is larger than the area of the first electrode exposed through the first open area. The method according to claim 1,
And a part of the first insulating layer and the second insulating layer are disposed between the first electrode and the first bump. The method according to claim 1,
And at least a part of the side surfaces of the first insulating layer and the second insulating layer surrounding the first open area and the lower side surfaces of the first bump are in contact with each other. The method according to claim 1,
And the first convex portion surrounds the first concave portion. The method according to claim 1,
Wherein the first insulating layer includes a second open region that exposes a portion of the second electrode and a second bump that is in ohmic contact with the second electrode through the second open region,
Wherein the second bump includes a second concave portion and a second convex portion at an upper portion thereof,
The second bump includes a third region on an upper surface including a bottom surface of the second concave portion and a fourth region on an upper surface including an upper surface of the second convex portion,
Wherein at least a portion of the third region is disposed on the second open region, and at least a portion of the fourth region is disposed on the second insulating layer. The method of claim 8,
And an area of a bottom surface of the second concave portion is proportional to an area of the second electrode exposed through the second open area. The method of claim 8,
Wherein a depth of the second concave portion is proportional to a thickness of the first insulating layer and the second insulating layer disposed on the second electrode. The method of claim 8,
The sum of the area of the upper surface of the second convex portion and the area of the bottom surface of the second concave portion is larger than the area of the second electrode exposed at least through the second open area. The method of claim 8,
And a part of the first insulating layer and the second insulating layer are disposed between the second electrode and the second bump. The method of claim 8,
And at least a part of the side surfaces of the first insulating layer and the second insulating layer surrounding the second open area and the side surfaces of the bottom end of the second bump are in contact with each other. The method of claim 8,
And the second convex portion surrounds the second concave portion. The method according to claim 1,
Wherein the second insulating layer comprises a silicon nitride layer. The method according to claim 1,
Wherein the light emitting cells emit light in an ultraviolet wavelength range. The method according to claim 1,
The substrate includes a first surface on which the light emitting cells are disposed and a second surface opposite to the first surface,
And the other surface includes concavities and convexities. The method according to claim 1,
Wherein the substrate is a transparent sapphire substrate. The method according to claim 1,
Wherein the first insulating layer comprises a distributed Bragg reflector.

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