KR20150058273A - 집적 회로를 위한 유연하고 공간 효율적인 i/o 회로 - Google Patents

집적 회로를 위한 유연하고 공간 효율적인 i/o 회로 Download PDF

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Publication number
KR20150058273A
KR20150058273A KR1020157008651A KR20157008651A KR20150058273A KR 20150058273 A KR20150058273 A KR 20150058273A KR 1020157008651 A KR1020157008651 A KR 1020157008651A KR 20157008651 A KR20157008651 A KR 20157008651A KR 20150058273 A KR20150058273 A KR 20150058273A
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KR
South Korea
Prior art keywords
pads
pad
defining
bonding
signal
Prior art date
Application number
KR1020157008651A
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English (en)
Korean (ko)
Inventor
조나단 씨. 팍스
인 하오 리우
콕 세옹 이
살라 엠 웨르펠리
Original Assignee
베이샌드 인코퍼레이티드
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Publication date
Priority claimed from US13/627,270 external-priority patent/US9166593B2/en
Application filed by 베이샌드 인코퍼레이티드 filed Critical 베이샌드 인코퍼레이티드
Publication of KR20150058273A publication Critical patent/KR20150058273A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
KR1020157008651A 2012-09-26 2013-09-24 집적 회로를 위한 유연하고 공간 효율적인 i/o 회로 KR20150058273A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/627,270 US9166593B2 (en) 2012-05-28 2012-09-26 Flexible, space-efficient I/O circuitry for integrated circuits
US13/627,270 2012-09-26
PCT/US2013/061317 WO2014052274A1 (en) 2012-09-26 2013-09-24 Flexible, space-efficient i/o circuitry for integrated circuits

Publications (1)

Publication Number Publication Date
KR20150058273A true KR20150058273A (ko) 2015-05-28

Family

ID=53719571

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157008651A KR20150058273A (ko) 2012-09-26 2013-09-24 집적 회로를 위한 유연하고 공간 효율적인 i/o 회로

Country Status (5)

Country Link
EP (1) EP2901477A4 (de)
JP (1) JP2015532530A (de)
KR (1) KR20150058273A (de)
CN (1) CN104781924A (de)
WO (1) WO2014052274A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7273654B2 (ja) * 2019-08-09 2023-05-15 ルネサスエレクトロニクス株式会社 半導体装置、その製造方法および電子装置
WO2021171408A1 (ja) * 2020-02-26 2021-09-02 株式会社ソシオネクスト 半導体集積回路装置
WO2024042698A1 (ja) * 2022-08-26 2024-02-29 株式会社ソシオネクスト 半導体集積回路装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246354A (ja) * 1989-03-20 1990-10-02 Nec Corp マスタースライス方式集積回路装置
JP3464802B2 (ja) * 1991-09-18 2003-11-10 株式会社東芝 セミカスタム集積回路
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
JP3951090B2 (ja) * 2000-06-19 2007-08-01 セイコーエプソン株式会社 半導体集積回路装置及びそのレイアウト設計方法
TW511193B (en) * 2001-12-13 2002-11-21 Acer Labs Inc Inner circuit structure of array type bonding pad chip and its manufacturing method
JP2004296998A (ja) * 2003-03-28 2004-10-21 Matsushita Electric Ind Co Ltd 半導体装置
US6798069B1 (en) * 2003-03-28 2004-09-28 Lsi Logic Corporation Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors
US7194707B2 (en) * 2004-09-17 2007-03-20 International Business Machines Corporation Method and apparatus for depopulating peripheral input/output cells
KR100699894B1 (ko) * 2006-01-31 2007-03-28 삼성전자주식회사 Ｅｓｄ 보호회로의 레이아웃을 개선한 반도체 칩
JP2007305822A (ja) * 2006-05-12 2007-11-22 Kawasaki Microelectronics Kk 半導体集積回路
US20070267748A1 (en) * 2006-05-16 2007-11-22 Tran Tu-Anh N Integrated circuit having pads and input/output (i/o) cells
JP2007335511A (ja) * 2006-06-13 2007-12-27 Fujitsu Ltd 半導体集積回路装置の設計方法、半導体集積回路装置およびその製造方法
US7872283B2 (en) * 2006-11-09 2011-01-18 Panasonic Corporation Semiconductor integrated circuit and multi-chip module
JP5264135B2 (ja) * 2006-11-09 2013-08-14 パナソニック株式会社 半導体集積回路及びマルチチップモジュール
JP2009164195A (ja) * 2007-12-28 2009-07-23 Panasonic Corp 半導体チップ
US7932744B1 (en) * 2008-06-19 2011-04-26 Actel Corporation Staggered I/O groups for integrated circuits
JP2010147282A (ja) * 2008-12-19 2010-07-01 Renesas Technology Corp 半導体集積回路装置
TWI370531B (en) * 2009-03-19 2012-08-11 Faraday Tech Corp Io cell with multiple io ports and related techniques for layout area saving
JP2012235048A (ja) * 2011-05-09 2012-11-29 Renesas Electronics Corp 半導体装置

Also Published As

Publication number Publication date
EP2901477A4 (de) 2016-07-06
WO2014052274A1 (en) 2014-04-03
EP2901477A1 (de) 2015-08-05
CN104781924A (zh) 2015-07-15
JP2015532530A (ja) 2015-11-09

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