WO2007136932A2 - Integrated circuit having pads and input/output (i/o) cells - Google Patents
Integrated circuit having pads and input/output (i/o) cells Download PDFInfo
- Publication number
- WO2007136932A2 WO2007136932A2 PCT/US2007/065619 US2007065619W WO2007136932A2 WO 2007136932 A2 WO2007136932 A2 WO 2007136932A2 US 2007065619 W US2007065619 W US 2007065619W WO 2007136932 A2 WO2007136932 A2 WO 2007136932A2
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- bond
- cell
- bond pad
- pad
- pads
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Definitions
- the present invention relates to an integrated circuit, and more particularly, to an integrated circuit having pads and input/output cells.
- the pads such as, for example, bond pads and probe pads
- the equipment used to make connections to the pads may not be able to adequately handle the significantly reduced geometries desired for the pads.
- the connections which utilize smaller pads may not be as reliable.
- FIG. 1 illustrates a top view of an integrated circuit having a pad portion in accordance with one embodiment of the present invention
- FIGS. 2-9 illustrate a top view of a pad portion of an integrated circuit of FIG. 1 in accordance with alternate embodiments of the present invention
- FIG. 10 illustrates a cross-section view of a pad portion of an integrated circuit of FIG. 5 in accordance with one embodiment of the present invention.
- FIGS. 11-14 illustrate a top view of a pad portion of an integrated circuit of FIG. 1 in accordance with alternate embodiments of the present invention.
- Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention. Detailed Description
- FIG. 1 illustrates a top view of an integrated circuit (IC) 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an integrated circuit (IC) 10 having a core area 514, an integrated circuit (IC) 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a core area 514, an IC 10 having a
- I/O area 11 an I/O portion 12 in accordance with one embodiment of the present invention.
- the I/O portion 12 is located within the I/O area 11.
- the I/O area 11 is an area of IC 10 in which I/O cells and pads for the IC 10 are located.
- the I/O area 11 is located around all or most of the peripheral area of the integrated circuit 10.
- Alternate embodiments of IC 10 may locate the I/O area 11 anywhere on IC 10.
- the geometric shape of I/O area 11 may not be rectangular, but may be any desired shape or shapes.
- I/O area 11 may be comprised of any number of non-contiguous shapes.
- FIG. 2 illustrates one embodiment of a pad portion 12 or I/O portion 12 of integrated circuit 10 of FIG. 1.
- portion 12 includes multiple I/O cells 14, 16.
- I/O cell encompasses an input-only cell, an output-only cell, or an input and output cell.
- I/O pad and “pad” encompass a pad that conveys only an input signal, only an output signal, or both an input signal and an output signal.
- I/O pads include one or more bond pads and/or one or more probe pads. Bond pads may also include wire bond pads, bump bond pads, or any other type of bond pad.
- I/O cells In physical layout, I/O cells (e.g. I/O cells 300-310, 350-360 of FIG. 9) are placed adjacent to each other to form one or more linear banks of I/O cells occupying a specific area (e.g. I/O area 11 in FIG. 1) of the IC 10.
- each I/O cell 14, 16 (see FIG. 2) has the same structure and includes a bond pad 20, 18, respectively.
- one or more I/O cells 14, 16 may have a different structure and may still utilize bond pads 20, 18, respectively. Note that each of the bond pads 18, 20 may be used as an interconnection point between circuitry internal to IC 10, and circuitry external to IC 10 (not shown).
- FIG. 2 illustrates a bond pad 20 which is electrically connected to a first I/O cell 14 while also physically overlaying active circuitry of a second I/O cell 16.
- Bond pad 18 is electrically connected to an I/O cell 16 while also physically overlaying active circuitry of a second I/O cell 14.
- I/O cell 14 is electrically connected to pad 20
- I/O cell 16 is electrically connected to pad 18.
- Pad 18 has a bonded region 22 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 20 has a bonded region 24 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- the size of the pads 18, 20 may be increased, thus allowing the diameter of the ball bonds to be increased.
- Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- the bond pads 18, 20 are not placed in a single horizontal row.
- the term horizontal refers to the "x" direction
- the term “vertical” refers to the "y” direction.
- the pads 18, 20 are vertically displaced relative to each other so that each bond pad 18, 20 may be widened in the horizontal direction without any overlapping of bond pads 18, 20. If bond pads 18, 20 had been placed side by side in a same horizontal row, they would have been required to be more narrow so that they did not overlap. Narrower bond pads would have required smaller ball bond diameters. A smaller geometry of ball bonds would have reduced manufacturing yield and would have reduced the long term interconnect reliability. This was not desirable.
- the "x" direction in the figures is parallel to the outside edge of IC 10, and the "y” direction is perpendicular to the outside edge of IC 10.
- the "x" direction for I/O cells 300-310 is parallel to edge 396 and the "y” direction for I/O cells 300-310 is perpendicular to edge 396; similarly, the "x" direction for I/O cells 350-360 is parallel to edge 398 and the "y” direction for I/O cells 350-360 is perpendicular to edge 398.
- I/O cell is generally assumed to include conductors and active devices for a wide variety of purposes, such as, for example, for normal I/O functionality, for ESD (electro-static discharge) protection, for local interconnect between all these devices, and for power and/or ground buses (herein called power buses).
- the power buses provide the required power and/or ground voltages to cells (e.g. 14, 16), to the bond pads (e.g. 18, 20), and/or to the probe pads (e.g. 60, 61 of FIG. 5).
- the bond pads and probe pads provide electrical coupling to the outside world beyond IC 10.
- the active devices used for normal I/O functionality include, as examples, p-channel field effect transistors (e.g. PMOSFETs) and n- channel field effect transistors (e.g. NMOSFETs), output drivers, predriver circuitry, input buffers, and other circuit components typically included for normal I/O operation. Alternate embodiments may use any desired device or devices in an I/O cell. Note that in the illustrated embodiment, the width of bond pad 18 is wider than the width of I/O cell 16, and the width of bond pad 20 is wider than the width of I/O cell 14. Note that as used herein, the term “wider” refers to the "x" direction. Wider pads (e.g.
- a pad e.g. 18
- I/O cell e.g. 16
- the wider pads 18, 20 allow for more reliable and manufacturable wire bonds to those pads 18, 20. Note that for these widths in the illustrated embodiment, the bond pad width and the I/O cell width are measured along substantially parallel lines. Note also that I/O cell 14 and I/O cell 16 are adjacent.
- FIG. 3 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- the term "power bond pad” refers to a bond pad (e.g. 34, 35) used for either power or ground interconnection.
- the term “signal bond pad” refers to a bond pad (e.g. 32, 33) used for interconnection of a signal, where the signal is not solely providing either power or ground. Note that each signal bond pad (e.g. 32) and its corresponding signal bonded region (e.g. 36) are associated with one I/O cell to which it is electrically connected.
- each signal bond pad may be located wherever desired on IC 10 and no longer must overlie its associated I/O cell.
- Each power bond pad (e.g. 34) and its corresponding power bonded region (e.g. 38) is associated with one power interconnect conductor (not shown) to which it is electrically connected. This power interconnect conductor may be considered to be part of a corresponding I/O cell (e.g. 30).
- each signal bond pad (e.g. 32, 33) and power bond pad (e.g. 34, 35) may be located wherever desired on IC 10.
- the power bond pads are not restricted to the die edge, and the signal bond pads are not restricted to the interior; alternate embodiments might have bond pads 32 and 33 as the power bond pads, and bond pads 34 and 35 as the signal bond pads; additional alternate embodiments might have bond pads 32 and 34 as the power bond pads, and bond pads 33 and 35 as the signal bond pads.
- the signal bond pads and power bond pads are generally placed overlying the I/O cells (e.g. 30, 31).
- the power and ground buses are routed through the I/O cell as part of the I/O cells. In alternate embodiments, the power buses may not be routed through the I/O cells, but may be routed elsewhere on IC 10.
- FIG. 3 illustrates one embodiment of a pad portion 12 or I/O portion 12 of integrated circuit 10 of FIG. 1.
- portion 12 includes multiple I/O cells 30, 31.
- Bond pads 32, 34 are electrically connected to a first I/O cell 30 while also physically overlaying active circuitry of a second I/O cell 31.
- Bond pads 33, 35 are electrically connected to an I/O cell 31 while also physically overlaying active circuitry of a second I/O cell 30.
- I/O cell 30 is electrically connected to pads 32, 34, and I/O cell 31 is electrically connected to pads 33, 35.
- Pad 32 has a bonded region 36 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 34 has a bonded region 38 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 33 has a bonded region 37 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 35 has a bonded region 39 which is the intended region for the ball bond (not shown) when wire bonding is performed. Note that by allowing the pads 32, 34 and 33, 35 to overlie adjacent I/O cells (31 and 30, respectively) the size of the pads 32-35 may be increased, thus allowing the diameter of the ball bonds to be increased. Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- FIG. 3 differs from the embodiment of FIG. 2 is that there is not enough vertical space to place the bond pads (32, 33) in separate rows. Likewise, there is not enough vertical space to place the bond pads (33, 34) in separate rows, and there is not enough vertical space to place the bond pads (34, 35) in separate rows. Thus, unlike FIG. 2 which illustrates total vertical displacement (i.e. full staggering) between pads 18 and 20, FIG. 3 illustrates only partial vertical displacement (i.e. partial staggering) between pads 32 and 33, between pads 33 and 34, and also between pads 34 and 35. As a result, the bond pads 32 and 33 are only partially staggered in the "y" direction.
- the bond pads 33 and 34 are only partially staggered in the "y” direction; and the bond pads 34 and 35 are only partially staggered in the "y” direction.
- the hexagonal shape of the bond pads 32-35 of FIG. 3 lends itself to tight packing when partial staggering, rather then full staggering, is used.
- alternate embodiments may use any desired shapes or combination of shapes for bond pads 32-35, such as, for example, square, diamond, rectangular, octagonal, circular, oval, curved, etc.
- Other embodiments may use any polygon or curved shape or shapes and varying orientations that pack with the desired compactness.
- each I/O cell 30, 31 illustrated in FIG. 3 has a plurality of bond pads connected to it (e.g. pads 32, 34 for I/O cell 30).
- one of the bond pads e.g. 34
- the other bond pad e.g. 32
- bond pads 32 and 33 may be arranged in a partially staggered manner, and bond pads 34 and 35 may be omitted.
- the little squares within the bond pads 32-35 represent vias used to make the underlying connection to their respective bond pads 32-35.
- the bond pads (e.g. 34, 35) closer to the edge of IC 10 are used as power bond pads, and the bond pads (e.g. 32, 33) farther from the edge of IC 10 are used as signal bond pads.
- restrictive layout design rules for the interconnect layers are used to prevent damage during wire bonding.
- the restrictive layout design rules provide sufficient structural support to prevent damage to IC 10 during the physical stress of the wire bonding process.
- most ICs 10 do not have these same restrictive layout design rules for the interconnect layers in other portions of the IC 10 (e.g. core area 514 of FIG. 1 where functional circuitry may be located, such as, for example, memory, execution units, registers, state machines, control logic, arithmetic logic, timers, etc.).
- FIG. 4 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention. Note that the embodiment illustrated in FIG. 4 uses octagonal shapes for bond pads 42-45.
- octagonal shapes may be more compatible with computer aided design (CAD) tools that limit the vertices of a pad to 45 degrees or 90 degrees.
- CAD computer aided design
- the vertices of 30 degrees and 60 degrees required by a hexagonal shape may not be supported, or not easily supported, by some CAD tools used to design integrated circuits.
- the shapes used for bond pads (e.g. 42-45) may be any desired shape; however, some shapes may have an advantage in particular embodiments. Still referring to FIG. 4, bond pads 42, 44 are electrically connected to a first I/O cell
- I/O cell 40 is electrically connected to pads 42, 44, and I/O cell 41 is electrically connected to pads 43, 45.
- Pad 42 has a bonded region 46 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 44 has a bonded region 48 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 43 has a bonded region 47 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 45 has a bonded region 49 which is the intended region for the ball bond (not shown) when wire bonding is performed. Note that by allowing the pads 42, 44 and 43, 45 to overlie adjacent I/O cells (41 and 40, respectively) the size of the pads 42-45 may be increased, thus allowing the diameter of the ball bonds to be increased. Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- FIG. 5 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- FIG. 5 illustrates the use of a separate probe pad 60 that is electrically coupled to its corresponding bond pad 52 for communicating the same signal from probe pad 60 and bond pad 52.
- a separate probe pad 61 that is electrically coupled to its corresponding bond pad 53 is also shown.
- Probe pad 60 may be implemented as an extension of bond pad 52, and probe pad 61 may be implemented as an extension of bond pad 53.
- Probe pad 60 has a probe region 62 which is the intended region for the probe tip (not shown) touchdown and scrub when probing is performed.
- Probe pad 61 has a probe region 63 which is the intended region for the probe tip (not shown) touchdown and scrub when probing is performed.
- bond pads 54 and 55 have bonded regions 58 and 59 which are the intended region for the ball bond (not shown) when wire bonding is performed for the purpose of creating a power and/or ground electrical connection.
- the corresponding probe regions for bond pads 54 and 55 may be elsewhere on IC 10.
- bond pads 52-55 and probe pads 60, 61 are formed of aluminum. In alternate embodiments, bond pads 52-55 and probe pads 60, 61 may be formed of any conductive material. Note that aluminum may be used for bond pads 52-55 and probe pads 60, 61 even when a different material (e.g. copper) is used for underlying interconnect layers. Note that for one embodiment, the probe pads 60, 61 are formed overlying a passivation layer, and thus may be formed overlying region 514. Note that bond pads 52, 53 may also be formed over passivation like probe pads 60, 61.
- the probe needle (during the probe process) may physically damage the top layer of the pad region; and thus wire bond reliability and manufacturability may be negatively impacted if the same pads are used for probe and wire bonding.
- FIG. 5 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- bond pads 54, 55 are used as power bond pads and bond pads 52, 53 are used as signal bond pads.
- each signal bond pad (e.g. 52) and its corresponding signal bonded region (e.g. 56) are associated with one I/O cell to which it is electrically connected.
- each signal bond pad may be located wherever desired on IC 10 and no longer must overlie its associated I/O cell.
- Each power bond pad (e.g. 54) and its corresponding power bonded region (e.g. 58) is associated with one power interconnect conductor (not shown) to which it is electrically connected. This power interconnect conductor may be considered to be part of a corresponding I/O cell (e.g. 50).
- each signal bond pad e.g. 52, 53
- power bond pad e.g. 54, 55
- the signal bond pads and power bond pads are generally placed overlying the I/O cells (e.g. 50. 51) or within the I/O area 11.
- the power and ground buses are routed through the I/O cell as part of the I/O cells. In alternate embodiments, the power buses may not be routed through the I/O cells, but may be routed elsewhere on IC 10.
- FIG. 5 illustrates one embodiment of a pad portion 12 or I/O portion 12 of integrated circuit 10 of FIG. 1.
- portion 12 includes multiple I/O cells 50, 51.
- Bond pads 52, 54 are electrically connected to a first I/O cell 50 while also physically overlaying active circuitry of a second I/O cell 51.
- Bond pads 53, 55 are electrically connected to an I/O cell 51 while also physically overlaying active circuitry of a second I/O cell 50.
- I/O cell 50 is electrically connected to pads 52, 54, and I/O cell 51 is electrically connected to pads 53, 55.
- Pad 52 has a bonded region 56 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 54 has a bonded region 58 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 53 has a bonded region 57 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 55 has a bonded region 59 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- the size of the pads 52-55 may be increased, thus allowing the diameter of the ball bonds to be increased. Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- the small squares 400 within the bond pad 54 represent vias used to make the underlying connection from conductors in I/O cell 50 to bond pad 54.
- the small squares 401 within the bond pad 55 represent vias used to make the underlying connection from conductors in I/O cell 51 to bond pad 55.
- FIG. 6 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- Fig. 6 is similar to FIG. 5, except the length of probe pad 81 is extended vertically so that probe regions 82, 83 align at the top. For some embodiments, this alignment allows for ease of the probe process and probe card maintenance because it is easier to verify alignment of probe needles when all needles on a side are expected to be in a straight line.
- pad extension 84 may be added to bond pad 74 so that 84 and 74 in combination produces a region that may be probed. This probe region may or not be used for wire bonding. Some embodiments may use redundant power bond pads 74 so that a portion of these pads may be probed, and a different portion may be wire bonded to avoid the problem of wire bonding over probe damage.
- FIG. 6 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- bond pads 74, 75 are used as power bond pads and bond pads 72, 73 are used as signal bond pads.
- each signal bond pad (e.g. 72) and its corresponding signal bonded region (e.g. 76) are associated with one I/O cell to which it is electrically connected.
- each signal bond pad may be located wherever desired on IC 10 and no longer must overlie its associated I/O cell.
- Each power bond pad (e.g. 74) and its corresponding power bonded region (e.g. 78) is associated with one power interconnect conductor (not shown) to which it is electrically connected. This power interconnect conductor may be considered to be part of a corresponding I/O cell (e.g. 70).
- each signal bond pad e.g. 72, 73
- power bond pad e.g. 74, 75
- the signal bond pads and power bond pads are generally placed overlying the I/O cells (e.g. 70. 71).
- the power and ground buses are routed through the I/O cell as part of the I/O cells. In alternate embodiments, the power buses may not be routed through the I/O cells, but may be routed elsewhere on IC 10.
- FIG. 6 illustrates one embodiment of a pad portion 12 or I/O portion 12 of integrated circuit 10 of FIG. 1.
- portion 12 includes multiple I/O cells 70, 71.
- Bond pads 72, 74 are electrically connected to a first I/O cell 70 while also physically overlaying active circuitry of a second I/O cell 71.
- Bond pads 73, 75 are electrically connected to an I/O cell 71 while also physically overlaying active circuitry of a second I/O cell 70.
- I/O cell 70 is electrically connected to pads 72, 74, and I/O cell 71 is electrically connected to pads 73, 75.
- Pad 72 has a bonded region 76 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 74 has a bonded region 78 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 73 has a bonded region 77 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 75 has a bonded region 79 which is the intended region for the ball bond (not shown) when wire bonding
- the size of the pads 72-75 may be increased, thus allowing the diameter of the ball bonds to be increased.
- Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- FIG. 7 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- FIG. 7 is similar to FIG. 6, except adjacent pads from FIG. 6 (namely 74, 75) have been merged (electrically and physically connected) so that region 108 may be used for probe and region 109 may be used for wire bonding. Thus the wire bonding region 109 will not have any probe damage.
- bond pad 104 is used as a power bond pad having a wire bond region 109 and having a probe region 108.
- bond pads 102, 103 are used as signal bond pads. Note that each signal bond pad (e.g. 102) and its corresponding signal bonded region (e.g. 106) are associated with one I/O cell to which it is electrically connected. However, each signal bond pad may be located wherever desired on IC 10 and no longer must overlie its associated I/O cell.
- the power bond pad 104 and its corresponding power bonded regions (e.g. 108 and 109) is associated with one power interconnect conductor (not shown) to which it is electrically connected. This power interconnect conductor may be considered to be part of a corresponding I/O cell (e.g. 100).
- the power bond pad 104 may be located wherever desired on IC 10. However, due to the fact that the underlying layers must withstand the impact of the wire bonding process, the power bond pads are generally placed overlying the I/O cells (e.g. 100, 101). Also, in some embodiments, the power and ground buses are routed through the I/O cell as part of the I/O cells. In alternate embodiments, the power buses may not be routed through the I/O cells, but may be routed elsewhere on IC 10.
- FIG. 7 illustrates one embodiment of a pad portion 12 or I/O portion 12 of integrated circuit 10 of FIG. 1.
- portion 12 includes multiple I/O cells 100, 101.
- Bond pad 102 is electrically connected to a first I/O cell 100 while also physically overlaying active circuitry of a second I/O cell 101.
- Bond pad 103 is electrically connected to an I/O cell 101 while also physically overlaying active circuitry of a second I/O cell 100.
- Pad 102 has a bonded region 106 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 104 has a region 108 which is the intended region to receive a probe needle for probing at least a portion of IC 10.
- Pad 104 also has a bonded region 109 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 103 has a bonded region 107 which is the intended region for the ball bond (not shown) when wire bonding is performed. Note that by allowing the pads 102, 103, and 104 to overlie adjacent I/O cells 100, 101, the size of the pads 102-104 may be increased, thus allowing the diameter of the ball bonds to be increased and allowing the area of the probe region to be increased. Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- FIG. 8 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG.
- bond pad 131 may have a substantially larger size and area than bond pad 130.
- the present invention may be used to solve this problem because the width of the bond pad (e.g. width of pad 131) is no longer limited by the width of the I/O cell ("c"). This allows the width of the I/O cell to be narrowed, while still maintaining or even enlarging the width of the bond pad.
- the width "c" of the I/O cells 134, 135 are the same as the width of the I/O cells 132, 133; however, the width of the bond pad 131 may be made substantially larger than "c".
- Dimensions "a” and “b” denote the dimension of the separate probe pad that is electrically coupled to its corresponding bond pad for communicating the same signal from probe pad and bond pad.
- Pad 130 has a bonded region 136 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- Pad 131 has a bonded region 137 which is the intended region for the ball bond (not shown) when wire bonding is performed.
- the bonded region 137 of pad 131 may have a substantially larger size than the bonded region 136 of pad 130, thus allowing the diameter of the ball bonds to be substantially increased. Increasing the size of the ball bonds improves the manufacturability and long term reliability of the interconnect (e.g. wire bonds).
- the vertical dimension of the I/O cell may be increased (i.e. the vertical dimension "e” of I/O cells 134, 135 may be larger than the vertical dimension "d" of I/O cells 132, 133).
- Most IC designs have more flexibility to expand in the vertical dimension of an I/O cell than in the horizontal dimension of an I/O cell.
- most IC designs place a limit on the bond pad size and width, since increasing the bond pad size or width might cause the size die to increase.
- FIG. 8 illustrates a way to increase the size and width of a bond pad (from the size of pad 130 to the size of pad 131) without increasing the pitch or width of the I/O cells 132-135, and thus without increasing the die size. Note that I/O cells 134, 135 still have the same width and pitch "c" as I/O cells 132, 133.
- FIG. 9 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- the location of bond pads 320-324, 330-335, 380-384, and 390-395 are spread out as the corner of IC 10 is approached. This is done in order to maintain a minimum pitch between wires (not shown) that are bonded to the bond pads. Note that the wires would become squeezed more closely together at the corners if the pitch between the bond pads was not increased as the corner was approached.
- the pitch of the I/O cells 300-310 and 350-360 can remain constant (abutted without any gap or space) while the bond pads 320-324, 330-335, 380-384, 390-395 can become more spread out as the corner of IC 10 is approached. Since the pitch of the I/O cells 300-310, 350-360 is not increased as the corner is approached, more I/O cells 300-310, 350-360 may be squeezed along the periphery of IC 10. Thus, the pitch or spacing for bond pads (e.g. 320-324, 330-335, 380-384, 390- 395) can be increased at the corners of IC 10, while maintaining the closest possible pitch or spacing for the I/O cells (e.g. 300-310, 350-360).
- bond pad pitch and I/O cell pitch is made possible by allowing bond pads (e.g. 320-324, 330-335, 380-384, 390-395) to overlie any I/O cell: not just the I/O cell to which each bond pad is electrically connected.
- bond pads e.g. 320-324, 330-335, 380-384, 390-395
- corner cell 341 may be used for bond pads.
- one or more additional I/O cells may be added either horizontally or vertically if desired.
- more bond pads may be added overlying corner cell 341 if there is sufficient space.
- the hatched filled shapes e.g.
- each I/O cell 300-310, 350-360 is connected to one or more corresponding bond pads 320-324, 330-335, 380-384, 390-395. Note that in the illustrated embodiment, as the corner is approached, the offset between the I/O cell and its corresponding bond pad is increased.
- each I/O cell has one corresponding bond pad.
- each I/O cell may have more than one bond pad, such as a signal bond pad plus one or more associated power bond pads (see FIG. 3).
- Alternate embodiments may also have one or more probe pads associated with some or all of the I/O cells.
- Bond pads may be any shape (e.g. see FIGS. 3 and 4) and may be any size that meets the design rule criteria. Alternate embodiments may have only a single row of bond pads, may have two rows of bond pads, or may have any number of rows of bond pads.
- FIG. 10 illustrates a cross-section view of a pad portion 12 of integrated circuit 10 of FIG. 5 in accordance with one embodiment of the present invention.
- bond pad 54 may be formed of a single layer (e.g. aluminum). In alternate embodiments, bond pad 54 may be formed of a plurality of layers of different materials (e.g. a layer of aluminum overlying a layer of copper). In some embodiments, a barrier layer (e.g. tantalum) may be interposed between the aluminum and copper layers.
- layer 402 is a dielectric layer. Layer 402, in some embodiments, may be a passivation layer formed using a passivation material.
- pad 54 may comprise copper, aluminum, gold or any other conducting materials.
- pad 54 may be formed from an aluminum layer. This aluminum layer may be used as an aluminum cap layer, and the underlying interconnect layers 403 may be formed of copper.
- Region 404 is a substrate region with active devices, and region 405 is a substrate region without active devices.
- Vias 400 make an electrical connection from pad 54 to active devices in region 404 of I/O cell 50.
- Vias 401 make an electrical connection from pad 55 to active devices in region 404 of I/O cell 51.
- examples of specific materials have been mentioned in the context of FIG. 10, alternate embodiments are not limited to the mentioned materials and may use any materials that achieve the desired functionality.
- FIG. 11 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- This embodiment has the constraint that there is less space available in the vertical "y" direction (perpendicular to die edge 600) and more space available in the horizontal "x" direction (parallel to die edge 600).
- the dotted lines represent the space that would have been required to accommodate layout of the bond pads using conventional pad technology where the pad for an I/O cell is restricted from overlying a different I/O cell.
- power bond pads may have associated power probes pads.
- one or more I/O bond pads may not have associated probe pads.
- some or all power bond pads and some or all I/O bond pads may have associated probe pads.
- Alternate embodiments may use different shapes (e.g. square, diamond, rectangular, octagon, circular, oval, curved) which may benefit from the offset of the probe pads from the bond pads, and/or the offset of selected bond pads from each other.
- Alternate embodiments may use different pad shapes (e.g. octagon, pentagon) that may also benefit from rotating the orientation of the shape relative to the edge 600 of IC 10 in order to allow denser packing of the pads.
- combinations of different shapes may be used. Alternate embodiments may use any desired shape, rotation, staggering, or other orientation for bond pads and probe pads.
- FIG. 12 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- FIG. 12 is very similar to FIG. 11, except the shape of the power bond pads has been changed to a pentagon shape instead of a hexagon shape and the top of the probe pads have been flattened. This allows unused area at the edge of IC 10 to be added to the power bond pads, and unused area at the top of the I/O cells to be added to the probe pads. However, for manufacturability of some embodiments, it may be better not to use pads which have 90 degree angles at the corners of IC lO.
- FIG. 13 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- some of the bond pads and their associated probe pads are electrically connected by way of one or more traces 700-707 because other pads are interposed between the bond pad portion and its associated probe pad portion.
- Other bond pads and their associated probe pads do not need to use traces for electrical connection because they are contiguous with each other having no other pads interposed between them.
- One advantage to allowing the use of traces to electrically connect pads is that less space is required in the horizontal "x" direction. Thus space in the "y” direction may be used for the I/O cells instead of space in the "x” direction.
- a flat side of a hexagon is placed parallel to the die edge of IC 10. Alternate embodiments may use any desired shape, rotation, staggering, or other orientation for bond pads and probe pads.
- FIG. 13 represents the space that would have been required to accommodate layout of the bond pads using conventional pad technology where the pad for an I/O cell is restricted from overlying a different I/O cell. Note that the layout used in FIG. 13 requires more space in the vertical "y" direction, but require less space in the horizontal "x' direction. This may be an important advantage when the horizontal dimension "x" is more limited and constrained than the vertical dimension "y".
- FIG. 14 illustrates a top view of a pad portion 12 of integrated circuit 10 of FIG. 1 in accordance with an alternate embodiment of the present invention.
- pads 501-510 may be a probe pad and/or a bond pad. Note that the staggered arrangement of pads (bond and/or probe) allows for a denser layout.
- pads 501-505 are arranged radially around a center pad 506.
- the minimum distance (labeled "551") between the closest edge of pad 501 and the closest edge of pad 506 is at most 2 micrometers.
- the minimum distance (labeled "552") between the closest edge of pad 501 and the closest edge of pad 502 is at most 2 micrometers.
- the minimum distance (labeled "553") between the closest edge of pad 502 and the closest edge of pad 506 is at most 2 micrometers.
- the minimum distance (labeled "551") between the closest edge of pad 501 and the closest edge of pad 506 is at most 1 micrometers.
- the minimum distance (labeled "552") between the closest edge of pad 501 and the closest edge of pad 502 is at most 1 micrometers.
- the minimum distance (labeled "553") between the closest edge of pad 502 and the closest edge of pad 506 is at most 1 micrometers.
- pads 501, 502, and 506 are not layed out in a linear arrangement, but instead are staggered in a non-linear manner.
- a hexagonal shape is used, and the centers of pads (e.g. 501-505) also form a hexagonal shape 500 having sides of approximately equal length and having six angles of approximately 120 degrees each.
- one or more of the pads may not be implemented (e.g. the pad that would be placed directly above 506 in the vertical "y" direction).
- the denser packing or layout may be advantageous for any number of pad rows, where rows are considered to be arranged in the horizontal "x" direction. In regard to FIG.
- the "x” direction is the direction parallel to die edge 602 in the plane of the figure
- the "y” direction is the direction perpendicular to die edge 602 in the plane of the figure.
- some of the flat sides of the hexagonal shape 500 formed by the centers of the pads 501-505 are perpendicular to the edge of IC 10. Note that this arrangement of pads allows for an optimal packing of pads for ICs 10 in which there is more space in one direction (e.g. vertical "y") and less space in another direction (e.g. horizontal "x”) and also allows for a very dense packing of pads as the layout transitions around corners of IC 10.
- Alternate embodiments may locate some of the flat sides of the hexagon shapes (e.g. 500) formed by the centers of the bond pads (e.g. 501-505) parallel to the edge of IC 10. Note that this arrangement of pads allows for an optimal packing of pads for ICs 10 in which there is more space in one direction (e.g. horizontal "x") and less space in another direction (e.g. vertical "y").
- pads and associated I/O cells described in FIG. 1-10 and throughout this document may be combined in any desired manner and used with the pad layout features illustrated in FIGS. 11-14. Thus, it is intended that any and all of the features described herein may be mixed and matched and interchanged in any desired manner when designing an IC.
- An integrated circuit comprising: a first bond pad; a second bond pad; a first I/O cell having active circuitry selected from a group consisting of first output circuitry to directly provide a signal to the first bond pad and first input circuitry to directly receive a signal from the first bond pad; and a second I/O cell having active circuitry selected from a group consisting of second output circuitry to directly provide a signal to a second bond pad and second input circuitry to directly receive a signal from the second bond pad, wherein the first bond pad overlies at least a portion of the active circuitry of the second I/O cell.
- a bond pad width of the first bond pad is greater than an I/O cell width of the first I/O cell, the I/O cell width and the bond pad width measured along substantially parallel lines.
- first I/O cell has a first cell edge and a second cell edge, the second cell edge less than or equal to the first cell edge in length, and wherein the first bond pad is placed at a first distance from the first cell edge and the second bond pad is placed at a second distance from the first cell edge, the first distance being different than the second distance, and the second bond pad overlying at least a portion of the first bond pad.
- An integrated circuit comprising: a plurality of bond pads; and a plurality of I/O cells, each of the plurality of I/O cells corresponding to a corresponding bond pad of the plurality of bond pads and having active circuitry selected from a group consisting of input active circuitry for directly receiving a signal from the corresponding bond pad and output active circuitry for directly providing a signal to the corresponding bond pad, wherein: the plurality of I/O cells are arranged having a substantially constant pitch, the plurality of bond pads overlies at least a portion of the plurality of I/O cells, and the plurality of bond pads have a maximum pitch greater than the substantially constant pitch of the plurality of I/O cells.
- each bond pad of the plurality of bond pads comprise a wire bond region.
- a method for forming an integrated circuit comprising: forming a first I/O cell; forming a second I/O cell; forming a first bond pad corresponding to the first I/O cell, the first I/O cell having active circuitry selected from a group consisting of input active circuitry to directly receive signals from the first bond pad and output active circuitry to directly provide signals to the first bond pad; and forming a second bond pad corresponding to the second I/O cell over at least a portion of the first I/O cell, the second I/O cell having active circuitry selected from a group consisting of input active circuitry to directly receive signals from the second bond pad and output active circuitry to directly provide signals to the second bond pads.
- An integrated circuit die comprising: a first bond pad; a second bond pad; and a third bond pad, wherein a minimum distance between the first and second bond pad is at most 2 micrometers, a minimum distance between the second and third bond pad is at most 2 micrometers, and a minimum distance between the first and third bond pad is at most 2 micrometers.
- the integrated circuit die of item 23 further comprising a probe region adjacent at least one of the first, second, and third bond pads.
- the integrated circuit die of item 23 further comprising: an I/O cell having active circuitry selected from a group consisting of input circuitry for directly receiving a signal from one of the first bond pad, second bond pad, and third bond pad and output circuitry for directly providing a signal to the one of the first bond pad, second bond pad, and third bond pad.
- an I/O cell having active circuitry selected from a group consisting of input circuitry for directly receiving a signal from one of the first bond pad, second bond pad, and third bond pad and output circuitry for directly providing a signal to the one of the first bond pad, second bond pad, and third bond pad.
- each of the first, second, and third bond pads are regular hexagons having sides substantially equal in length and defining substantially equal angles.
- An integrated circuit die comprising: a plurality of bond pads arranged according to a hexagonal pattern, wherein at least five bond pads of the plurality of bond pads form at least part of a hexagon having six corners and six edges, wherein the centers of the at least five bond pads of the plurality of bond pads align with five of the six corners of the hexagon; an underlying metal layer below the plurality of bond pads; and a plurality of I/O cells, wherein a first bond pad of the at least five bond pads of the plurality of bond pads is connected to active circuitry of a corresponding I/O cell of the plurality of I/O cells with a via interconnect extending to the underlying metal layer.
- each bond pad of the plurality of bond pads is connected to active circuitry of a corresponding I/O cell of the plurality of I/O cells with a via interconnect extending to the underlying metal.
- each of the at least five bond pads are regular hexagons having sides substantially equal in length and defining substantially equal angles.
- An integrated circuit die comprising: a plurality of bond pads arranged according to a hexagonal pattern, wherein at least five bond pads of the plurality of bond pads form at least part of a first hexagon having six corners and six edges, wherein the centers of the at least five bond pads of the plurality of bond pads align with five of the six corners of the first hexagon; core circuitry; and a die edge, wherein the at least five bond pads are located between the core circuitry and the die edge, wherein at least one edge of the six edges of the first hexagon is substantially perpendicular to a first portion of the die edge nearest to the at least five bond pads.
- the integrated circuit die of item 42 further comprising: a plurality of I/O cells, wherein a first bond pad of the plurality of bond pads is connected to active circuitry of a corresponding I/O cell of the plurality of I/O cells, wherein at least a portion of the plurality of bond pads overlies at least a portion of the plurality of I/O cells, and wherein a bond pad width across the first bond pad is greater than an I/O cell width across the corresponding I/O cell of the plurality of I/O cells, the bond pad width and corresponding I/O cell width measured along substantially parallel lines.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07759809A EP2020026A4 (en) | 2006-05-16 | 2007-03-30 | Integrated circuit having pads and input/output (i/o) cells |
JP2009511129A JP2009537988A (en) | 2006-05-16 | 2007-03-30 | Integrated circuit having pad and input / output (I / O) cells |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/383,656 | 2006-05-16 | ||
US11/383,653 US7808117B2 (en) | 2006-05-16 | 2006-05-16 | Integrated circuit having pads and input/output (I/O) cells |
US11/383,653 | 2006-05-16 | ||
US11/383,656 US20070267748A1 (en) | 2006-05-16 | 2006-05-16 | Integrated circuit having pads and input/output (i/o) cells |
Publications (2)
Publication Number | Publication Date |
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WO2007136932A2 true WO2007136932A2 (en) | 2007-11-29 |
WO2007136932A3 WO2007136932A3 (en) | 2009-03-26 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US2007/065619 WO2007136932A2 (en) | 2006-05-16 | 2007-03-30 | Integrated circuit having pads and input/output (i/o) cells |
Country Status (4)
Country | Link |
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EP (1) | EP2020026A4 (en) |
JP (1) | JP2009537988A (en) |
KR (1) | KR20090025239A (en) |
WO (1) | WO2007136932A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009302136A (en) * | 2008-06-10 | 2009-12-24 | Panasonic Corp | Semiconductor integrated circuit |
EP2242095A1 (en) * | 2007-12-28 | 2010-10-20 | Fujitsu Semiconductor Limited | Semiconductor device and its manufacturing method |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI640047B (en) * | 2013-02-01 | 2018-11-01 | 新力股份有限公司 | Semiconductor integrated circuit |
DE102013215580A1 (en) | 2013-08-07 | 2015-02-12 | Orgentec Diagnostika Gmbh | 25-OH Vitamin D derivatives for the determination of vitamin D metabolites |
WO2023047599A1 (en) * | 2021-09-27 | 2023-03-30 | 日本電信電話株式会社 | Optical communication device |
WO2024042698A1 (en) * | 2022-08-26 | 2024-02-29 | 株式会社ソシオネクスト | Semiconductor integrated circuit device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
US6323559B1 (en) * | 1998-06-23 | 2001-11-27 | Lsi Logic Corporation | Hexagonal arrangements of bump pads in flip-chip integrated circuits |
US6833620B1 (en) * | 2000-11-28 | 2004-12-21 | Ati Technologies, Inc. | Apparatus having reduced input output area and method thereof |
US6717270B1 (en) * | 2003-04-09 | 2004-04-06 | Motorola, Inc. | Integrated circuit die I/O cells |
-
2007
- 2007-03-30 JP JP2009511129A patent/JP2009537988A/en not_active Withdrawn
- 2007-03-30 EP EP07759809A patent/EP2020026A4/en not_active Withdrawn
- 2007-03-30 WO PCT/US2007/065619 patent/WO2007136932A2/en active Application Filing
- 2007-03-30 KR KR1020087030486A patent/KR20090025239A/en not_active Application Discontinuation
Non-Patent Citations (1)
Title |
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See references of EP2020026A4 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2242095A1 (en) * | 2007-12-28 | 2010-10-20 | Fujitsu Semiconductor Limited | Semiconductor device and its manufacturing method |
EP2242095A4 (en) * | 2007-12-28 | 2013-06-05 | Fujitsu Semiconductor Ltd | Semiconductor device and its manufacturing method |
US8519551B2 (en) | 2007-12-28 | 2013-08-27 | Fujitsu Semiconductor Limited | Semiconductor device with I/O cell and external connection terminal and method of manufacturing the same |
JP2009302136A (en) * | 2008-06-10 | 2009-12-24 | Panasonic Corp | Semiconductor integrated circuit |
US8669593B2 (en) | 2008-06-10 | 2014-03-11 | Panasonic Corporation | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
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WO2007136932A3 (en) | 2009-03-26 |
EP2020026A4 (en) | 2010-06-09 |
EP2020026A2 (en) | 2009-02-04 |
JP2009537988A (en) | 2009-10-29 |
KR20090025239A (en) | 2009-03-10 |
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