KR20140058166A - Liquid crystal display device - Google Patents

Abstract

The present invention provides a liquid crystal display device which includes: a liquid crystal panel; a data driving unit which is connected to a data line of the liquid crystal panel; a power converting unit which converts a first power voltage from a power supply unit into a second power voltage and outputs the converted voltage; and a power control unit which outputs a discharge control signal to supply a gate high voltage through a gate line and to supply a ground voltage level through a data line for N frame sections if the power source of the power supply unit is abnormally turned off. Wherein, the N is an integer and is 1 or more.

Description

[0001] The present invention relates to a liquid crystal display device,

An embodiment of the present invention relates to a liquid crystal display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display and a plasma liquid crystal display (PDP) ) Have been increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

Recently, with the development of a high-resolution model, a liquid crystal display device has been implemented with various structures and various driving methods. On the other hand, in some of the liquid crystal display devices, when power is normally turned off, the charges charged in all the subpixels are discharged in accordance with the off sequence. However, when the power source is abnormally turned off, the charges that have been charged in all the subpixels remain without being discharged. In this case, DC stress is applied to the subpixels microscopically and macroscopically causes a flicker phenomenon on the liquid crystal panel.

Therefore, if the number of times of power on / off is increased by a normal method and an abnormal method for a short time, a discharge for charges remaining in the sub-pixel is not efficiently performed and is continuously accumulated inside, The flicker phenomenon is severely induced, and improvement thereof is required.

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device capable of improving a flicker phenomenon even when the number of times of power on / off is increased by a normal method and an abnormal method for a short period of time.

According to an aspect of the present invention, A data driver connected to a data line of the liquid crystal panel; A gate driver connected to a gate line of the liquid crystal panel; A power conversion unit converting the first power voltage output from the power supply unit to a second power voltage and outputting the second power voltage; And a power supply control unit for outputting a discharge control signal so that a gate high voltage is supplied through the gate line and a ground voltage level is supplied through the data line during N (N is an integer equal to or greater than 1) frame period when the power of the power supply unit is abnormally turned off, And a liquid crystal display device.

The electric charge remaining in the liquid crystal panel can be discharged through the data line and the common voltage line having the equal potential level corresponding to the ground voltage by the discharge control signal.

The power control unit includes a monitor unit for detecting an output voltage of the power conversion unit and determining whether the power supply unit is turned off in an abnormal state, a discharge control unit for outputting a discharge control signal in response to the discharge control unit control signal output from the monitor unit, . ≪ / RTI >

The discharge control signal may include a gate control signal for switching all the gate signals output through the gate driver to a gate high voltage and a mux control signal for turning on all the output control transistors included in the data driver.

The monitor unit may detect a first drive voltage and a second drive voltage supplied to the data driver and determine whether the power supply unit is turned off in an abnormal state.

The discharge control unit may switch the gate control signal and the mux control signal to the gate high voltage in response to the discharge control unit control signal and output the same.

The power conversion unit may include a gate high voltage output unit having a voltage holding unit for maintaining and outputting a gate high voltage during the N frame period, and a gate low voltage output unit for outputting a gate low voltage.

The discharge control unit includes switches connected at one end and the other end between the mux control signal lines, an inverter having one end connected to the discharge control unit control signal supply terminal and the other end connected to the selection terminal of the switches, And a diode connected to a second electrode of the control transistor and to which the cathode electrode is connected at the other end of the switches connected to the mux control signal lines. have.

When the power supply of the power supply unit is turned on, the power supply control unit supplies a gate high voltage through the gate line for M (M is an integer equal to or greater than 1) frame period before the display ON period and supplies the gate high voltage through the common voltage line connected to the data line and the liquid crystal panel It is possible to output the discharge control signal so that the ground voltage level is supplied.

The discharge control signal may be supplied immediately before the display section of the liquid crystal panel is turned on.

It is an object of the present invention to provide a liquid crystal display device capable of improving the flicker phenomenon even when the number of times of turning on and off the power by a normal method and an abnormal method is shortened for a short time by efficiently discharging the electric charge remaining in the liquid crystal panel have.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention;
Fig. 2 is a diagram illustrating a configuration example of the power conversion unit shown in Fig. 1. Fig.
FIG. 3 is a schematic view showing the subpixel shown in FIG. 1; FIG.
4 is a waveform diagram for explaining a discharge sequence when the power supply unit is abnormally turned off;
FIGS. 5 and 6 are diagrams for explaining differences depending on the presence or absence of a discharge sequence. FIG.
7 is a diagram illustrating an example of the configuration of a third power conversion unit;
8 is a diagram illustrating a configuration example of a power control unit;
9 is a diagram showing an example of the configuration of a discharge control section.
10 is a graph illustrating flicker recovery in a structure to which the present invention is applied and a structure in which the present invention is not used.
11 is a view showing a discharge sequence after the power supply unit is turned on;
12 is a waveform diagram for explaining a discharge sequence after the power supply unit is turned on;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a display apparatus according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of a power conversion unit shown in FIG. 1, Fig.

The display device according to an embodiment of the present invention includes a power supply unit 110, a power conversion unit 120, a timing control unit 130, a gate driving unit 140, a data driving unit 150, a liquid crystal panel 160, (170) and a power control unit (180).

The power supply unit 110 may be configured in various forms according to the size of the liquid crystal panel 160. When the liquid crystal panel 160 is large, the power supply unit 110 may be configured as a circuit that converts an AC voltage to a DC voltage and outputs the DC voltage. When the liquid crystal panel 160 is small, the power supply unit 110 may be constituted by a battery.

The power conversion unit 120 converts the first power supply voltage output from the power supply unit 110 into a second power supply voltage and outputs the second power supply voltage. The power conversion unit 120 may include a low dropout (LDO), a charge pump, a power chip, or the like, and may output various voltages. The power conversion unit 120 may include a first power conversion unit 121, a second power conversion unit 123, and a third power conversion unit 125.

The first power source conversion unit 121 is connected to the timing controller 130, the external memory unit 120, the gate driver 140, the data driver 150, the liquid crystal panel 160 and the backlight unit 170, (VCC) and the ground voltage (GND). The second power conversion unit 123 may output the first driving voltage DDVDH and the second driving voltage DDVDL to be supplied to the data driver 150. The third power conversion unit 125 may output the gate high voltage VGH and the gate low voltage VGL to be supplied to the gate driver 140 and the common voltage VCOM to be supplied to the liquid crystal panel 160. [ And may be output by a common voltage output unit configured separately in the case of the common voltage VCOM.

The timing controller 130 controls the timing of the data driver 140 and the gate of the data driver 140 using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. And controls the operation timing of the driving unit 130.

The timing controller 130 outputs a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150. [ The timing controller 130 supplies the data driver 150 with the data signal DATA along with the data timing control signal DDC.

The gate driver 140 outputs a gate signal in response to the gate timing control signal GDC output from the timing controller 130. The gate driver 140 supplies gate signals to the sub-pixels SP included in the liquid crystal panel 160 through the gate lines GL. The gate signal includes a gate high voltage VGH (or a gate-on voltage) for turning on the switching transistor of the liquid crystal panel 160 and a gate-low voltage VGL (or gate-off voltage) for turning off the switching transistor.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC output from the timing controller 130 and converts the sampled data signal into a gamma reference voltage. The data driver 150 supplies the data signal DATA to the sub-pixels SP included in the liquid crystal panel 160 through the data lines DL.

The backlight unit 170 provides light to the liquid crystal panel 160. The backlight unit 170 includes an LED (Light Emitting Diode), an LED driving unit, a light guide plate, an optical sheet, and the like. The backlight unit 170 may be an edge type, a dual type, or a direct type. The edge type is a structure in which LEDs are disposed on one side of the liquid crystal panel 160. The dual type is a structure in which LEDs are disposed on both sides of the liquid crystal panel 160. The direct type is a bottom side of the liquid crystal panel 160 LEDs are arranged.

The liquid crystal panel 160 displays an image corresponding to the gate signal output from the gate driver 140 and the data signal DATA output from the data driver 150. The liquid crystal panel 160 includes a transistor array substrate, a color filter substrate, and a liquid crystal layer Clc. The transistor array substrate includes a switching transistor SW and a storage capacitor Cst. The color filter substrate includes a color filter and a black matrix.

The liquid crystal panel 160 is implemented in a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode or ECB (Electrically Controlled Birefringence) mode. The pixel electrode 1 for driving the liquid crystal layer Clc is formed on the transistor array substrate while the common electrode 2 is formed on the transistor array substrate in accordance with the mode of implementation of the liquid crystal layer Clc, .

On the other hand, the liquid crystal panel 160 is based on low temperature polysilicon (LTPS) or amorphous silicon (a-Si). The low-temperature polysilicon base can output the R data signal, the G data signal and the B data signal in a time-division manner, unlike the amorphous silicon (a-Si) base. According to this method, the R data signal, the G data signal, and the B data signal can be selectively supplied through one data line corresponding to the mux control signal MUX, thereby reducing the number of data lines. Hereinafter, the liquid crystal panel 160 will be described based on low-temperature polysilicon.

The power control unit 180 outputs a discharge control signal DCS for controlling the gate driving unit 140 and the data driving unit 150 when the power supply unit 110 is turned off in an abnormal state. The gate driving unit 140 and the data driving unit 150 are driven by the discharge control signal DCS output from the power source control unit 180 so that the discharge sequence for discharging the charges charged in the sub pixels SP of the liquid crystal panel 160 . When the power supply unit 110 is abnormally turned off, the charges charged in all the sub-pixels SP of the liquid crystal panel 160 are discharged in accordance with the discharge sequence.

The discharge sequence after the power supply unit 110 is abnormally turned off will be described in detail as follows.

FIG. 4 is a waveform diagram for explaining a discharge sequence when the power supply unit is abnormally turned off, and FIGS. 5 and 6 are diagrams for explaining the difference depending on the presence or absence of a discharge sequence.

- Display ON -

The first driving voltage DDVDH, the second driving voltage DDVDL, the reset signal Reset, the gate control signal GOA, the mux control signal MUX and the gate high voltage VGH during the display ON period (Display ON) , The gate low voltage (VGL), the data signal (DATA), and the common voltage (VCOM) are maintained in a normal state.

In this way, if each normal circuit maintains a normal output and the power supply unit is turned off abnormally (Abnormal Power Off), then the discharge sequence is performed. The discharge period during which the discharge sequence is performed is performed between the display ON period and the display OFF period.

- Discharge section -

A discharge sequence for discharging the electric charge charged in the sub-pixels of the liquid crystal panel during the discharge interval is performed. When the power supply unit is abnormally turned off (Abnormal Power Off), the power control unit maintains the gate control signal GOA and the mux control signal MUX at a logic high level for N frames (where N is an integer equal to or greater than 1). At this time, the first driving voltage DDVDH and the second driving voltage DDVDL gradually fall to a level corresponding to the ground voltage GND with respect to the other voltages. Then, the reset signal Reset is switched from logic low to logic high. Then, the data signal DATA and the common voltage VCOM drop to a level corresponding to the ground voltage GND.

- Display Off -

After the discharge period for the N frames has passed, the first drive voltage DDVDH, the second drive voltage DDVDL, the gate control signal GOA, the mux control signal MUX, the gate high voltage VGH, The voltage VGL, the data signal DATA, and the common voltage VCOM drop to a level corresponding to the ground voltage GND.

[Invention: Figure 5]

The present invention performs a discharge sequence after the power is abnormally turned off. When the discharge sequence is performed, the gate driver 140 applies a gate high voltage VGH to turn on all the switching transistors SW of the liquid crystal panel in response to a gate control signal GOA of a logic high Output through all gate lines. The data driver 150 turns on all the output control transistors TM included therein corresponding to the logic high mux control signal MUX.

The switching transistor SW of the liquid crystal panel becomes a gate high state, that is, turned on by the discharge sequence. Accordingly, the charge charged in the subpixel (storage capacitor, etc.) of the liquid crystal panel is discharged through the data line and the common voltage line having the equal potential level corresponding to the ground voltage (GND). In the present invention, since two discharge paths are set, a fast discharge is performed.

[Comparative Example: Fig. 6]

In the comparative example, the discharge sequence is not performed after the power source is abnormally turned off. In the comparative example, since the discharge sequence is not performed, the gate control signal GOA of the ground voltage GND causes the switching transistor SW to be in a gate floating state, that is, turned off. All the output control transistors TM are turned off by the mux control signal MUX of the ground voltage GND. Accordingly, the charge charged in the sub-pixel (storage capacitor, etc.) of the liquid crystal panel is discharged through the common voltage line. In the comparative example, since one discharge path is set, a fast discharge is not performed.

Hereinafter, the configuration of the circuit for performing the discharge sequence after the power supply unit is abnormally turned off will be described.

FIG. 9 is a diagram illustrating a configuration of a discharge control unit, and FIG. 10 is a diagram illustrating a structure in which the present invention is applied and a structure in which the present invention is not used. FIG. 7 is a diagram showing a configuration example of a third power source conversion unit, In the graph of FIG.

The third power conversion section 125 includes a gate high voltage output section 125a for outputting the gate high voltage VGH and a gate low voltage output section 125b for outputting the gate low voltage VGL.

The gate high voltage output unit 125a includes a first rectifier diode LD1 and a first capacitor C2 for outputting a positive voltage of the first voltage source V1. The gate low voltage output unit 125b includes a second rectifier diode LD2 and a second capacitor C2 for outputting a negative voltage of the second voltage source V2. The configurations of the gate high voltage output portion 125a and the gate low voltage output portion 125b are schematically shown as rectifier diodes D1 and D2 and capacitors C1 and C2. However, the configurations of the gate high voltage output section 125a and the gate low voltage output section 125b are intended to be understood only, but are not limited thereto.

The gate high voltage output portion 125a includes a voltage holding portion 126 unlike the gate low voltage output portion 125b. The voltage holding unit 126 serves to maintain the gate high voltage VGH for N frames. The voltage holding portion 126 is composed of a first resistor R1, a second resistor R2 and a dummy capacitor Cc. The configuration of the voltage holding unit 126 is for the sake of understanding, but is not limited thereto.

With such a configuration, the gate high voltage VGH remains in the logic high state for N frames even when the power supply unit is abnormally turned off.

The power supply control unit 180 includes a monitor unit 181 and a discharge control unit 185. The monitor unit 181 detects the output voltage Vout of the power conversion unit such as the first drive voltage DDVDH and the second drive voltage DDVDL to determine whether the power supply unit 110 is turned off in an abnormal state do. Here, the fact that the power supply unit 110 is turned off in an abnormal state means that the AC voltage supplied to the power supply unit 110 is cut off or the battery is disconnected. The monitor unit 181 outputs a discharge control unit control signal APO when the level of the first drive voltage DDVDH and the second drive voltage DDVDL falls below a predetermined range.

The discharge control unit 185 generates a discharge control signal including the mux control signals MUX _R , MUX _G , and MUX _B and the gate control signal GOA in response to the discharge control unit control signal APO output from the monitor unit 181, (DCS). The discharge control unit 185 includes first to fifth switches SW1 to SW5, a control transistor Tr, an inverter INV and first to fifth diodes D1 to D5.

The control transistor Tr has a gate electrode connected to the discharge control unit control signal supply terminal, a gate high voltage supply terminal connected to the first electrode, and a second electrode connected to the anode electrode of the first through fifth diodes D1 to D5. do.

The inverter INV has one end connected to the discharge control unit control signal supply terminal and the other end connected to the selection terminal of the first through fifth switches SW1 through SW5.

One end and the other end of the first switch SW1 are connected between the Rmux control signal lines. The second switch SW2 is connected between the Gmux control signal line and the other end. The third switch SW3, One end and the other end of the fourth switch SW4 are connected between the first and second clock signal lines, and the fifth switch SW5 is connected between the second clock signal line One end is connected to the other end.

The first diode D1 is connected to the cathode of the first switch SW1 connected to the Rmux control signal line and the second diode D2 is connected to the Gmux control signal line of the second switch SW2 And a cathode electrode is connected to the other end of the third diode D3. The cathode electrode of the third diode D3 is connected to the other end of the third switch SW3 connected to the B mux control signal line. The fourth diode D4 is connected to the first clock signal line The cathode of the fourth switch SW4 is connected to the cathode of the fifth switch SW5 and the cathode of the fifth diode D5 is connected to the cathode of the fifth switch SW5 connected to the second clock signal line.

With the above arrangement, the discharge control section 185 operates as follows.

When the discharge control unit control signal APO is supplied (for example, a logic high signal), the first to fifth switches SW1 to SW5 are turned off by the inverter INV. As the first to fifth switches SW1 to SW5 are turned off, existing signals output through the mux control signal line and the gate control signal line are cut off.

Instead, as the control transistor Tr is turned on, the mux control signals MUX _R , MUX _G , and MUX _B and the gate control signal GOA corresponding to the gate high voltage VGH of the logic high are applied to the mux control signal line And output through the gate control signal line. Here, the gate control signal GOA includes the first and second clock signals CLK1 and CLK2 as an example. However, the signal for switching all gate signals output through the gate driver to the gate high voltage (VGH) is not limited thereto.

On the other hand, when the discharge control unit control signal APO is not supplied (for example, a logic low signal), the first to fifth switches SW1 to SW5 are turned on by the inverter INV. As the first to fifth switches SW1 to SW5 are turned on, the existing signal output through the mux control signal line and the gate control signal line is maintained.

In the meantime, as a result of testing the flicker recovery degree in the structure using the discharge sequence according to the present invention and the unused structure, the structure using the discharge sequence according to the present invention was able to discharge the residual charge in the same or similar manner as the normal discharge sequence. See the two graphs shown in Figure 10)

In the experiment, the flicker was measured at intervals of 1 minute after the power was turned off in an abnormal manner. Specifically, in the initial stage, after the power was supplied, the flicker was measured. After 5 minutes of operation, the power was turned off in an abnormal manner, and then the power was turned on again after 30 seconds. At this time, the test pattern displayed on the liquid crystal panel was a mid gray pattern. The mid gray pattern is an image in which the presence of flicker is visually perceived because the change in luminance is large even in a minute voltage change.

On the other hand, if the number of times the power is turned on / off is increased by a normal method or an abnormal method for a short time, the electric charge remaining in the sub-pixel is not completely discharged and accumulated continuously inside the sub-pixel when the power is turned on. To improve this, the discharge sequence is applied even after the power supply unit is turned on.

The discharge sequence after the power supply unit is turned on will be described in detail as follows.

FIG. 11 is a diagram showing a discharge sequence after the power supply unit is turned on, and FIG. 12 is a waveform diagram for explaining a discharge sequence after the power supply unit is turned on.

- Power ON Sequence -

When the power supply unit is turned on, the power on sequence proceeds. The preliminary operation of the device for outputting the data signal DATA and the common voltage VCOM as well as the vertical synchronization signal Vsync during the power ON sequence period is performed. At this time, the liquid crystal panel is turned off.

- Discharge section -

The discharge sequence proceeds for M (M is an integer equal to or greater than 1) frame before the liquid crystal panel is turned on. During the discharge period (Discharge), the data signal DATA and the common voltage VCOM are temporarily set to a stop or a halt level. For example, the data signal DATA and the common voltage VCOM may be set to a level corresponding to the ground voltage GND. Then, the charges remaining in the data line and the common voltage line are discharged through these lines. At this time, the gate control signal GOA and the mux control signal MUX can be set to a logic high level. At this time, the liquid crystal panel is turned off.

- Display ON -

The operation of the device for outputting the data signal DATA or the common voltage VCOM during the display ON period after the discharge period is resumed. At this time, the gate control signal GOA and the mux control signal MUX show a normal output. At this time, the liquid crystal panel is turned on.

As a result of experimenting with the structure of the discharge sequence according to the present invention, it is possible to improve the level of flicker occurring after the power source is turned on.

[Table 1]

In the experiment shown in Table 1, the M frame defining the discharge interval is set to 2 frames, and then the power is turned on and after a certain delay time (delay: 15 seconds, 5 seconds, 3 seconds, 2 seconds, 1 second) The flicker was measured after repeating the process of turning off normally for about 2 hours. According to the measurement results, the level of flicker is improved by the decrease of the voltage difference between the turn-on and turn-off states of the switching transistor. At this time, the test pattern displayed on the liquid crystal panel used a user interface.

On the other hand, the discharge sequence after the power supply unit is turned on may also be performed by the power supply control unit described in Figs. The M frame for discharging the remaining charge in the liquid crystal panel can be set to at least one frame and is set to not exceed a maximum of five frames.

When the normal power source is abnormally turned off, the charge charged in the liquid crystal panel is not discharged but remains. In this case, DC stress is applied to the subpixels microscopically and macroscopically causes a flicker phenomenon on the liquid crystal panel.

Therefore, if the number of times of power on / off is increased by a normal method and an abnormal method for a short time, the discharge for the electric charge remaining in the liquid crystal panel is not completely performed but accumulated continuously.

However, according to the present invention, flicker phenomenon on the liquid crystal panel is hardly caused even when the number of times of power on / off is increased by a normal method and an abnormal method. This is because even if the power is turned off in an abnormal manner, the discharge sequence is applied and the discharge sequence is applied even after the power is turned on.

On the other hand, when the power is normally off and when the power is abnormally turned off, there is a difference in electric charge remaining on the liquid crystal panel. Therefore, a frame for discharging the electric charge remaining in the liquid crystal panel can be set correspondingly.

As described above, the present invention provides a liquid crystal display device capable of improving the flicker phenomenon even when the number of times of power on / off is increased by a normal method and an abnormal method for a short time by efficiently discharging the electric charge remaining in the liquid crystal panel .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110: power supply unit 120: power conversion unit
130: timing controller 140: gate driver
150: data driver 160: liquid crystal panel
170: backlight unit 180: power source control unit
DCS: discharge control signal GOA: gate control signal
MUX: Mux control signal 125a: Gate high voltage output section
126: voltage holding unit 125b: gate low voltage output unit
Tr: Control transistor INV: Inverter
SW1 to SW5: First to fifth switches
D1 to D5: First to fifth diodes

Claims (10)

A liquid crystal panel;
A data driver connected to a data line of the liquid crystal panel;
A gate driver connected to a gate line of the liquid crystal panel;
A power conversion unit converting the first power voltage output from the power supply unit to a second power voltage and outputting the second power voltage; And
When a power supply of the power supply unit is abnormally turned off, a gate high voltage is supplied through the gate line for N (where N is an integer equal to or greater than 1) frame period, and a discharge control signal is outputted so that a ground voltage level is supplied through the data line A liquid crystal display comprising a power controller. The method according to claim 1,
Wherein the electric charge remaining in the liquid crystal panel is discharged through the common voltage line and the data line having an equal potential level corresponding to the ground voltage by the discharge control signal. The method according to claim 1,
The power control unit
A monitor unit for detecting an output voltage of the power conversion unit and determining whether the power supply unit is turned off in an abnormal state,
And a discharge control unit for outputting the discharge control signal in response to a discharge control unit control signal output from the monitor unit. The method of claim 3,
The discharge control signal
A gate control signal for switching all gate signals output through the gate driver to a gate high voltage,
And a mux control signal for turning on all the output control transistors included in the data driver. The method of claim 3,
The monitor unit
Wherein the controller determines whether the power supply unit is turned off in an abnormal state by detecting a first drive voltage and a second drive voltage supplied to the data driver. 5. The method of claim 4,
The discharge control unit
And switches the gate control signal and the mux control signal to the gate high voltage in response to the discharge control unit control signal. The method according to claim 6,
The power conversion unit
A gate high voltage output unit having a voltage holding unit for holding and outputting the gate high voltage during the N frame period;
And a gate low voltage output section for outputting a gate low voltage. The method according to claim 6,
The discharge control unit
Switches whose one end and the other end are connected between the mux control signal lines,
An inverter having one end connected to the discharge control unit control signal supply terminal and the other end connected to the selection terminal of the switches,
A control transistor having a gate electrode connected to the discharge control unit control signal supply terminal and a first electrode connected to the gate high voltage supply terminal,
And diodes having an anode electrode connected to the second electrode of the control transistor and a cathode electrode connected to the other end of the switches connected to the mux control signal lines. The method according to claim 1,
The power control unit
When a power source of the power supply unit is turned on, a gate high voltage is supplied through the gate line for M (M is an integer equal to or greater than 1) frame period before a display-on period, and a common voltage line connected to the data line and the liquid crystal panel And a discharge control signal is outputted so that a ground voltage level is supplied through the discharge cell. 10. The method of claim 9,
The discharge control signal
Wherein the liquid crystal display panel is supplied immediately before a section in which the display of the liquid crystal panel is turned on.

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