KR20080064928A - Liquid crystal display and method for eliminating afterimage thereof - Google Patents

Abstract

A liquid crystal display device and a method for removing an afterimage therein are provided to remove the afterimage during separation of a battery by applying a common voltage to a data line. A liquid crystal display device includes a power supply unit(160), a gate driving unit(120), and a discharge unit(112). The power supply unit detects blocking of an external power voltage supply and provides it as a discharge signal. The gate driving unit simultaneously provides a gate driving signal to a plurality of gate lines in response to the discharge signal. The discharge unit provides a command voltage to a plurality of data lines in response to the discharge signal. The gate driving includes a driving transistor and an inverter corresponding to the gate lines.

Description

Afterimage removal method of a liquid crystal display device and a liquid crystal display device {LIQUID CRYSTAL DISPLAY AND METHOD FOR ELIMINATING AFTERIMAGE THEREOF}

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention;

FIG. 2 is an exemplary circuit diagram illustrating a discharge unit shown in FIG. 1;

3 is an exemplary circuit diagram illustrating an output buffer shown in FIG. 1.

4 is an exemplary circuit diagram illustrating a power off detection unit illustrated in FIG. 1;

FIG. 5 is a timing diagram for describing an operation of the liquid crystal display illustrated in FIG. 1.

<Code Description of Main Parts of Drawing>

100: liquid crystal display 110: liquid crystal panel

112: discharge unit 120: data driver

130: gate driving circuit 132: output buffer

134: level shifter 140: gamma voltage generator

150: timing controller 160: power supply

162: pao off detection unit

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display and a method for removing an afterimage when the external power is cut off.

In general, a liquid crystal display device includes a thin film transistor substrate and a color filter substrate each having a field generating electrode disposed so that the surface on which the electrode is formed face each other, injecting a liquid crystal between the two substrates, and then applying a voltage to the electrode to generate an electric field. By moving the liquid crystal by this, it is an apparatus for representing the image by the transmittance of light that varies accordingly.

Such liquid crystal displays are widely used in mobile information devices such as portable personal digital assistants and mobile phones as well as personal computers and televisions due to their ultra-thin, light weight, high reliability, and low power consumption.

However, in the liquid crystal display device used in the conventional mobile information device, when the battery is removed by the user or an external shock during use, the power supplied to the liquid crystal display device is interrupted and the operation is stopped, but there is a problem that an afterimage remains on the liquid crystal panel.

This is because when the battery is removed and the power supply is suddenly stopped, all the gate lines except the gate line selected immediately before the battery are removed are in the gate-off voltage state to maintain the gray scale display voltage accumulated in the pixel capacitor of the liquid crystal panel. . That is, except for the gate line selected just before the battery is removed, the passage for discharging the gradation display voltage accumulated in the pixel capacitor is blocked, and the gradation display voltage is maintained until all the discharges are caused by natural discharge due to leakage current. Will remain.

However, the thin film transistor formed in the liquid crystal panel has a difference in leakage current due to a characteristic difference generated in the process, for example, a process spread of the threshold value Vth of the thin film transistor, and thus, a discharge state is changed for each pixel capacitor. There is a problem that can be perceived as noise.

Accordingly, the present invention has been made to solve the conventional problems, and provides a liquid crystal display and a method for removing all residual images by driving all gate lines at the same time when a battery removal is detected and inputting a common voltage to the data lines. There is a purpose.

In order to achieve the above object, the liquid crystal display device of the present invention, the power supply for detecting the interruption of the external power supply voltage to provide a discharge signal; A gate driver configured to simultaneously provide a gate driving signal to a plurality of gate lines in response to the discharge signal; And a discharge unit configured to provide a common voltage to a plurality of data lines in response to the discharge signal.

The gate driver may include a driving transistor and an inverter respectively corresponding to the plurality of gate lines, wherein the driving transistor includes a control terminal provided with the discharge signal, an output terminal connected to an input terminal of the inverter, and a gate-off voltage. And a provided input terminal, wherein the inverter has an input terminal connected to an output terminal of the driving transistor and an output terminal connected to the gate line.

The discharge unit may include a switching transistor corresponding to each of the plurality of data lines, wherein the switching transistor includes a control terminal provided with the discharge signal, an output terminal connected to the data line, and an input terminal provided with the common voltage. It includes.

The power supply unit may include a signal generation transistor having a source and a drain-in connected to a power supply terminal and a ground terminal and providing the power supply voltage to a gate.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a plurality of gate lines, a plurality of data lines, a pixel capacitor formed at an intersection of the plurality of gate lines and a plurality of data lines, and having a common voltage applied to one end thereof, and provided to the gate line. A liquid crystal panel comprising a thin film transistor connecting the data line and the other end of the pixel capacitor in response to a gate driving signal; A timing controller providing a gate control signal in response to an external signal; A power supply unit configured to receive an external power supply voltage, generate a driving voltage including the common voltage, detect a supply cutoff of the external power supply voltage, and provide a discharge signal; A gate driver configured to sequentially provide the gate driving signal to the plurality of gate lines in response to the gate control signal, and simultaneously provide the gate driving signal to the plurality of gate lines in response to the discharge signal; And a discharge unit configured to apply the common voltage to the plurality of data lines in response to the discharge signal.

The driving voltage may include a gate on voltage and a gate off voltage, and the gate driver may provide the gate driving signal having the gate on voltage and the gate off voltage levels.

The gate driver may receive a first gate control signal from the timing controller and receive a gate on voltage and a gate off voltage from the power supply to generate a second gate control signal having the gate on voltage and the gate off voltage levels. Level shifter; A gate driving circuit sequentially providing the gate driving signal to the plurality of gate lines in response to the second gate control signal; And an output buffer configured to simultaneously provide the gate driving signal to the plurality of gate lines in response to the discharge signal.

In addition, the discharge unit, the gate driving circuit, and the output buffer are preferably formed in the liquid crystal panel.

The output buffer may include a switching transistor, a driving transistor, and an inverter respectively corresponding to the plurality of gate lines, wherein the switching transistor includes a control terminal provided with the discharge signal, an input terminal connected to the gate driving circuit, and the gate. And an output terminal connected to a line, wherein the driving transistor includes a control terminal provided with the discharge signal, an output terminal connected to an input terminal of the inverter, and an input terminal provided with a gate-off voltage. It is preferable to be connected to the output terminal of the transistor and the output terminal to the gate line.

In addition, it is preferable that the switching transistor is an NMOS transistor, and the driving transistor is a PMOS transistor.

The discharge unit may include a switching transistor corresponding to each of the plurality of data lines, and the switching transistor may include a control terminal provided with the discharge signal, an output terminal connected to the data line, and an input terminal provided with the common voltage. Include.

In addition, the switching transistor is preferably a PMOS transistor.

The power supply unit may include a signal generation transistor having a source and a drain-in connected to a power supply terminal and a ground terminal and providing the power supply voltage to a gate.

The driving voltage may include an analog power supply voltage, and the liquid crystal display according to the present invention may include a gamma voltage generator configured to generate a gamma voltage by dividing the analog power supply voltage; And a data driver configured to provide a gray scale display voltage to the plurality of data lines using the gamma voltage.

In an afterimage removing method of a liquid crystal display of the present invention, a plurality of gate lines, a plurality of data lines, pixel capacitors respectively formed at intersections of the plurality of gate lines and the plurality of data lines, and one end of which is applied with a common voltage, An afterimage removal method of a liquid crystal display including a thin film transistor connecting the data line and the other end of the pixel capacitor in response to a gate driving signal provided to a gate line. Providing a detecting step; A gate driving step of simultaneously providing the gate driving signals to the plurality of gate lines in response to the discharge signal; And discharging the common voltage to the plurality of data lines in response to the discharge signal.

Here, the detecting step may include a signal generation transistor having a source and a drain connected to a power supply terminal and a ground terminal, a gate connected to the external power supply voltage, and a source connected to the power supply terminal operating as an output terminal for providing the discharge signal. And using the discharge signal to output the discharge signal when the external power supply voltage is cut off.

The gate driving step may include inverting a gate-off voltage to provide the gate driving signal when the discharge signal is enabled.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. As illustrated in FIG. 1, the liquid crystal display device 100 according to an exemplary embodiment of the present invention includes a liquid crystal panel 110, a data driver 120, a gate driver 130, 132, 134, a gamma voltage generator 140, and a timing. The controller 150 and the power supply unit 160 are included.

The liquid crystal panel 110 includes a color filter substrate on which a color filter and a common electrode are formed, a thin film transistor substrate on which a thin film transistor (TFT) is formed, and a liquid crystal filled between the color filter substrate and the thin film transistor substrate.

The thin film transistor substrate includes a plurality of gate lines GL1 through GLn, a plurality of data lines DL1 through DLm, a plurality of gate lines GL1 through GLn, and a plurality of data lines. A thin film formed at the intersections of (DL1, ..., DLm) to provide the gray scale display voltage to the pixel capacitor Clc in response to the gate capacitor voltage (Clc) and the gate-on voltage (VON) that charge the gray scale display voltage. And a transistor (TFT). The thin film transistor TFT includes a gate connected to the gate line GL1, a source connected to the data line DL1, and a drain connected to the pixel electrode of the pixel capacitor Clc.

In addition, the liquid crystal panel 110 includes a discharge unit 112 connected to the plurality of data lines DL1,..., DLm in the non-display area. The discharge unit 112 is provided with the common voltage VCOM from the power supply unit 160, and the discharge signal DCGsig is provided from the power off detection unit 162. When the supply of the external power voltage is cut off in response to the discharge signal DCGsig, for example, when the battery is removed from the mobile information device to which the liquid crystal display is applied, the plurality of data lines DL1 are included. , ..., DLm) to provide a common voltage (VCOM).

In addition, the liquid crystal panel 100 may include a gate driving circuit 130 and an output buffer 132 that are integrated in a non-display area in the form of an Amolphos Silicon Gate (ASG) in the non-display area.

The data driver 120 generates a gray scale display voltage corresponding to the data signal DATA using the gamma voltage VGMA, and applies the gray scale display voltage to the thin film transistor TFT driven by the gate-on voltage VON. Is applied to display the gray scale display voltage in units of gate lines GL1, ..., GLn.

To this end, the data driver 120 receives the data control signal DCS and the data signal DATA from the timing controller 140, and receives the gamma voltage VGMA from the gamma voltage generator 140. The gray scale display voltage is an analog voltage corresponding to the data signal DATA, and the data control signal DCS includes a data start pulse STH and a data synchronization clock CPH.

The data driver 120 may be manufactured as an integrated circuit (IC), and may be attached to the liquid crystal panel 110 in a tape carrier package (TCP) type, and may be a chip on glass (COG) type liquid crystal panel ( It may be directly mounted on the non-display area of 110.

The gate drivers 130, 132, and 134 simultaneously turn on a plurality of TFTs connected to sequentially selected gate lines GL1,..., GLn. To this end, the gate drivers 130, 132, and 134 include a level shifter 134, a gate driving circuit 130, and an output buffer 132.

The level shifter 134 receives the output enable signal OE, the gate clock CPV, and the start signal STV as the gate control signal from the timing controller 140, and the gate-on voltage VON from the power supply 160. And a gate off voltage VOFF to generate gate clock pulses CKV and CKVB and a start pulse STVP having a gate on voltage VON and a gate off voltage VOFF level, and generate the gate driving circuit 130. To provide.

The gate driving circuit 130 receives the gate clock pulses CKV and CKBV and the start pulse STVP from the level shifter 134 and transmits the gate clock pulses CKV, CKVB) is sequentially provided as the gate driving voltage.

The output buffer 132 sequentially provides the gate driving signals to the plurality of gate lines GL1,..., GLn in response to the discharge signal DISsig provided from the power off detection unit 162, or simultaneously performs the gate driving signal. To provide.

The gamma voltage generator 140 generates a gamma voltage VGMA by dividing the analog power voltage AVDD supplied from the power supply unit 160 and provides the gamma voltage VGMA to the data driver 120.

The timing controller 150 converts an external data signal input from the outside into a data signal DATA that can be processed by the data driver 120, and supplies the data signal to the data driver 120, and the data driver 120 and the level shifter. Control signals DCS (OE, CPV, STV) necessary for the operation of 134 are generated and provided to the data driver 120 and the level shifter 134, respectively.

The power supply unit 160 receives a power supply voltage VDD from an external source and generates a gate-on voltage VON and a gate-off voltage VOFF, and provides them to the level shifter 134 and the output buffer 132. In addition, the power supply unit 160 generates an analog power voltage AVDD and provides the same to the gamma voltage generator 140.

In addition, when the battery is removed and the power supply voltage VDD is cut off from the outside, the power supply unit 160 detects this and generates a discharge signal DCGsig to output the output buffer 132 and the discharge unit 112. The power off detection unit 162 is provided. Here, the discharge signal DCGsig maintains a "high" level when the power supply voltage is normally supplied, and is enabled to a "low" level when the power supply voltage is abnormally cut off.

In the liquid crystal display according to the exemplary embodiment, when the supply of the power supply voltage VDD is abnormally cut off, the plurality of gate lines GL1,..., GLn are simultaneously driven, and the pixel capacitor CLC Since the common voltage VCOM is applied to both ends, all of the gray scale display voltage remaining in the pixel capacitor CLC is discharged to remove the afterimage.

FIG. 2 is an exemplary circuit diagram illustrating a discharge unit illustrated in FIG. 1. As illustrated in FIG. 2, the discharge unit 112 may be configured to apply the common voltage VCOM to the plurality of data lines DL1,..., DLm in response to the discharge signal DCGsig. Have

More specifically, the discharge unit 112 includes a plurality of switching transistors PT1,..., PTm respectively corresponding to the plurality of data lines DL1,..., DLm. Each switching transistor includes a control terminal provided with a discharge signal DCGsig, an output terminal connected to a data line, and an input terminal provided with a common voltage VCOM. The switching transistors PT1,..., And PTm may be P-channel metal-oxide semiconductor (PMOS) transistors.

In operation, when the power supply voltage is normally supplied and the discharge signal DCGsig is provided at the " high " level, the plurality of switching transistors PT1,..., PTm are turned off so that the plurality of data lines DL1,. .., DLm) is electrically isolated. Therefore, the data driver may normally apply the gray scale display voltage to the thin film transistors connected to each of the data lines DL1, DLm.

On the other hand, when the power supply voltage is abnormally cut off and the discharge signal DCGsig is provided at the "low" level, the plurality of switching transistors PT1,..., PTm is turned on so that the plurality of data lines DL1,... DLm) are electrically connected to each other. The switching transistors PT1,..., PTm provide a common voltage VCOM to the thin film transistor TFT connected to each of the plurality of data lines DL1,..., DLm. That is, the common voltage VCOM is provided to both electrodes of the pixel capacitor CLC connected to the plurality of thin film transistors TFT, so that the potential difference between the electrodes of the pixel capacitor CLC is zero. Accordingly, the charge remaining in the pixel capacitor CLC may be discharged and removed through the data lines DL1, DLm connected to the thin film transistor TFT without remaining in the pixel capacitor CLC.

FIG. 3 is an exemplary circuit diagram of the output buffer shown in FIG. 1. As illustrated in FIG. 3, the output buffer 132 has a configuration capable of providing gate driving signals to the plurality of gate lines GL1,..., GLn in response to the discharge signal DCGsig.

More specifically, the output buffer 132 includes a plurality of switching transistors NT1,..., NTn, and driving transistors PT1,..., PTn respectively corresponding to the plurality of gate lines GL1,..., GLn. ), Inverting inverters INV1, ..., INVn and buffer inverters INVA1, ..., INVAn; INVB1, ..., INVBn.

Each switching transistor includes a control terminal provided with a discharge signal DCGsig, an input terminal connected to the gate driving circuit 130, and an output terminal connected to the gate line. The switching transistors NT1 to NTn are preferably N-channel metal-oxide semiconductor (NMOS) transistors.

Each driving transistor includes a control terminal provided with a discharge signal DCGsig, an output terminal connected to an input terminal of an inverting inverter, and an input terminal provided with a gate-off voltage VOFF. The driving transistors PT1, ..., PTn are preferably P-channel metal-oxide semiconductor (PMOS) transistors.

Each inverting inverter has an input terminal connected to the output terminal of the driving transistor and an output terminal connected to the output terminal of the switching transistor.

Each buffer inverter includes two inverters INVA and INVB connected in series with the output terminal of the switching transistor.

  In operation, when the power supply voltage is normally supplied and the discharge signal DCGsig is provided at the "high" level, the plurality of switching transistors NT1, ..., NTn are turned on and the plurality of driving transistors PT1, .. ., PTn) is turned off. Therefore, the gate driving circuit 130 sequentially provides the gate driving signal to the plurality of gate lines GL1,..., GLn.

On the other hand, when the power supply voltage is abnormally cut off and the discharge signal DCGsig is provided at the "low" level, the plurality of switching transistors NT1, ..., NTn are turned off and the plurality of driving transistors PT1, ... , PTn) is turned on. The inverting inverters INV1, ..., INVn drive gates of the gate-on voltage VON level inverting the gate-off voltage VOFF provided to the input terminals of the plurality of driving transistors PT1, ..., PTn. The signal is simultaneously provided to the plurality of gate lines GL1, ..., GLn. Therefore, the plurality of thin film transistors respectively connected to the plurality of gate lines GL1,..., GLn are turned on, and the gray scale display voltage stored in the pixel capacitor CLC includes the plurality of data lines DL1,..., DLm. Discharged). As a result, the afterimage generated in the liquid crystal panel may be removed due to abnormal power supply interruption.

FIG. 4 is a circuit diagram illustrating an example of the power off detection unit illustrated in FIG. 1. As illustrated in FIG. 4, the power off detection unit 162 generates a discharge signal DCGsig in response to the external power supply voltage VDD.

More specifically, the power off detector 162 includes a signal generation transistor that generates a discharge signal DCGsig. The signal generation transistor has a source and a drain connected to a power supply terminal and a ground terminal, and a power supply voltage VDD is provided to a gate. The source to which the power terminal is connected operates as an output terminal for outputting the discharge signal DCGsig. The signal generation transistor may be a PMOS (P-channel Metal-Oxide Semiconductor) transistor.

In operation, when the power supply voltage is normally supplied, the signal generation transistor is turned off to output a "high" level voltage supplied to the power supply terminal as the discharge signal DCGsig. On the other hand, when the power supply voltage is abnormally cut off, the signal generation transistor is turned on to form a path connecting the power supply terminal and the ground terminal so that all currents of the "high" level voltage provided to the power supply terminal flow to the ground terminal. Therefore, the "low" level voltage corresponding to the ground terminal is output as the discharge signal DCGsig.

FIG. 5 is a timing diagram for describing an operation of the liquid crystal display illustrated in FIG. 1. Referring to FIG. 5, the period in which the discharge signal DCGsig is “high” is a period in which the power supply voltage VDD is normally supplied. The gate driving signals are sequentially applied to the plurality of gate lines GL1,..., GLn. Is provided.

The section in which the discharge signal DCGsig is "low" is a section in which the power supply voltage VDD is abnormally cut off, such as a battery removal, and the gate driving signal is applied to the plurality of gate lines GL1, ..., GLn by the output buffer. Provided at the same time.

Here, T means the time when the gate driving signal provided to the plurality of gate lines GL1, ..., GLn by the output buffer maintains the "high" level. T is preferably a time at which all the charge accumulated in all the pixel capacitors of the liquid crystal panel can be discharged by driving the plurality of gate lines GL1, ..., GLn.

The liquid crystal display according to the exemplary embodiment of the present invention has a configuration in which a plurality of gate lines GL1,..., GLn are simultaneously driven when the supply of the power supply voltage VDD is abnormally cut off from the outside. All of the gradation display voltages remaining in the CLC are discharged to remove the afterimage.

The liquid crystal display and the afterimage removal method of the present invention have the effect of removing all the residual images generated when the battery is removed by driving all the gate lines at the same time and inputting a common voltage to the data lines when the battery removal is detected.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A power supply unit detecting a cutoff of the external power supply voltage and providing the discharge signal as a discharge signal; A gate driver configured to simultaneously provide a gate driving signal to a plurality of gate lines in response to the discharge signal; And And a discharge unit configured to provide a common voltage to a plurality of data lines in response to the discharge signal. The method of claim 1, The gate driver includes a driving transistor and an inverter respectively corresponding to the plurality of gate lines, The driving transistor includes a control terminal provided with the discharge signal, an output terminal connected to an input terminal of the inverter, and an input terminal provided with a gate off voltage. The inverter has an input terminal connected to an output terminal of the driving transistor and an output terminal connected to the gate line. The method of claim 2, The discharge unit includes a switching transistor corresponding to each of the plurality of data lines, The switching transistor includes a control terminal provided with the discharge signal, an output terminal connected to the data line, and an input terminal provided with the common voltage. The method of claim 3, wherein the power supply unit, And a signal generation transistor having a source and a drain-in connected to a power supply terminal and a ground terminal, wherein the power supply voltage is provided to a gate. A plurality of gate lines, a plurality of data lines, a pixel capacitor each formed at an intersection of the plurality of gate lines and the plurality of data lines, and having a common voltage applied thereto at one end thereof, in response to a gate driving signal provided to the gate line; A liquid crystal panel including a thin film transistor connecting a data line and the other end of the pixel capacitor; A timing controller providing a gate control signal in response to an external signal; A power supply unit configured to receive an external power supply voltage, generate a driving voltage including the common voltage, detect a supply cutoff of the external power supply voltage, and provide a discharge signal; A gate driver configured to sequentially provide the gate driving signal to the plurality of gate lines in response to the gate control signal, and simultaneously provide the gate driving signal to the plurality of gate lines in response to the discharge signal; And And a discharge unit configured to apply the common voltage to the plurality of data lines in response to the discharge signal. The method of claim 5, wherein The driving voltage includes a gate on voltage and a gate off voltage, And the gate driver provides the gate driving signal having the gate on voltage and the gate off voltage levels. The method of claim 6, wherein the gate driver, A level shifter configured to receive a first gate control signal from the timing controller and receive the gate on voltage and the gate off voltage from the power supply to generate a second gate control signal having the gate on voltage and the gate off voltage levels; A gate driving circuit sequentially providing the gate driving signal to the plurality of gate lines in response to the second gate control signal; And And an output buffer configured to simultaneously provide the gate driving signal to the plurality of gate lines in response to the discharge signal. The liquid crystal display of claim 7, wherein the discharge unit, the gate driving circuit, and the output buffer are formed in the liquid crystal panel. The method of claim 8, The output buffer includes a switching transistor, a driving transistor, and an inverter respectively corresponding to the plurality of gate lines. The switching transistor includes a control terminal provided with the discharge signal, an input terminal connected to the gate driving circuit, and an output terminal connected to the gate line, The driving transistor includes a control terminal provided with the discharge signal, an output terminal connected to an input terminal of the inverter, and an input terminal provided with a gate off voltage. The inverter has an input terminal connected to an output terminal of the driving transistor and an output terminal connected to the gate line. The liquid crystal display of claim 9, wherein the switching transistor is an NMOS transistor, and the driving transistor is a PMOS transistor. The method of claim 8, The discharge unit includes a switching transistor corresponding to each of the plurality of data lines, The switching transistor includes a control terminal provided with the discharge signal, an output terminal connected to the data line, and an input terminal provided with the common voltage. The liquid crystal display of claim 11, wherein the switching transistor is a PMOS transistor. The method of claim 5, wherein the power supply unit, And a signal generation transistor having a source and a drain-in connected to a power supply terminal and a ground terminal, wherein the power supply voltage is provided to a gate. The method of claim 5, wherein The driving voltage comprises an analog power supply voltage, A gamma voltage generator for generating a gamma voltage by dividing the analog power voltage; And And a data driver configured to provide a gray scale display voltage to the plurality of data lines using the gamma voltage. A plurality of gate lines, a plurality of data lines, a pixel capacitor each formed at an intersection of the plurality of gate lines and the plurality of data lines, and having a common voltage applied thereto at one end thereof, in response to a gate driving signal provided to the gate line; An afterimage removing method of a liquid crystal display including a thin film transistor connecting a data line and the other end of the pixel capacitor. Detecting the interruption of the external power supply and providing the discharge signal as a discharge signal; A gate driving step of simultaneously providing the gate driving signals to the plurality of gate lines in response to the discharge signal; And And discharging the common voltage to the plurality of data lines in response to the discharge signal. The method of claim 15, wherein the detecting step, Source and drain connected to a power supply terminal and a ground terminal, a gate is provided to the external power supply voltage, and a source connected to the power supply terminal uses a signal generation transistor to operate as an output terminal for providing the discharge signal. And disabling the discharge signal and outputting the discharge signal when the external power supply voltage is cut off. The method of claim 16, wherein the gate driving step, If the discharge signal is enabled, inverting a gate-off voltage and providing the gate driving signal as the gate driving signal.

Images