CN101217026B

CN101217026B - Liquid crystal display and method for eliminating afterimage thereof

Info

Publication number: CN101217026B
Application number: CN2008100024246A
Authority: CN
Inventors: 朱胜镛; 李重先; 郑锡祺; 李东烨; 金哲民; 朴泰炯; 朴俊河; 尹汝珍; 俞相旭
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2007-01-06
Filing date: 2008-01-07
Publication date: 2012-03-28
Anticipated expiration: 2028-01-07
Also published as: KR20080064928A; CN101217026A

Abstract

A liquid crystal display (''LCD'') for eliminating an afterimage includes a power supply, a gate driver and a discharger. The power supply detects the cutting off of external power voltage and supplies a discharge signal. The gate driver simultaneously supplies a gate driving signal to a plurality of gate lines in response to the discharge signal, and the discharger supplies a common voltage to aplurality of data lines in response to the discharge signal.

Description

Eliminate the LCD and the method thereof of after image

Technical field

The present invention relates to the LCD (" LCD ") and the method thereof of a kind of elimination after image (afterimage), more specifically, relate to a kind of LCD and method thereof of when cutting off external power source, eliminating after image.

Background technology

LCD uses the light transmission rate (light transmittance) that is inserted in the liquid crystal between first substrate and second substrate to come display image; Wherein when to the electrode application voltage of these two substrates respect to one another when producing electric field, the light transmission rate of this liquid crystal changes.

Along with the development of small and exquisite profile, light characteristics such as weight, low-power consumption and high reliability, LCD just is being widely used in the mobile device of the quick demand of people, like personal digital assistant (" PDA "), mobile phone and notebook computer etc.

When the battery of the LCD that is removed mobile device by user or external action was operated to stop it, the power supply of supplying with LCD was cut off.Therefore, after image possibly be left on the liquid crystal panel.

Summary of the invention

The invention provides a kind of through driving all gate lines simultaneously and importing LCD (" LCD ") and the method thereof that common electric voltage is eliminated after image to data line.

In addition, the invention provides a kind of data driving equipment of the charge discharge that is used for when abnormity of power supply stops, will remaining in driver IC (" IC ") and the LCD that uses this data driving equipment.

Example embodiment of the present invention provides a kind of LCD, and this LCD comprises: power supply, and it detects the cut-out of outer power voltage and applies the relevant discharge signal of detection with the cut-out of this outer power voltage; Gate drivers, it offers many gate lines in response to this discharge signal with gate drive signal simultaneously; And discharger; It offers many data lines in response to this discharge signal with common electric voltage; Wherein, said gate drivers offers time period of said many gate lines simultaneously with said gate drive signal, wherein during this time period; Be accumulated in all electric charges in the pixel capacitor of said LCD all by abundant discharge, and said gate drive signal is a high level.

Another example embodiment of the present invention provides a kind of LCD; This LCD comprises: liquid crystal panel, and it has many gate lines, many data lines, to its a plurality of thin film transistor (TFT)s (" TFT ") that apply a plurality of pixel capacitors of common electric voltage and in response to the gate drive signal that offers said gate line said data line is electrically connected to said pixel capacitor; Timing controller, it provides data-signal, data controlling signal and grid control signal in response to external signal; Power supply, it receives outer power voltage producing driving voltage and common electric voltage, and the cut-out that detects this outer power voltage is to provide the relevant discharge signal of detection with the cut-out of this outer power voltage; Gate drivers, it offers many gate lines in response to this discharge signal with gate drive signal simultaneously; And first discharger, it offers many data lines in response to this discharge signal with common electric voltage.

Another example embodiment of the present invention provides a kind of method that is used to eliminate the after image of LCD equipment; This LCD equipment comprises many gate lines, many data lines, a plurality of pixel capacitor and a plurality of TFT; Wherein each pixel capacitor is with respect to the intersection point of gate line and data line and form and have first end that applies common electric voltage to it, and said a plurality of TFT are connected to said data line in response to the gate drive signal that offers said gate line second end of said pixel capacitor.Said method comprises: detect the cut-out of outer power voltage and the relevant discharge signal of detection with the cut-out of this outer power voltage is provided; In response to this discharge signal gate drive signal is offered many gate lines simultaneously; And common electric voltage is offered many data lines in response to this discharge signal; Wherein, In response to this discharge signal gate drive signal being offered many gate lines simultaneously comprises said gate drive signal is offered time period of said many gate lines simultaneously; Wherein during this time period, be accumulated in all electric charges in the pixel capacitor of liquid crystal display all by abundant discharge, and said gate drive signal is a high level.

Description of drawings

Through understanding example embodiment of the present invention, wherein below in conjunction with the detailed description of accompanying drawing:

Fig. 1 is the block diagram that illustrates according to the exemplary LCD of example embodiment of the present invention;

Fig. 2 is the circuit diagram that the exemplary discharger shown in Fig. 1 is shown;

Fig. 3 is the circuit diagram that the exemplary output buffer shown in Fig. 1 is shown;

Fig. 4 is the circuit diagram that the exemplary shutdown detecting device shown in Fig. 1 is shown;

Fig. 5 is the sequential chart that is used to describe the example operation of the exemplary LCD shown in Fig. 1;

Fig. 6 is the circuit diagram that another the exemplary discharger shown in Fig. 1 is shown;

Fig. 7 is the circuit diagram that another the exemplary output buffer shown in Fig. 1 is shown;

Fig. 8 is the block diagram that exemplary LCD according to another exemplary embodiment of the present invention is shown; And

Fig. 9 is the circuit diagram that an exemplary discharger shown in Fig. 8 is shown.

Embodiment

When the power supply of supplying with traditional LC D was cut off, after image had been stayed on the liquid crystal panel.According to the present invention; Confirm when power supply in traditional LC D stops (as removing battery) suddenly; Except just other all gate lines the selecteed gate line all are in the grid cut-off voltage state before the battery removing, and the grayscale voltage that is accumulated in the pixel capacitor of liquid crystal panel is held former state.That is to say; Except removing before the battery the selecteed gate line just; Cut off the path that the grayscale voltage discharge that is accumulated in the pixel capacitor possibly passed through; Thereby this grayscale voltage is held and stays as after image, all passes through leakage current and naturally till the discharge up to all grayscale voltages.

But; Also confirm according to the present invention; Be formed at TFT in the liquid crystal panel among the traditional LC D because the property difference that in the technological process such as the process variability of TFT threshold voltage (Vth), produces, and cause said TFT possibly have different leakage currents.This possibly cause the different discharge condition of pixel capacitor, thereby causes noise.

Also confirm according to the present invention; If in traditional LC D, remove battery thereby power supply stops suddenly, then be used for white level pattern (white pattern) scan gate line cut off the coded program that the electric current of the power end of driver IC (" IC ") provides then can not normal running.Therefore, possibly unusual pattern after image take place owing to the operation such as the non-expectation by the data line on the electric charge driving liquid crystal panel that remains in this driver IC.

To example embodiment more completely be described with reference to the accompanying drawing that embodiments of the invention are shown below.But, can come embodiment of the present invention with multiple different form, and the present invention is not appreciated that and is confined to described embodiment here.On the contrary, these embodiment are provided so that the disclosure is clear for a person skilled in the art complete, and cover scope of the present invention fully.Similar reference number refers to similar element in the whole text.

Should be appreciated that when claiming an element " on another element " can directly perhaps also can there be the insertion element in it therebetween on another element.On the contrary, when claiming an element " directly on another element ", then there is not the insertion element.Here used, term " and/or " comprise being correlated with and list one or more any and all combinations of item.

First, second, third wait and describe various elements, assembly, zone, layer and/or part although should be appreciated that possibly use a technical term here, these elements, assembly, zone, layer and/or part should not limited by these terms.These terms only are used for an element, assembly, zone, layer and part and another element, assembly, zone, layer and part are made a distinction.Therefore, under the situation that does not break away from instruction of the present invention, can first element, assembly, zone, layer or the part of following discussion be called second element, assembly, zone, layer or part.

Terminology used here only is in order to describe concrete embodiment, to be not intended to limit the present invention.Just as used herein, singulative " ", " one " and " this " can be intended to also comprise plural form, only if clear from context to indicate be odd number.It should also be understood that; The term that is used for this instructions " comprise " and/or " comprising " specified that set characteristic, zone, integer, base are rapid, the existence of operation, element and/or assembly, but do not get rid of the existence of or more further feature, zone, integer, step, operation, element, assembly and/or their group or additional.

Only if definition is arranged in addition, all used here terms (comprising technology and scientific terminology) have the identical meaning with one of ordinary skill in the art's common sense of the present invention.It should also be understood that; Be appreciated that to have and the meaning of aggregatio mentium in correlation technique and content of the present disclosure such as those terms that in normally used dictionary, define; And should not be interpreted as Utopian or too formal, only if done special definition here.

Fig. 1 is the block diagram that illustrates according to the exemplary LCD of example embodiment of the present invention.As shown in Figure 1, comprise liquid crystal panel 110, data driver 120, gate drivers 130, gamma electric voltage producer 140, timing controller 150 and power supply 160 according to the LCD 100 of example embodiment of the present invention.

Liquid crystal panel 110 comprises the chromatic filter substrate that is formed with chromatic filter and public electrode on it, the TFT substrate that is formed with TFT on it and the liquid crystal of between this chromatic filter substrate and TFT substrate, filling.

The TFT substrate comprises many gate lines G L1 ..., GLn, many data line DL1; ...; DLm, with respect to gate lines G L1 ..., GLn and data line DL1; ..., the intersection point of DLm and forming with a plurality of pixel capacitor CLC of charging grayscale voltage and a plurality of TFT that are used in response to gate-on voltage VON grayscale voltage is offered pixel capacitor CLC.The drain electrode (like drain electrode) that each TFT has the grid (like gate electrode) that is connected to gate lines G L, the source electrode (like source electrode) that is connected to data line DL and is connected to the pixel electrode of pixel capacitor CLC is so that first end of each pixel capacitor CLC can receive the data-signal from each TFT.Each pixel capacitor CLC also receives the common electric voltage VCOM that applies to its second end through the public electrode that is formed on the chromatic filter substrate.

Liquid crystal panel 110 comprises and is connected to the data line DL1 that is in non-display area ..., the discharger 112 of DLm.For discharger 112 provides from the common electric voltage VCOM of power supply 160 with from the discharge signal DCGsig (also illustrating at Fig. 2) of shutdown detecting device 162.When outer power voltage VDD was cut off, as when from the mobile device with LCD 100, removing battery, discharger 112 offered many data line DL1 in response to discharge signal DCGsig with common electric voltage VCOM ..., DLm.

Data driver 120 produces the grayscale voltage corresponding with data-signal DATA, this grayscale voltage is put on by the TFT of gate-on voltage VON driving and with gate lines G L1 through using gamma electric voltage VGMA; ..., GLn is that unit shows this grayscale voltage.

For data driver 120 provides data controlling signal DCS and data-signal DATA that comes from timing controller 150 and the gamma electric voltage VGMA that comes from gamma electric voltage producer 140.Grayscale voltage is and data-signal DATA corresponding simulating voltage, and data controlling signal DCS comprises data initial pulse STH and data sync clock CPH.

Data driver 120 can be manufactured into data-driven integrated circuit (" IC "); Thereby can its form of carrying encapsulation (" TCP ") with band be invested on the liquid crystal panel 110 and be directly installed on the non-display area of liquid crystal panel 110 with the form of glass substrate chip (chip-on-glass, " COG ").

Gate drivers 130 offers gate lines G L1 with gate drive signal successively ..., GLn, and conducting is connected to selected gate lines G L1 ..., a plurality of TFT of GLn.The grid control signal GCS that comes from timing controller 150 and the gate-on voltage VON and the grid cut-off voltage VOFF that come from power supply 160 are provided for gate drivers 130.Grid control signal GCS comprises grid initial pulse STV, grid synchronous clock CPV and output enable signal OE.

Gate drivers 130 has output buffer 132, if when outer power voltage VDD is cut off, then this output buffer 132 offers many gate lines G L1 in response to discharge signal DCGsig with gate drive signal simultaneously ..., GLn.For this reason, for output buffer 132 discharge signal DCGsig and grid cut-off voltage VOFF from shutdown detecting device 162 are provided.

Gate drivers 130 can be manufactured into gate driving IC; Thereby can it be invested on the liquid crystal panel 110 with the TCP form and be integrated on the non-display area of liquid crystal panel 110 with the form of amorphous silicon grid (amorphous silicon gate, " ASG ").

Gamma electric voltage producer 140 will carry out dividing potential drop from the analog power voltage AVDD that power supply 160 provides, and produce and provide gamma electric voltage VGMA to data driver 120.

Timing controller 150 converts external signal to can be by the data-signal DATA of data driver 120 processing; It is offered data driver 120; And be created in required control signal DCS and GCS in the operation of data driver 120 and gate drivers 130, they are offered data driver 120 and gate drivers 130 respectively.This external signal comprises R, G, B data, synchronizing signal and clock.

The supply voltage VDD that power supply 160 receives from external source produces gate-on voltage VON and grid cut-off voltage VOFF, and they are offered gate drivers 130.In addition, power supply 160 produces analog power voltage AVDD and it is offered gamma electric voltage producer 140.

Power supply 160 has shutdown detecting device 162, and whether it detects outer power voltage VDD and be cut off, and produces discharge signal DCGsig and it is offered the output buffer 132 of discharger 112 and gate drivers 130.In an example embodiment, when supply voltage VDD normally provided, discharge signal DCGsig kept " height " level, and when supply voltage VDD was cut off unusually, discharge signal DCGsig was enabled and is " low " level.

In LCD, also will describe as following, if outer power voltage VDD is cut off by unusual according to example embodiment of the present invention; Then drive many gate lines G L1 simultaneously; ..., GLn, and common electric voltage VCOM put on the two ends of pixel capacitor CLC; Thereby will remain in all the grayscale voltage discharges among the pixel capacitor CLC, to eliminate the after image of LCD 100.

Fig. 2 is the circuit diagram that the exemplary discharger shown in Fig. 1 is shown.As shown in Figure 2, discharger 112 is constructed to: it can put on many data line DL1 with common electric voltage VCOM in response to discharge signal DCGsig ..., DLm.

Discharger 112 has respectively and many data line DL1 ..., a plurality of switching transistor PT1 that DLm is corresponding ..., PTm.Each switching transistor PT have to its provide the discharge signal DCGsig that comes from the detecting device 162 that shuts down control end, be connected to data line DL1 ..., the output terminal of DLm and the input end of the common electric voltage VCOM that comes from power supply 1 60 is provided to it.Here, preferably, switching transistor PT1 ..., PTm is P-channel metal-oxide-semiconductor (" PMOS ") transistor.

In operation, when supply voltage VDD normally provides thereby discharge signal DCGsig when being provided as " height " level, a plurality of switching transistor PT1 ..., PTm is ended, thereby with many data line DL1 ..., DLm electricity each other separates.Therefore, data driver 120 can be normally puts on grayscale voltage respectively and data line DL1 ..., the TFT that DLm connects.

When supply voltage VDD is cut off thereby discharge signal DCGsig when being provided as " low " level by unusual, a plurality of switching transistor PT1 ..., PTm is switched on, thereby with many data line DL1 ..., DLm is electrically connected to each other.Switching transistor PT1 ..., the common electric voltage VCOM that PTm will come from power supply 160 offers and is connected to data line DL1 ..., the TFT of DLm.That is, common electric voltage VCOM is put on the two ends of the pixel capacitor CLC that is connected to TFT, make that the electric potential difference between two electrodes (that is, pixel electrode and public electrode) of pixel capacitor CLC is 0.Thereby the electric charge that remains among the pixel capacitor CLC is no longer stayed among the pixel capacitor CLC, but can be through being connected to the data line DL1 of TFT ..., the DLm discharge.

Fig. 3 is the circuit diagram that exemplary output buffer shown in Figure 1 is shown.As shown in Figure 3, output buffer 132 is configured to: it can offer many gate lines G L1 with gate drive signal in response to discharge signal DCGsig ..., GLn.

Output buffer 132 comprises respectively and many gate lines G L1 ..., a plurality of switching transistor NT1 that GLn is corresponding ..., NTn, driving transistors PT1; ..., PTn, phase inverter INV1 ..., INVn and buffer inverter INVA1; ..., INVAn and INVB1 ..., INVBn.

Switching transistor NT1; ...; Each of NTn have to its provide the discharge signal DCGsig that comes from the detecting device 162 that shuts down control end, be connected to the input end of gate drivers 130 and be connected to gate lines G L1 ..., corresponding one output terminal of GLn.In an example embodiment, switching transistor NT1 ..., NTn is N NMOS N-channel MOS N (" NMOS ") transistor.

Driving transistors PT1 ..., PTn comprise to its provide the discharge signal DCGsig that comes from the detecting device 162 that shuts down control end, be connected to phase inverter INV1 ..., the output terminal of the input end of INVn and apply the input end of grid cut-off voltage VOFF to it.In an example embodiment, driving transistors PT1 ..., PTn is the PMOS transistor.

Phase inverter INV1 ..., INVn has the driving transistors of being connected to PT1 ..., the input end of the output terminal of PTn be connected to switching transistor NT1 ..., the output terminal of the output terminal of NTn.Like this, phase inverter INV1 ..., the output terminal of INVn also is connected to gate lines G L1 ..., GLn.

Buffer inverter INVA1 ..., INVAn and INVB 1 ..., INVBn comprises and is connected to switching transistor NT1 ..., a plurality of phase inverters of the output terminal of NTn are to INVA and INVB.

In operation, when supply voltage VDD normally provides thereby discharge signal DCGsig when being provided as " height " level, switching transistor NT1 ..., NTn is switched on, and driving transistors PT1 ..., PTn is ended.Therefore, gate drivers 130 offers gate lines G L1 with gate drive signal successively ..., GLn.

When supply voltage VDD is cut off thereby discharge signal DCGsig when being provided as " low " level by unusual, switching transistor NT1 ..., NTn is ended, and driving transistors PT1 ..., PTn is switched on.Phase inverter INV1 ..., INVn offers gate lines G L1 simultaneously with the gate drive signal of gate-on voltage VON level; ..., GLn, this gate-on voltage VON level is by offering driving transistors PT1; ..., the grid cut-off voltage VOFF of the input end of PTn converts.Thereby, be connected to gate lines G L1 ..., the whole conductings of the TFT of GLn, the grayscale voltage that is stored among the pixel capacitor CLC passes through data line DL1 ..., DLm is discharged.Thereby, can eliminate the after image that on traditional liquid crystal panel, produces owing to abnormal power-down.

Fig. 4 is the circuit diagram that the exemplary shutdown detecting device shown in Fig. 1 is shown.As shown in Figure 4, shutdown detecting device 162 is configured to produce discharge signal DCGsig in response to outer power voltage VDD.

Shutdown detecting device 162 comprises that the signal that produces discharge signal DCGsig produces transistor.This signal produces that transistorized source electrode is connected to power end, drain electrode is connected to earth terminal, grid is applied with outer power voltage VDD.The voltage VH corresponding with the high level of discharge signal DCGsig (like supply voltage VDD) can be applied in power end.The source electrode that is connected to power end is worked as the output terminal of exporting discharge signal DCGsig.In an example embodiment, it is the PMOS transistor that this signal produces transistor.

In operation, when supply voltage VDD normally provided, the signal in the shutdown detecting device 162 produces transistor to be ended, and " height " level voltage that offers power end is exported as discharge signal DCGsig.When supply voltage VDD was cut off unusually, the signal of shutdown in the detecting device 162 produced transistor turns, forms the path that power end is connected to earth terminal, thereby the electric current of " height " level through offering power end all flows to earth terminal.Thereby " low " level voltage corresponding with earth terminal exported as discharge signal DCGsig.

Fig. 5 is the sequential chart that is used to describe the operation of exemplary LCD shown in Figure 1.With reference to Fig. 5, be in the part of " height " level at discharge signal DCGsig, also, gate drive signal is offered many gate lines G L1 successively promptly corresponding to the part of supply voltage VDD normal supply ..., GLn.

Be in the part of " low " level at discharge signal DCGsig, also promptly corresponding to the unusual part of cutting off of supply voltage VDD, output buffer 132 puts on many gate lines G L1 simultaneously with gate drive signal owing to remove battery etc. ..., GLn is last.

The T representative is applied to many gate lines G L1 by output buffer 132 ..., the period that the last gate drive signal of GLn keeps " height " level.In an exemplary embodiment, T is that all electric charges that are accumulated among all pixel transistor CLC of liquid crystal panel 110 can be through driving many gate lines G L1 ..., GLn and period of being discharged.

LCD according to example embodiment of the present invention is configured to: in the voltage VDD that cuts off the electricity supply unusually; Drive many gate lines G L1 simultaneously ..., GLn; Thereby will remain in all the grayscale voltage discharges among the pixel transistor CLC, to eliminate the after image on the liquid crystal panel 110.

Fig. 6 is the circuit diagram that another exemplary discharger shown in Figure 1 is shown.As shown in Figure 6, discharger 112 is configured to: the common electric voltage VCOM that will come from power supply 1 60 in response to the discharge signal DCGsig that is provided by shutdown detecting device 162 puts on many data line DL1 ..., DLm is last.

Discharger 112 comprises and many data line DL1 ..., a plurality of switching transistor NT1 that DLm is corresponding; ..., NTm, and phase inverter INV; This phase inverter INV is used for the phase place anti-phase of discharge signal DCGsig is offered switching transistor NT1 with it then ..., the control end of each of NTm.Here, the output of phase inverter INV becomes the discharge signal DCGsigB of anti-phase, perhaps, in other words, becomes discharge and stops signal (discharge bar signal).

Switching transistor NT1 ..., NTm comprise to its apply anti-phase discharge signal DCGsigB control end, be connected to data line DL1 ..., the output terminal of DLm and the input end of common electric voltage VCOM is provided to it.In an exemplary embodiment, switching transistor NT1 ..., NTm is a nmos pass transistor.

In operation, when supply voltage VDD normally provides thereby discharge signal DCGsig when being provided as " height " level, be in the anti-phase discharge signal DCGsigB of " low " level from phase inverter INV output; Switching transistor NT1; ..., NTm is ended, thereby with many data line DL1; ..., DLm electricity each other separates.Therefore, data driver 120 can normally put on grayscale voltage and be connected respectively to data line DL1 ..., the TFT of DLm.

When supply voltage VDD is cut off thereby discharge signal DCGsig when being provided as " low " level by unusual, phase inverter INV output is in the anti-phase discharge signal DCGsigB of " height " level, a plurality of switching transistor NT1; ..., NTm is switched on, thereby with data line DL1; ..., DLm is electrically connected to each other.Switching transistor NT1 ..., NTm will put on switching transistor NT1 ..., the common electric voltage VCOM of the input end of NTm offers and is connected respectively to data line DL1 ..., the TFT of DLm.Thereby, for two electrodes (that is, pixel electrode and public electrode) of each pixel capacitor CLC of being connected to TFT provide common electric voltage VCOM, thereby eliminated the grayscale voltage that is accumulated simultaneously.

Fig. 7 is the block diagram that the structure of the exemplary gate drivers shown in Fig. 1 is shown.As shown in Figure 7, gate drivers 130 comprises shift register 136, level translator (shifter) 134 and output buffer 132.

Shift register 136 produces gate drive signal successively in response to control signal STV that provides from timing controller 150 and CPV.Control signal STV is the vertical synchronizing signal that is used to notify the beginning of a frame, and control signal CPV is a clock signal.

Level translator 134 will become gate-on voltage VON level and grid cut-off voltage VOFF level from the gate drive signal level conversion that shift register 136 provides.Level translator 134 can be controlled from the characteristic of the gate drive signal of shift register 136 generations, for example its pulse width through using the output enable signal OE as grid control signal GCS.

Output buffer 132 is configured to like this: will offer many gate lines G L1 from the gate drive signal that level translator 134 provides successively; ..., GLn maybe will offer many gate lines G L1 from the gate drive signal that level translator 134 provides simultaneously; ..., GLn.

Output buffer 132 comprises and being used for the phase place anti-phase of the gate drive signal that comes from level translator 134 and the phase inverter INV1 that strengthens the current drives capacity ..., INVn.Output buffer 132 also comprises a plurality of NAND (with non-) door ND1 ..., NDn, it is for phase inverter INV1 ..., the output of INVn is carried out NAND with discharge signal DCGsig and is operated, and this operating result is offered corresponding gate lines G L1 ..., GLn.

Table 1 is to illustrate according to phase inverter INV1 ..., the NAND door ND1 of the output signal of INVn and discharge signal DCGsig ..., the logical operation result's of NDn truth table.

Table 1

The output signal of phase inverter	Discharge signal	The output signal of NAND door
			0	0	1
1	0	1
			0	1	1
1	1	0

In table 1, if phase inverter INV1 ...; The output signal of INVn is " 0 ", this means that then corresponding gate line is shifted register 136 and chooses, and if phase inverter INV1; ..., the output signal of INVn is " 1 ", this means that then corresponding gate line is not shifted register 136 and chooses.

When the output signal of NAND door is " 1 "; The gate drive signal that this means gate-on voltage VON level has been provided for corresponding gate line; And if the output signal of NAND door is " 0 ", this means that then the gate drive signal of grid cut-off voltage VOFF level has offered corresponding gate line.

When discharge signal is " 0 "; When being in low level, this means that battery is removed thereby outer power voltage VDD is cut off such as discharge signal DCGsig, and if discharge signal is " 1 "; DCGsig is in high level such as discharge signal, this means that outer power voltage VDD normally provides.

When outer power voltage VDD normally provide so that discharge signal when " 1 ", according to the output buffer 1 32 of example embodiment of the present invention through NAND door ND1 ...; NDn is with phase inverter INV1; ..., the output signal inversion of INVn, thus gate drive signal is offered many gate lines G L1 successively; ..., GLn.In other words, be connected to many gate lines G L1 ..., the TFT of GLn depends on discharge signal DCGsig and conducting or end.

When outer power voltage VDD is cut off, NAND door ND1 ..., NDn provides " 1 " always; That is, the gate drive signal of gate-on voltage VON level is offered many gate lines G L1 simultaneously ..., GLn; And no matter phase inverter INV1 ..., the output signal of INVn is how.Thereby, be connected to many gate lines G L1 ..., all conductings of all TFT of GLn, thus formation can will remain in the path of the grayscale voltage discharge among the pixel capacitor CLC through it.Thereby, can eliminate the after image that on traditional liquid crystal panel, produces owing to abnormal power-down.

Fig. 8 is the block diagram that exemplary LCD according to another exemplary embodiment of the present invention is shown.As shown in Figure 8; The data driver 220 of LCD 200 according to another exemplary embodiment of the present invention comprises discharger 222; Be used in response to cutting off from the discharge signal DCGsig of shutdown detecting device 262, and will remain in the charge discharge in the data driver 220 from the supply of the data-signal DATA of timing controller 250 with from the supply of the gamma electric voltage VGMA of gamma electric voltage producer 240.

The power supply 260 of LCD 200 according to another exemplary embodiment of the present invention comprises shutdown detecting device 262, is used to detect the abnormal power-down of supply voltage VDD.Shutdown detecting device 262 detects supply voltage VDD and is cut off by unusual, producing discharge signal DCGsig, and this discharge signal DCGsig is offered the discharger 222 of data driver 220.The unusual cut-out of outer power voltage VDD is meant, situation about for example by user or external action etc. battery being removed from the mobile device of using LCD 200.

Therefore, discharger 222 can cut off the supply of data DATA and gamma electric voltage VGMA in response to discharge signal DCGsig, and will remain in the charge discharge in the data driver 220.

The structure of other assembly of LCD 200 and operation; Can therefore omit its detailed description with consistent with reference to the described respective element of Fig. 1 or consistent in fact like liquid crystal panel 210, gate drivers 230, gamma electric voltage producer 240, timing controller 250 and power supply 260.

Fig. 9 is the circuit diagram that is illustrated in the exemplary discharger in the exemplary data driver shown in Fig. 8.As shown in Figure 9, data driver 220 comprises shift register 224, input register 225, storage register 226, digital-to-analogue (" D/A ") converter 227, output buffer 228 and discharger 222.

Shift register 224 receives data start signal STH and data sync clock CPH, to produce sampled signal and then this sampled signal to be offered input register 225.In more detail, shift register 224 is at each this data start signal of clock period displacement STH of data sync clock CPH, and n sampled signal of generation.

Input register 225 is memory data signal DATA successively in response to the sampled signal of importing successively from shift register 224.In more detail, input register 225 is stored the data-signal DATA corresponding with delegation in response to sampled signal.

When input load signal LOAD, storage register 226 receives and stores simultaneously and be stored in the as many data-signal DATA of delegation in the input register 225.The effect of load signal LOAD is that the grayscale voltage corresponding with data line signal DATA put on a plurality of pixel capacitor CLC that are connected to a gate line simultaneously.

D/A converter 227 produces and the corresponding grayscale voltage of data-signal DATA value through using gamma electric voltage VGMA, then this grayscale voltage is offered output buffer 228.Output buffer 228 will offer data line DL1 simultaneously from the grayscale voltage that D/A converter 227 provides ..., DLm.

Discharger 222 switches the data-signal DATA that offers input register 225 and offers the gamma electric voltage VGMA of D/A converter 227 in response to discharge signal DCGsig, and provide can be with the path that remains in the charge discharge in input register 225 and the D/A converter 227 through it.

Discharger 222 comprises the first switching transistor NT1, the first grounded circuit resistor R 1, second switch transistor NT2 and the second grounded circuit resistor R 2.

The first switching transistor NT1 have to its input end of data-signal DATA is provided, to its output terminal that control end of discharge signal DCGsig is provided and is connected to input register 225.One end of the first grounded circuit resistor R 1 is connected to output terminal and the input register 225 of the first switching transistor NT1, and its other end is connected to earth terminal.

Second switch transistor NT2 have to its input end of gamma electric voltage VGMA is provided, to its output terminal that control end of discharge signal DCGsig is provided and is connected to D/A converter 227.One end of the second grounded circuit resistor R 2 is connected to output terminal and the D/A converter 227 of second switch transistor NT2, and its other end is connected to earth terminal.

In operation; When supply voltage VDD regular supply; Thereby discharge signal DCGsig is when being in " height " level, the first and second switching transistor NT1 and NT2 conducting, thereby to input register 225 and D/A converter 227 data-signal DATA and gamma electric voltage VGMA are provided normally respectively.Because data-signal DATA compares with D/A converter 227 with input register 225 with gamma electric voltage VGMA and has the higher voltage level; Therefore can data-signal DATA and gamma electric voltage VGMA be offered input register 225 and D/A converter 227, and no matter the first and second grounded circuit resistor R 1 and R2 how.

When supply voltage VDD is cut off thereby discharge signal DCGsig when being applied to " low " level by unusual; The first and second switching transistor NT1 and NT2 end, thereby cut off to data-signal DATA and the gamma electric voltage VGMA of input register 225 with D/A converter 227 supplies.In this case, the output terminal of the first and second switching transistor NT1 and NT2 is compared with D/A converter 227 with input register 225 and is had lower voltage level.

Therefore, the electric charge that remains in input register 225 and the D/A converter 227 is bypassed to first and second grounded circuit resistor R 1 and the R2 respectively.Thereby if supply voltage VDD is cut off by unusual, then remaining in input register 225 can be through the discharge of being forced property of earth terminal ground with the electric charge in the D/A converter 227.

In its example embodiment, if having the battery of detecting, LCD that is used to eliminate after image of the present invention and method removed, then through driving all gate lines simultaneously and importing common electric voltage is eliminated the after image that when removing battery, produces to data line effect.

In addition; Because LCD of the present invention can will remain in the charge discharge in the driver IC when abnormal power-down; Therefore, also can eliminate the unusual pattern that causes owing to the electric charge that remains in the driver IC and the effect of after image even it has when abnormal power-down so that the program that is used to cut off the electric current of the power end that flows to driver IC can not be worked.

Although the present invention has been carried out above-mentioned diagram and description with reference to particular exemplary embodiment of the present invention; But those skilled in the art are to be understood that; Do not breaking away under the situation of the spirit and scope of the present invention that limit appended claims, can carry out the various modifications on form and the details the present invention.

Cross reference to related application

The right of priority of the korean patent application 2007-0001819 that the application requires to submit on January 6th, 2007,2007-0001820,2007-0001821 number application, all these incorporate this paper into by reference in the content of first to file.

Claims

1. LCD comprises:

Power supply, it detects the cut-out and the applying charge signal of outer power voltage;

Gate drivers, it offers many gate lines in response to this discharge signal with gate drive signal simultaneously; And

Discharger, it offers many data lines in response to this discharge signal with common electric voltage,

Wherein, Said gate drivers offers time period of said many gate lines simultaneously with said gate drive signal; Wherein during this time period, be accumulated in all electric charges in the pixel capacitor of said LCD all by abundant discharge, and said gate drive signal is a high level.

2. LCD according to claim 1, wherein, said gate drivers comprises:

A plurality of driving transistorss, it is corresponding with this gate line respectively and in response to said discharge signal grid cut-off voltage is provided; And

Phase inverter, the phase place of its this grid cut-off voltage of conversion, and the grid cut-off voltage that will change phase place offers said many gate lines as said gate drive signal.

3. LCD according to claim 2; Wherein, This discharger comprises corresponding with said many data lines respectively a plurality of switching transistors, and said switching transistor offers said many data lines in response to said discharge signal with this common electric voltage.

4. LCD according to claim 1; Wherein, Said power supply comprises being connected to it and applies the power end of supply voltage and produce transistor to its signal that applies the earth terminal of ground voltage; Wherein this signal produces transient response and switches supply voltage that puts on power end and the ground voltage that puts on earth terminal in the supply of outer power voltage, and said discharge signal is provided.

5. LCD according to claim 1, wherein, said gate drivers comprises:

A plurality of and non-NAND door, it provides said gate drive signal; And

A plurality of first phase inverters, it is corresponding with said a plurality of NAND doors and with the phase place anti-phase of grid cut-off voltage, and

Said NAND door is to the output of this first phase inverter and this discharge signal is carried out the NAND operation and provide operating result as said gate drive signal.

6. LCD according to claim 5, wherein, said discharger comprises:

A plurality of switching transistors, it is corresponding with said many data lines respectively; And

Second phase inverter, it is the phase place anti-phase of said discharge signal, and with the discharge signal output of phase place anti-phase as discharge prevention signal, and

Said switching transistor stops signal that said common electric voltage is offered said data line in response to said discharge.

7. LCD according to claim 1; Wherein, First end of said pixel capacitor receives said common electric voltage from public electrode; And second end of this pixel capacitor receives said common electric voltage in response to said discharge signal from these many data lines, and all grayscale voltages in said pixel capacitor are all by abundant discharge.

8. LCD comprises:

Liquid crystal panel, it has many gate lines, many data lines, to its a plurality of thin film transistor (TFT)s that apply a plurality of pixel capacitors of common electric voltage and in response to the gate drive signal that offers said gate line said data line is electrically connected to said pixel capacitor;

Timing controller, it provides data-signal, data controlling signal and grid control signal in response to external signal;

Power supply, it receives outer power voltage producing driving voltage and common electric voltage, and the cut-out that detects this outer power voltage is to provide the relevant discharge signal of detection with the cut-out of this outer power voltage;

Gate drivers, it offers said many gate lines in response to this discharge signal with gate drive signal simultaneously; And

First discharger, it offers said many data lines in response to this discharge signal with said common electric voltage,

Wherein, said gate drive signal is a high level.

9. LCD according to claim 8, wherein, said gate drivers comprises:

A plurality of first switching transistors, it is corresponding with said many gate lines respectively, and in response to said discharge signal this gate drive signal is offered said gate line;

A plurality of driving transistorss, it is corresponding with said gate line respectively and in response to said discharge signal grid cut-off voltage is provided; And

Phase inverter, it is the phase place anti-phase of the output of this driving transistors, and the output of the driving transistors of phase place anti-phase is offered said gate line.

10. LCD according to claim 9, wherein, this first discharger comprises:

A plurality of second switch transistors, it is corresponding with said many data lines respectively; And

Second phase inverter, it is the phase place anti-phase of this discharge signal, and the discharge signal of output phase anti-phase stops signal as discharge, and

This second switch transient response stops signal and this common electric voltage is offered said data line in said discharge.

11. LCD according to claim 8, wherein, said gate drivers comprises:

A plurality of and non-NAND door, it provides said gate drive signal; And

12. LCD according to claim 11, wherein, said first discharger comprises:

13. LCD according to claim 8 also comprises:

Gamma electric voltage producer, it is with said driving voltage dividing potential drop, to produce gamma electric voltage; And

Data driver, it switches said data-signal and said gamma electric voltage in response to said discharge signal, and with residual charge discharge.

14. LCD according to claim 13, wherein, said data driver comprises:

Shift register, it produces sampled signal in response to said data controlling signal;

Input register, it stores said data-signal successively in response to said sampled signal;

Storage register, it stores the data-signal that provides from said input register simultaneously in response to said data controlling signal;

Digital to analog converter, it produces the grayscale voltage corresponding with said data-signal through using said gamma electric voltage;

Output buffer, it offers said liquid crystal panel with said grayscale voltage; And

Second discharger, the supply that it switches said data-signal and said grayscale voltage in response to said discharge signal, and will remain in the charge discharge in said input register and the said digital to analog converter.

15. LCD according to claim 14, wherein, said second discharger comprises:

First switching transistor, it offers said input register in response to said discharge signal with said data-signal; And

The first grounded circuit resistor, wherein first end of this first grounded circuit resistor is connected to the output terminal of said first switching transistor, and second end of this first grounded circuit resistor is connected to earth terminal.

16. LCD according to claim 15, wherein, said second discharger also comprises:

The second switch transistor, it offers said digital to analog converter in response to said discharge signal with said gamma electric voltage; And

The second grounded circuit resistor, wherein first end of this second grounded circuit resistor is connected to the transistorized output terminal of said second switch, and second end of this second grounded circuit resistor is connected to said earth terminal.

17. the method for a driving liquid crystal equipment, this method comprises:

Detect the cut-out of outer power voltage and the relevant discharge signal of detection with the cut-out of this outer power voltage is provided;

In response to this discharge signal gate drive signal is offered many gate lines simultaneously; And

In response to this discharge signal common electric voltage is offered many data lines,

Wherein, In response to this discharge signal gate drive signal being offered many gate lines simultaneously comprises said gate drive signal is offered time period of said many gate lines simultaneously; Wherein during this time period; Be accumulated in all electric charges in the pixel capacitor of liquid crystal display all by abundant discharge, and said gate drive signal is a high level.

18. method according to claim 17; Wherein, The cut-out of said detection outer power voltage comprises: if the supply of this outer power voltage is cut off, then enable and export this discharge signal through using signal to produce transistor, wherein this signal produces transistorized source electrode and is connected to power end also as the output terminal of discharge signal being provided and working; This signal produces transistor drain and is connected to earth terminal, and its grid is provided with outer power voltage.

19. method according to claim 18, wherein, said this gate drive signal that provides simultaneously comprises: if this discharge signal is enabled, then be provided as said gate drive signal with the grid cut-off voltage anti-phase and with it.