KR20140036984A - Serial linear thermal processor arrangement - Google Patents
Serial linear thermal processor arrangement Download PDFInfo
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- KR20140036984A KR20140036984A KR1020130111494A KR20130111494A KR20140036984A KR 20140036984 A KR20140036984 A KR 20140036984A KR 1020130111494 A KR1020130111494 A KR 1020130111494A KR 20130111494 A KR20130111494 A KR 20130111494A KR 20140036984 A KR20140036984 A KR 20140036984A
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- station
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- substrate
- assembly
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
Abstract
Description
TECHNICAL FIELD The present invention relates to electronic chips, and to a manufacturing method such as semiconductor substrates, and more particularly, to a stepwise process of a machine used for manufacturing semiconductor substrates.
When a semiconductor device is formed through a plating method, a printing method, and a solder ball melting method, solder bumps are formed on the semiconductor substrate. The solder is melted and bonded to connected material such as wires and conductors. Flux is used in most prior art manufacturing methods using solder, which is deposited on the surface of the terminals and wiring. Flux typically covers the deposited surface to remove oxides or prevent new oxidation when the surface is activated. Typically, the solder melts on the deposited surface and spreads throughout the substrate surface. Part of the flux). Removal of such fluxes is one of the common problems in the prior art. The flux between the die and the substrate cannot be completely eliminated, thus lowering the reliability of the device produced.
Prior art devices are generally flux dispensers, reflow furnaces, and flux washers. Each particular solder material often requires the use of different fluxes and different flux cleaning chemistry. Because of the nature of these materials and chemicals, prior art devices must be made suitable for particular materials and specific chemistries. Because of the nature of the fluxes used in the prior art, they were attached to the processing equipment, making it difficult to clean the equipment. The use of fluxes requires a lot of chemical consumption and a lot of maintenance during the manufacturing process.
In some cases, a vacuum system was used to heat the solder, inject the formic acid, minimize the voids and form solder bumps or solder balls. There are several disadvantages, such as the lack of heat transfer media, by using a vacuum system for solder reflow. The heat transfer coefficient of the solder is low, the concentration of formic acid used to remove surface oxides is low, and heat transfer by convection cannot be used to form solder bumps and balls.
The present invention aims to remedy these disadvantages of the prior art.
It is also an object of the present invention to minimize process steps that may be required for flux application and removal.
The invention also provides a substrate in a series of adjustably controlled, individually processing, generally linearly arranged chambers for space saving, step minimization, and efficient chip processing. It is an object of the present invention to provide a manufacturing arrangement in which the loading, processing and unloading of the dies and dies can be carried out linearly.
The present invention relates to a method of manufacturing solder bumps and solder joints on a semiconductor material. In one aspect, the process includes a production table having at least six in-line treatment stations or positons, a " an " loading station " an " the use of a treatment system having a linearly arranged sequential substrate component processing stations with a treated-component "loading station, and an" treated-component "unloading station; Stations may each include the mechanism shown in US Pat. Nos. 6,827,789, 7,008,879, 7,358,175, incorporated herein.
The linear production disclosed herein incorporates a pre-assembled material component, which must be treated as a semiconductor substrate, respectively, and incorporates various aspects and implementations of the '789 and' 879 patents mentioned above. Arranged to transport components to provide a series of closely spaced station locations that can independently adjust temperature, pressure, and atmosphere as shown in the examples .
An initial station into which devices, such as a semiconductor chip / die substrate assembly, are loaded is designated as a load / lock station for the purpose of defining one aspect of the invention. In the loadlock station, a combination of vertically provided, pre-attached but unsoldering dies and substrates is loaded into a support plate and continuously loaded with nitrogen to reduce the amount of oxygen in the housing or chamber at the current ambient atmospheric pressure. It is enclosed in an enclosed climate controlled chamber that is purged by an enclosed climate controlled chamber. The substrates having solder pads in the load / lock chamber and the solder bumps positioned adjacent to each other are easily pre-attached to each other by, for example, thermal energy or ultrasonic energy. The wafer / die loaded plate is moved to the next location designated
In
The support plate, which includes the substrate and the chip or die assembly, is lowered from the enclosure housing and then moved to the next position or next station designated
The processing temperatures at these stations are regulated and regulated based on the particular solder characteristics used / required for a particular run of substrates / semiconductors.
The chip / die and substrate assembly on the plate is moved out of
The chip / die and substrate assembly on the plate is linearly moved out of
At
Subsequently, by controlled movement of the support plate on which the substrate / die assembly is placed, the chip / die and substrate assembly on the plate in
The temperature at
Thereafter, the chip or die and substrate assembly joined on the support plate are moved out of
The atmosphere at
The final stage of the serial thermal processing portion of this semiconductor processing is performed when the substrate assembly is sequentially moved to the final or substrate assembly Un-Load / Lock station. And the chip or die and substrate assembly or substrate joined and processed therein are unloaded from the support plate in the final chamber.
After the previous chip or die substrate assemblies have been moved to their next successive stations, the new raw substrate assembly is sequentially staged through
At each particular station, processing parameters are set to cover all specific solders, which may include high lead, eutectic, and lead free solders.
The processing details of the system include the following:
Load / Lock Station: A chip or die pre-attached on the substrate (without melting the solder) is placed on a support plate in a load station or chamber that is purged with nitrogen gas at room or room temperature to remove moisture and oxygen therein. Loaded and transported from there to the first process station designated as
In
At the next station (# 2), provide heating and vacuum to a temperature above the melting point of the solder, provide a vacuum to the chamber, purge the chamber with formic acid vapor for oxide reduction, and move the assembly to the next station # Go to 3.
In the next station (# 3) it is preferred to provide heating and vacuum to a temperature above the melting point of the solder, to provide a vacuum to the chamber, purge the chamber with formic acid vapor for oxide reduction, and Go to
At
At the
In
The cooled, fully joined substrate assembly is provided at or near room temperature while linearly downstream, while reaching the next or Unload / Lock station. The shuttled, cooled, joined assembly linear downstream is unloaded from it as a now joined substrate assembly.
Reflowing of high lead, eutectic, and lead free solders is completed due to the treatment of formic acid, and the substrate configuration is a chamber of a particular station under atmospheric pressure. Treatment by injection of formic acid into. Due to the provision of a vacuum, removal or minimizing the voids inside the solder during solder reflow occurs after the surface oxide has been reduced and the solder has melted.
However, in the present invention, in order to effectively remove surface oxides such as lead, tin, copper, silver, and indium, only one chemical like formic acid is used. need. Formic acid also contains surface oxides of high-lead solders such as lead and tin compounds, eutectic solders, and lead-free solders, as well as silver, tin or silver, copper, and indium compounds. Can be used to remove.
For example, lead-free solders such as tin / silver (SnAg) have a melting temperature (mT) of 217 ° C. and formic acid reaction temperature is between 180 ° C. and 200 ° C. which can be used in the process of the invention.
As used herein, the removal of moisture on the surface can be easily accomplished by using a stepped, independent, multi-chamber linearly aligned machine. Removal of surface oxides or minimization of internal voids of solder bumpers or balls may also be achieved. By supplying formic acid under atmospheric or higher pressures, large amounts of formic acid molecules can be used in the oxide removal process. It is very important to provide a vacuum and a formic acid vapor charge and vent before melting the solder in the assembly.
In addition, by supplying formic acid under atmospheric pressure or higher, the mechanical system for the transport of chemicals is easy and adjustable. Because of the pressure used, the heating system is capable of uniform and controlled heating of the substrate or semiconductor assembly. Under atmospheric pressure, heat transfer from the heating system to the solder is more efficient. This is especially true because substrate sizes are larger, and system requirements are higher, in modern semiconductor manufacturing.
Since the conduction of heating and cooling can be carried out more efficiently when done at atmospheric pressure or above, the formation of solder bumps and ball joints can be performed in an improved manner. Initial heating and cooling at atmospheric pressure and subsequent heating and vacuum application at elevated temperatures cause the pressure inside the void to move the void to the surface. Such voids can then be easily removed.
The objects and advantages of the present invention can be more clearly understood with reference to the following drawings.
1 is a perspective view showing a linear substrate assembly processing apparatus of the present invention.
Figure 2 is a side view of a chip or die and substrate with a solder arrangement in between when performing the first step of the process of the present invention.
FIG. 3 is a side view similar to that shown in FIG. 2 when the chip or die and the substrate assembly perform a second step of the process of the present invention.
4 is a side view of the processing apparatus of FIG. 1.
FIG. 5 is a perspective view of a chamber cut transversely to a linear heat treatment system showing heater plates and associated shuttle elements of the chamber structure. FIG.
6 is a perspective view of a series of lower heater plates and shuttle elements in linear alignment.
1 is a pre-assembled chip or die through a series of at least six independent and closed station chambers, an initial load lock chamber, and a final unload lock chamber in a
As shown in FIG. 1, a linear
To define a particular aspect of the present invention, devices such as semiconductor chip / die substrate assemblies W as shown in FIGS. 2 and 3 are loaded into the initial station L1 of FIG. 1. In the load lock station L1, a combination of the pre-attached chip or die 14 and the
Assembly W is moved from the load lock position to the first processing chamber at
The
In
The processing temperatures and atmosphere at these stations are adjusted and controlled based on the specific solder characteristics used or required for the particular process of substrate / semiconductor assemblies.
As shown in FIG. 3, the atmosphere in the chamber is vented with formic acid (FA) vapor to remove oxides. In addition, the chip / die on the
The chip / die on the
In
The chip / die on the
With a properly controlled linear advancement of the mechanism in which the
The pre-assembly "W" comprising a substrate or chip or die assembly "W" pre-assembled in the chamber at
Thereafter, by the controlled, stepped, linear advancement in which the
The temperature of
The atmosphere of
The final load / lock station where the wafer die / chip and substrate assembly (W) are joined and treated and the chip or die and substrate assembly "W" is unloaded from its final chamber. When sequentially entered up to L2, the last step in the series of heat treatment sections of this semiconductor processing is performed.
The processing parameters of each particular station are set to cover all specific solders, including high lead, eutectic, and lead free solder.
The system for processing the aforementioned components is shown in more detail in FIG. 5. 5 shows in part a sealable chip-
The
The
The
The processing cycle includes transferring the
A unique apparatus for moving a plurality of ceramic chips arranged in a device tray so as to be supportable traverses below a linear arrangement of lower heaters and an arrangement of top heating plates. The chip device tray provides a rapid movement sequence while minimizing irregularities and downtime in the process. Device trays and chips thereon are intermittently supported in a unique way between the shuttling processes in a linear device.
Claims (5)
The preassembled chip / substrate is loaded into a device support tray in a chamber at an initial Load / Lock station of the processor, and the preassembled chip / substrate Put at atmospheric pressure, the chamber is purged with nitrogen gas;
The pre-assembled chip / substrate is first processed chamber or station by the device tray moved to a position between an upper heater plate and a lower heater plate that can be moved vertically. (a first treatment chamber or station), the preassembled chip / substrate assembly is heated to a temperature below the solder melting temperature, the first treatment chamber is kept below atmospheric pressure, and a formic acid vent is introduced, and a bottom process chamber of the station is lowered;
The pre-assembled chip / substrate assembly enters an open awaition second chamber or station that is open and waiting between the upper and lower heater plates, and the second chamber has its bottom heater. Closed by the vertical movement of the preassembled chip / substrate assembly, heated to a temperature above the melting temperature of the solder, the second chamber is maintained in vacuum, and formic acid vapor vent is introduced into the chamber ;
When the pre-assembled chip / substrate assembly processing chamber is opened by the vertical lowering of its bottom heater plate, the device tray enters into a third chamber or station which is open and waiting between its respective upper and lower heater plates. The chamber is closed, the preassembled chip / substrate assembly is heated to a temperature above the melting point of the solder, vacuum is maintained, and formic acid vapor vent is introduced into the chamber;
The pre-assembled chip / substrate assembly is the fourth station waiting to be opened by the lowering of the bottom or lower heater plate of the fourth station from the third station when the third station is opened by the lowering of its bottom heater plate. Is entered, the preassembled chip / wafer assembly is disposed between the upper and lower plates, and the bottom process section of the chamber is raised by raising the lower heater plate to close the chamber. The chip substrate assembly is heated at a high temperature to handle the solder between the spaced chip and the substrate for lifting and electrically connecting the solder of the chip with the substrate, and the formic acid vapor vent Introduced into the chamber;
The heated and bonded chip / substrate assembly enters the fifth station when the bottom processing chamber section of the fifth station descends, the bottom processing chamber section is elevated to close the chamber, and the assembly is evacuated in vacuum. Heated to peak solder melt temperature to melt and connect the combined chip / substrate assembly, and the chamber is vented with nitrogen;
The connected chip / substrate assembly is transferred from the fifth station to the sixth station when the fifth station is opened and cooled at room temperature or room temperature;
The chip / substrate assembly is transferred to a final downstream loadlock station, and the connected chip / substrate assembly is unloaded from the chamber at the loadlock station;
The first, second, third, and fourth stations are each independently heated to a predetermined temperature of about 150 ° C. to about 270 ° C., at a pressure of about 760 torr for about 10 to about 300 seconds. .
And a preset temperature of the first to fourth stations, respectively, maintained below the melting of the particular solder used in the assembly.
And a preset temperature of the first to fifth stations, respectively, maintained above the melting point of the particular solder used in the assembly.
The preset temperatures of the first and second stations are kept below the melting point of the particular solder used in the assembly, respectively, and the preset temperatures of the third to fifth stations. Is maintained above a melting point of the particular solder used in the assembly.
The pre-set temperature of the fifth station is maintained at the peak temperature of all the stations of the heat treatment device and is higher than the melting point of the particular solder used in the assembly. .
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/573,486 US20130175323A1 (en) | 2002-07-01 | 2012-09-17 | Serial thermal linear processor arrangement |
US13/573,486 | 2012-09-17 |
Publications (2)
Publication Number | Publication Date |
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KR20140036984A true KR20140036984A (en) | 2014-03-26 |
KR101505944B1 KR101505944B1 (en) | 2015-03-27 |
Family
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Application Number | Title | Priority Date | Filing Date |
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KR1020130111494A KR101505944B1 (en) | 2012-09-17 | 2013-09-17 | Serial linear thermal processor arrangement |
Country Status (4)
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JP (1) | JP5778731B2 (en) |
KR (1) | KR101505944B1 (en) |
CN (1) | CN103681363B (en) |
TW (1) | TWI523177B (en) |
Cited By (2)
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DE102014118963A1 (en) | 2013-12-26 | 2015-07-16 | Electronics And Telecommunications Research Institute | Device for generating virtual objects and methods for communication by data distribution service (DDS) in multiple network domains |
CN117577562A (en) * | 2024-01-15 | 2024-02-20 | 北京仝志伟业科技有限公司 | Vacuum device for chip packaging |
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US9226407B2 (en) * | 2002-07-01 | 2015-12-29 | Semigear Inc | Reflow treating unit and substrate treating apparatus |
EP3665718B1 (en) * | 2017-08-07 | 2024-04-24 | Sharpack Technology Pte. Ltd. | Hot wall flux free solder ball treatment arrangement |
CN109822174B (en) * | 2019-03-22 | 2021-05-04 | 清华大学 | Hot air fusion welding method for disassembling circuit board and reducing chip layering rate |
CN110335930A (en) * | 2019-05-21 | 2019-10-15 | 秦启洋 | Fully automatic vacuum eutectic equipment |
CN110993550B (en) * | 2019-12-25 | 2022-12-09 | 北京北方华创微电子装备有限公司 | Semiconductor heat treatment equipment |
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DE19953654A1 (en) * | 1999-11-08 | 2001-05-23 | Pink Gmbh Vakuumtechnik | Method and device for producing a solder connection |
JP3397313B2 (en) * | 1999-12-20 | 2003-04-14 | 富士通株式会社 | Semiconductor device manufacturing method and electronic component mounting method |
JP3378852B2 (en) * | 1999-12-20 | 2003-02-17 | 富士通株式会社 | Heat melting processing equipment |
JP3404021B2 (en) * | 2001-01-18 | 2003-05-06 | 富士通株式会社 | Soldering equipment |
JP3786091B2 (en) | 2002-03-22 | 2006-06-14 | セイコーエプソン株式会社 | Electronic device manufacturing apparatus, electronic device manufacturing method, and electronic device manufacturing program |
US6827789B2 (en) * | 2002-07-01 | 2004-12-07 | Semigear, Inc. | Isolation chamber arrangement for serial processing of semiconductor wafers for the electronic industry |
US8274161B2 (en) * | 2002-07-01 | 2012-09-25 | Semigear Inc | Flux-free chip to substrate joint serial linear thermal processor arrangement |
US20060102078A1 (en) * | 2004-11-18 | 2006-05-18 | Intevac Inc. | Wafer fab |
JP2007000915A (en) * | 2005-06-27 | 2007-01-11 | Shinko Seiki Co Ltd | Soldering method and soldering device |
JP4297945B2 (en) * | 2007-03-01 | 2009-07-15 | パナソニック株式会社 | Heat treatment equipment |
JP2010161207A (en) * | 2009-01-08 | 2010-07-22 | Toyota Industries Corp | Soldering method and soldering equipment |
JP5424201B2 (en) * | 2009-08-27 | 2014-02-26 | アユミ工業株式会社 | Heat-melt treatment apparatus and heat-melt treatment method |
JP2011119352A (en) * | 2009-12-01 | 2011-06-16 | Panasonic Corp | Reflow soldering device and reflow soldering system using the same |
US20120088370A1 (en) * | 2010-10-06 | 2012-04-12 | Lam Research Corporation | Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods |
-
2013
- 2013-09-13 JP JP2013190994A patent/JP5778731B2/en active Active
- 2013-09-16 CN CN201310421281.3A patent/CN103681363B/en active Active
- 2013-09-16 TW TW102133486A patent/TWI523177B/en active
- 2013-09-17 KR KR1020130111494A patent/KR101505944B1/en active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102014118963A1 (en) | 2013-12-26 | 2015-07-16 | Electronics And Telecommunications Research Institute | Device for generating virtual objects and methods for communication by data distribution service (DDS) in multiple network domains |
CN117577562A (en) * | 2024-01-15 | 2024-02-20 | 北京仝志伟业科技有限公司 | Vacuum device for chip packaging |
CN117577562B (en) * | 2024-01-15 | 2024-04-16 | 北京仝志伟业科技有限公司 | Vacuum device for chip packaging |
Also Published As
Publication number | Publication date |
---|---|
JP5778731B2 (en) | 2015-09-16 |
KR101505944B1 (en) | 2015-03-27 |
CN103681363B (en) | 2016-12-07 |
JP2014060401A (en) | 2014-04-03 |
TW201413898A (en) | 2014-04-01 |
CN103681363A (en) | 2014-03-26 |
TWI523177B (en) | 2016-02-21 |
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