JPH11121921A - Method and device for soldering electronic components - Google Patents

Method and device for soldering electronic components

Info

Publication number
JPH11121921A
JPH11121921A JP27677797A JP27677797A JPH11121921A JP H11121921 A JPH11121921 A JP H11121921A JP 27677797 A JP27677797 A JP 27677797A JP 27677797 A JP27677797 A JP 27677797A JP H11121921 A JPH11121921 A JP H11121921A
Authority
JP
Japan
Prior art keywords
soldering
solder
furnace
circuit board
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27677797A
Other languages
Japanese (ja)
Inventor
Hiroshi Machida
浩 町田
Ikuro Kishi
郁朗 岸
Takayasu Soramoto
高寧 空本
Takeshi Yanagisawa
丈志 柳沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP27677797A priority Critical patent/JPH11121921A/en
Publication of JPH11121921A publication Critical patent/JPH11121921A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053Bonding environment
    • H01L2224/85095Temperature settings
    • H01L2224/85096Transient conditions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494Heating methods for reflowing of solder

Abstract

PROBLEM TO BE SOLVED: To improve a method and a device for soldering, by which a proper solder fillet can be formed in a step for mounting chip elements to a circuit board through soldering by preventing an undercut such as soldering failures in a solder layer under the chip. SOLUTION: In a soldering furnace, in which a heating block 14 is provided in a first half as a temperature rising zone along a substrate transfer route within a tunnel-like chamber 4, and a cooling block 15 is provided in a second half as a temperature dropping zone therealong, a circuit board 1 and a chip element 2 applied with a spare solder are fed into the furnace and they are overlapped with each other. Then a solder is melted and solidified for soldering, riding midway between the blocks. In the transfer zone of a temperature dropping zone within the furnace, a needle bundle 18 consisting of many needle-like columns 18a is provided on the substrate-supporting surface of a cooling block 15a close to a positions, where a solder is solidified into a solid phase from a liquid phase, and a circuit board passing there is supported by a point contact. Thus, the unevenness of temperature on the substrate can be suppressed and the entire solder layer be solidified at the same time, thereby forming a solder fillet having no undercut.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、例えばパワート
ランジスタモジュールを対象に、回路基板に半導体チッ
プ(ベアチップ)を含む各種電子部品(表面実装のチッ
プ素子)をリフローはんだ付け法によりはんだマウント
する電子部品のはんだ付け方法,およびはんだ付け装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component for mounting various electronic components (surface mounted chip elements) including a semiconductor chip (bare chip) on a circuit board by a reflow soldering method, for example, for a power transistor module. And a soldering apparatus.

【0002】[0002]

【従来の技術】下面に電極面を形成したチップ素子(ベ
アチップ)を、回路基板(例えばセラミックス基板の両
面に銅箔を直接接合したダイレクトボンデッドカッパー
基板)にはんだマウントする方法として、電極面に予備
はんだを施したチップ素子を回路基板に重ね合わせ、リ
フロー熱源にホットプレートを用いたはんだ付け炉を使
用したリフローはんだ付け法が一般に採用されている。
2. Description of the Related Art A chip element (bare chip) having an electrode surface formed on a lower surface is solder-mounted on a circuit board (for example, a direct bonded copper substrate in which copper foil is directly bonded to both surfaces of a ceramic substrate). A reflow soldering method using a soldering furnace using a hot plate as a reflow heat source, in which a chip element subjected to preliminary soldering is superimposed on a circuit board, is generally adopted.

【0003】次に、頭記したパワートランジスタモジュ
ールを例に、そのモジュール組立体,およびダイボンダ
として採用されている従来のはんだ付け装置の基本構成
を説明する。まず、図3(a) にパワートランジスタの組
立体を示す。図において、1は回路基板(アルミナなど
のセラミックス板1aを挟んでその上下両面に銅箔1
b,1cを接合したダイレクト・ボンデッド・カッパー
基板など)、2は回路基板1の上面側銅箔1bに形成し
た回路パターンにはんだマウントしたパワートランジス
タのチップ素子(ベアチップ)で、チップ素子2はその
下面にはんだ付け面となる電極が形成されており、両者
の間がはんだ(例えば、Pb98%−Sn2%(融点3
22℃),Pb95%−Sn5%(融点314℃),Pb9
3.5%−Sn5%−Ag1.5%(融点296℃))
3により接合されている。
Next, taking the power transistor module described above as an example, a basic configuration of a module assembly thereof and a conventional soldering apparatus employed as a die bonder will be described. First, FIG. 3A shows a power transistor assembly. In the figure, reference numeral 1 denotes a circuit board (copper foil 1
b, 1c, etc.), 2 is a power transistor chip element (bare chip) solder-mounted on a circuit pattern formed on the upper surface side copper foil 1b of the circuit board 1, and the chip element 2 is An electrode serving as a soldering surface is formed on the lower surface, and a solder (for example, Pb 98% -Sn 2% (melting point 3
22 ° C), Pb95% -Sn5% (melting point 314 ° C), Pb9
3.5% -Sn5% -Ag1.5% (melting point 296 [deg.] C.)
3 are joined.

【0004】次に、はんだ付け装置の構成を図4,図5
(a) にて説明する。各図において、はんだ付け装置は、
はんだ付け炉のトンネル状主チャンバー4と、主チャン
バー4の入口,出口側に敷設した基板搬入,搬出用コン
ベヤ5,6と、主チャンバー4の入口側で先記した回路
基板1を1個ずつ搬入コンベヤ5に供給するローダ7
と、出口側でチップ素子2とはんだ付された回路基板を
搬出コンベヤ6から取り出すアンローダ8と、主チャン
バー4の中央部に設定したはんだ付け部9から側方に引
出したチップ素子搬入用の分岐チャンバー10と、分岐
チャンバー10の内部に設置した予備はんだ付け部11
と、はんだ付け面を下に向けてチップ素子2を真空チャ
ックに吸着保持し、かつ分岐チャンバー10の入口側か
ら予備はんだ付け部11を経由して主チャンバー4のは
んだ付け部9へ移送する昇降ユニット付きのチップ搬送
機構12と、分岐チャンバー10の入口側でチップ素子
2を1個ずつチップ搬送機構12に受け渡すチップ用ロ
ーダ13と、主チャンバー4内の搬送経路に沿って炉内
底部側に敷設したホットプレート(リフロー熱源)とか
らなる。ここで、ホットプレートは、主チャンバー4の
入口と中間のはんだ付け部9との間の昇温ゾーンに配列
した電熱ヒータ内蔵の加熱ブロック14と、はんだ付け
部9とチャンバー出口との間の降温ゾーンに配列した水
冷式の冷却ブロック15と、これらの各ブロックの間を
乗り継いで主チャンバー4の入口から搬入した回路基板
1を出口へ向けて間欠的にピッチ送りするウォーキング
ビーム式基板搬送機構(該機構については図6で説明す
る)とから構成されている。
Next, the construction of the soldering apparatus is shown in FIGS.
This will be described in (a). In each figure, the soldering equipment
Tunnel-shaped main chamber 4 of the soldering furnace, substrate loading / unloading conveyors 5 and 6 laid on the entrance and exit sides of main chamber 4, and one circuit board 1 described above at the entrance side of main chamber 4. Loader 7 to supply to carry-in conveyor 5
An unloader 8 for taking out the circuit board soldered to the chip element 2 at the outlet side from the unloading conveyor 6; and a branch for carrying in the chip element drawn laterally from the soldering section 9 set at the center of the main chamber 4. A chamber 10 and a pre-soldering portion 11 installed inside the branch chamber 10
The chip element 2 is sucked and held on a vacuum chuck with the soldering surface facing down, and is transferred from the entrance side of the branch chamber 10 to the soldering section 9 of the main chamber 4 via the preliminary soldering section 11. A chip transfer mechanism 12 with a unit, a chip loader 13 for transferring chip elements 2 one by one to the chip transfer mechanism 12 at the entrance side of the branch chamber 10, and a furnace bottom side along a transfer path in the main chamber 4. And a hot plate (reflow heat source) laid on the floor. Here, the hot plate includes a heating block 14 with a built-in electric heater arranged in a heating zone between the entrance of the main chamber 4 and the intermediate soldering section 9, and a temperature decrease between the soldering section 9 and the chamber outlet. A cooling block 15 of a water-cooling type arranged in a zone, and a walking beam type substrate transport mechanism for intermittently pitching the circuit board 1 carried in from the entrance of the main chamber 4 toward the exit while transiting between these blocks ( The mechanism will be described with reference to FIG. 6).

【0005】また、主チャンバー4にはその入口側から
窒素と水素の混合ガスを吹き込み、前半の昇温ゾーンで
は還元性ガス雰囲気に、また後半の降温ゾーンでは窒素
ガスを流して基板1のはんだ付け面の酸化を防ぎ、併せ
て回路基板1のはんだ付け面に生成した酸化膜を還元除
去してはんだの「濡れ性」を確保するようにしている。
また、分岐チャンバー10の内部には窒素ガスを吹き込
んで不酸化性雰囲気に保ち、チップ素子2に施した予備
はんだ層の酸化を防止している。
Further, a mixed gas of nitrogen and hydrogen is blown into the main chamber 4 from the inlet side, and a reducing gas atmosphere is flowed in the first half of the temperature rising zone, and a nitrogen gas is flowed in the second half of the temperature drop zone to flow the solder of the substrate 1. The attachment surface is prevented from being oxidized, and at the same time, the oxide film formed on the soldering surface of the circuit board 1 is reduced and removed, thereby ensuring the “wetability” of the solder.
Further, nitrogen gas is blown into the inside of the branch chamber 10 to maintain the atmosphere in a non-oxidizing atmosphere, thereby preventing the preliminary solder layer applied to the chip element 2 from being oxidized.

【0006】さらに、前記した加熱ブロック14,冷却
ブロック15は各ブロックごとに温度管理を行い、ブロ
ックの上を乗り継いで炉内搬送される回路基板1が図5
(b)の温度分布で表すように昇温→降温の経過を辿るよ
うにしている。ここで、tHははんだ融点よりも多少高
く設定したはんだ付け温度、tL は主チャンバー4の出
口からはんだ付け済の基板を取り出す際の温度で例えば
50℃程度に設定されている。なお、前記構成のはんだ
付け装置は、タクトシステムを組んで運転制御部からの
指令により各工程を全自動で運転制御するようにしてお
り、特に回路基板を加熱,冷却ブロック間に乗り継いで
搬送する際には、基板を各ブロックの上に受け渡した状
態で数十秒程度停止して予熱,冷却を行うようにしてい
る。
Further, the heating block 14 and the cooling block 15 perform temperature control for each block, and the circuit board 1 transferred in the furnace while being connected on the block is shown in FIG.
As shown by the temperature distribution in (b), the process proceeds from a rise in temperature to a fall in temperature. Here, t H is a soldering temperature set slightly higher than the solder melting point, and t L is a temperature at which the soldered substrate is taken out from the outlet of the main chamber 4 and is set to, for example, about 50 ° C. In the soldering apparatus having the above-described configuration, a tact system is assembled to automatically control the operation of each step according to a command from an operation control unit. In particular, the circuit board is transferred between the heating and cooling blocks while being transferred. In this case, preheating and cooling are performed by stopping the substrate for about several tens of seconds in a state where the substrate is transferred onto each block.

【0007】そして、ローダ7によりはんだ付け面を上
に向けて回路基板1を1個ずつ搬入コンベヤ5に供給す
ると、回路基板1は主チャンバー4の中に進入して加熱
ブロック14に受け渡された後、加熱ブロック14の間
を間欠的に乗り継いではんだ付け部9へ搬送され、ここ
で後記のようにチップ素子2とはんだ付けされ、さらに
後半に敷設した冷却ブロック15の間を乗り継いで出口
まで炉内搬送される。ここで、炉内における前半の昇温
ゾーンでは、回路基板1が加熱ブロック14からの伝熱
により加熱されてはんだ付け温度tH まで昇温し、後半
の降温ゾーンでは冷却ブロック15との間の伝熱により
冷却され、出口では温度tL まで低下するようになる。
When the circuit boards 1 are supplied one by one to the carry-in conveyor 5 with the soldering surface facing upward by the loader 7, the circuit boards 1 enter the main chamber 4 and are transferred to the heating block 14. After that, the heating block 14 is intermittently transferred and transferred to the soldering section 9 where it is soldered to the chip element 2 as described later. Conveyed in the furnace. Here, in the first half of the heating zone in the furnace, the circuit board 1 is heated by the heat transfer from the heating block 14 and rises to the soldering temperature t H , and in the second half of the cooling zone between the cooling block 15 Cooled by heat transfer, the temperature at the outlet drops to t L.

【0008】一方、はんだ付け面を下に向けてローダ1
3により供給されたチップ素子2は、チップ搬送機構1
2の昇降ユニットに取付けた予熱ヒータ付きの真空チャ
ックに吸着保持され、続いてチップ素子2を搬送経路の
途上に配置した予備はんだ付け部11まで移送し、ここ
でチップ素子2のはんだ付け面に予備はんだ層を形成す
る。続いてチップ素子2が分岐チャンバー10を通じて
主チャンバー4のはんだ付け部9に搬入され、ここで予
熱状態で待機して回路基板1の上に、チップ搬送機構1
2の下降操作によりチップ素子2を上方から回路基板1
のチップマウント位置に重ね合わせ、予備はんだ層の面
を基板1に押し付ける。これにより、予備はんだが溶融
してチップ素子2と回路基板1との間がはんだ付けされ
る。その後に、チップ搬送機構12をチップ素子2から
切り離した上で、回路基板1をはんだ付け部9から後半
の降温ゾーンに敷設した冷却ブロック15に受け渡し、
各冷却ブロックの間を乗り継いで主チャンバー4の出口
へ搬送する。この搬送過程では溶融したはんだが液相か
ら固相に凝固し、さらに出口端に到達した際には常温近
くまで冷却され、主チャンバー4の出口側から搬出コン
ベヤ6を経てアンローダ8により取り出される。
On the other hand, with the soldering surface facing down, the loader 1
3 is supplied to the chip transport mechanism 1
The chip element 2 is sucked and held by a vacuum chuck with a preheater attached to the lifting unit 2 and then transferred to the pre-soldering section 11 arranged on the way of the transport path, where the chip element 2 Form a preliminary solder layer. Subsequently, the chip element 2 is carried into the soldering section 9 of the main chamber 4 through the branch chamber 10, where the chip element 2 waits in a preheated state, and is placed on the circuit board 1.
2 lowers the chip element 2 from above to the circuit board 1
And the surface of the preliminary solder layer is pressed against the substrate 1. As a result, the preliminary solder is melted and the chip element 2 and the circuit board 1 are soldered. After that, after separating the chip transport mechanism 12 from the chip element 2, the circuit board 1 is transferred from the soldering section 9 to the cooling block 15 laid in the lower temperature zone in the latter half.
The transfer between the cooling blocks is carried to the outlet of the main chamber 4. In this transport process, the molten solder solidifies from a liquid phase to a solid phase, and when it reaches the outlet end, it is cooled down to near normal temperature, and is taken out from the outlet side of the main chamber 4 via the unloading conveyor 6 by the unloader 8.

【0009】次に、先記のように主チャンバー4内で加
熱ブロック14,冷却ブロック15の間を乗り継いで基
板1を炉内で搬送するウォーキングビーム式の基板搬送
機構を図6(a),(b) の原理図で説明する。すなわち、直
線状に並ぶ冷却,加熱ブロック14,15にはその上面
側に左右一対の凹溝16が形成されている。また各ブロ
ック間にまたがって前記凹溝16を通すように長尺な左
右一対の基板支持ビーム17(ビームは凹溝19の深さ
よりも小)が敷設されており、該ビーム17を駆動部
(図示せず)に連結してウォーキングビーム式の基板搬
送機構を構成している。
Next, as described above, a walking beam type substrate transfer mechanism for transferring the substrate 1 in the furnace while transferring between the heating block 14 and the cooling block 15 in the main chamber 4 is shown in FIGS. This will be described with reference to the principle diagram (b). That is, the cooling and heating blocks 14 and 15 arranged in a straight line have a pair of left and right concave grooves 16 formed on the upper surface side. Further, a pair of long left and right substrate support beams 17 (the beam is smaller than the depth of the concave groove 19) are laid so as to pass through the concave groove 16 between the blocks, and the beam 17 is driven by a driving unit ( (Not shown) to form a walking beam type substrate transfer mechanism.

【0010】かかる構成で、基板支持ビーム17を駆動
部の操作により、図示のように上昇,前進,下降
,後退を1サイクルとする動作を行うことにより、
左右のビーム17の間にまたがって載置した回路基板1
をブロック間を乗り継いで矢印P方向に間欠的に搬送す
る。なお、ビーム17が下降すると回路基板1が加熱
ブロック14,冷却ブロック15の上面に載り、この位
置で基板が加熱,ないし冷却される。
In such a configuration, the substrate support beam 17 is operated by operating the drive unit, as shown in FIG.
Circuit board 1 placed between right and left beams 17
Is intermittently conveyed in the direction of the arrow P while being transferred between blocks. When the beam 17 is lowered, the circuit board 1 is placed on the upper surfaces of the heating block 14 and the cooling block 15, and the board is heated or cooled at this position.

【0011】[0011]

【発明が解決しようとする課題】ところで、前記のはん
だ付け炉を使用して回路基板1にチップ素子2をはんだ
マウントしたものでは、次に記すようなはんだ付け不良
の欠陥が多々発生する。すなわち、炉内の基板搬送経路
に沿って敷設した電熱ヒータ内蔵の加熱ブロック14,
水冷管を内蔵した冷却ブロック15は、ブロック全体を
均等に加熱,冷却することが実際には困難であり、局部
的な温度のばらつきによりブロック上面の温度分布が均
一にならない。また、はんだ付け炉に搬入した回路基板
(セラミックス基板)1を、昇温ゾーンの加熱ブロック
14を乗り継いではんだ付け温度まで予熱すると、その
搬送途上で加わる不均一な加熱などにより回路基板1の
板面には100〜200μm程度の反りが生じて変形
し、回路基板1と加熱,冷却ブロック14,15の上面
に接触する部分と接触しない部分とが生じる。このため
に、加熱,冷却ブロックとブロックの上面に載置した回
路基板1との間では基板全域で熱が平均に伝熱せず、こ
のために炉内で搬送する回路基板1に温度むらが生じる
ようになる。
By the way, in the case where the chip element 2 is solder-mounted on the circuit board 1 by using the above-mentioned soldering furnace, many defects such as the following defective soldering occur. That is, the heating block 14 with a built-in electric heater laid along the substrate transfer path in the furnace,
In the cooling block 15 having a built-in water cooling tube, it is actually difficult to uniformly heat and cool the entire block, and the temperature distribution on the upper surface of the block is not uniform due to local temperature variations. Further, when the circuit board (ceramic substrate) 1 carried into the soldering furnace is preheated to the soldering temperature by connecting to the heating block 14 in the heating zone, the board of the circuit board 1 is unevenly heated during the transportation. The surface is warped by about 100 to 200 μm and deformed, and there are portions that contact the circuit board 1 and the upper surfaces of the heating and cooling blocks 14 and 15 and portions that do not contact the upper surface. Therefore, heat is not transferred evenly between the heating / cooling block and the circuit board 1 placed on the upper surface of the block over the entire area of the board, so that the temperature of the circuit board 1 conveyed in the furnace becomes uneven. Become like

【0012】この場合に、特に炉内後半の降温ゾーンで
の搬送領域で、はんだが液相から固相に相転移して凝固
する過程で回路基板1に温度むらが生じていると、はん
だ層全体が同時に凝固せず、先に凝固したはんだ部分の
体積収縮によって末凝固部分のはんだが表面張力により
引っ張られるように流動し、その結果として図3(b)で
表すように、チップ素子2の下ではんだ層3にアンダー
カット3aが生成する。このアンダーカット3aの発生
により、良好なはんだフィレットが形成されなくなるほ
か、アンダーカット3aの部分に働く切欠き効果でこの
部分に応力集中が生じてはんだ接合強度が低下する。
In this case, if the circuit board 1 has a temperature unevenness in the process of solidifying the solder from the liquid phase to the solid phase, particularly in the transport region in the temperature lowering zone in the latter half of the furnace, the solder layer The whole does not solidify at the same time, and the solder in the last solidified portion flows by the volume contraction of the previously solidified solder portion so as to be pulled by the surface tension. As a result, as shown in FIG. Undercut 3a is generated in solder layer 3 below. Due to the occurrence of the undercut 3a, a good solder fillet is not formed, and stress concentration occurs in this portion due to a notch effect acting on the portion of the undercut 3a, so that the solder joint strength is reduced.

【0013】また、頭記したパワートランジスタモジュ
ールのように、実使用環境の下ではんだ付け部に100
℃を超えるようなヒートショックが繰り返し加わると、
アンダーカット3aの切欠き部を起点として、はんだ層
3内にクラックが発生してチップ素子2が回路基板1か
ら剥離するといった致命的トラブルに進展するおそれが
ある。
Further, as in the power transistor module described above, 100
When heat shocks exceeding ℃ are repeatedly applied,
Starting from the notch of the undercut 3a, there is a possibility that a crack may occur in the solder layer 3 and the chip element 2 may develop into a fatal trouble such as peeling off from the circuit board 1.

【0014】この発明は、上記の点に鑑みなされたもの
であり、その目的は前記課題を解決し、回路基板にチッ
プ素子をはんだマウントするはんだ付け工程で、チップ
下のはんだ層にはんだ付け性の欠陥要因となるアンダー
カットのない良好なはんだフィレットが形成できるよう
に改良した電子部品のはんだ付け方法および,はんだ付
け装置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to solve the above-mentioned problems, and to provide a soldering step for solder-mounting a chip element on a circuit board. It is an object of the present invention to provide an improved method and apparatus for soldering an electronic component so that a good solder fillet free from undercuts, which can cause defects, can be formed.

【0015】[0015]

【課題を解決するための手段】上記目的を達成するため
に、この発明のはんだ付け方法によれば、炉内にホット
プレートを敷設したはんだ付け炉を用い、回路基板,お
よび予備はんだを施したチップ素子を炉内に搬入して両
者を重ね合わせ、その搬送途上ではんだを溶融,凝固さ
せてはんだ付けを行うものにおいて、炉内ではんだが液
相から固相に凝固する地点の搬送領域で、回路基板を下
面側から点接触式に支持するようにする(請求項1)。
In order to achieve the above object, according to the soldering method of the present invention, a circuit board and a preliminary solder are applied by using a soldering furnace having a hot plate laid in the furnace. The chip element is loaded into the furnace, the two are superimposed, and the solder is melted and solidified in the course of the transfer to perform the soldering. In the transfer area where the solder solidifies from the liquid phase to the solid phase in the furnace The circuit board is supported in a point contact manner from the lower surface side (claim 1).

【0016】上記のはんだ付け方法により、炉内の降温
ゾーンで溶融した予備はんだが液相から固相に凝固する
搬送領域では、回路基板がホットプレートに対して点接
触で支持される。これにより、ホットプレートの上面に
基板の底面を重ね合わせて面接触させた支持状態と較べ
て、基板の支持面積,したがって支持体との間の伝熱面
積が極端に小さくなり、両者の間が伝熱的には熱絶縁に
近い状態となる。したがって、回路基板は伝熱的にプレ
ート側の温度分布の影響を殆ど受けず、これに起因して
基板の温度むらを引き起こすことがなくなる。これによ
り、回路基板は周囲の炉内ガス雰囲気(均一な温度)と
の関係で基板温度が決まるようになり、チップ素子を接
合するはんだ層の全域が殆ど同時に液相から固相に凝固
するようになる。この結果、チップ下部分のはんだ層に
アンダーカットが生じることがなく、良好なはんだフィ
レットが形成される。
According to the above-described soldering method, the circuit board is supported in point contact with the hot plate in the transport region where the preliminary solder melted in the temperature lowering zone in the furnace solidifies from the liquid phase to the solid phase. As a result, the supporting area of the substrate, that is, the heat transfer area between the supporting body and the supporting body is extremely small as compared with a supporting state in which the bottom surface of the substrate is superimposed on the upper surface of the hot plate and brought into surface contact. The heat transfer is in a state close to thermal insulation. Therefore, the circuit board is hardly affected by the temperature distribution on the plate side in terms of heat transfer, and the temperature unevenness of the board due to this is not caused. As a result, the substrate temperature of the circuit board is determined in relation to the ambient gas atmosphere (uniform temperature) in the furnace, so that the entire area of the solder layer joining the chip elements solidifies from the liquid phase to the solid phase almost simultaneously. become. As a result, an undercut does not occur in the solder layer under the chip, and a good solder fillet is formed.

【0017】また、前記はんだ付け方法の実施に用いる
この発明のはんだ付け装置は、トンネル状チャンバー内
の基板搬送経路に沿ってその前半の昇温ゾーンに加熱ブ
ロック,後半の降温ゾーンに冷却ブロックを敷設して構
成したはんだ付け炉に対して、回路基板,および予備は
んだを施したチップ素子を炉内に搬入するとともに、両
者を重ね合わせて前記加熱,冷却ブロックの間を乗り継
ぎ搬送し、その搬送途上ではんだを溶融,凝固させては
んだ付けを行うようにしたものにおいて、はんだ付け炉
の炉内における降温ゾーンの搬送領域で、はんだが液相
から固相に凝固する地点に敷設した冷却ブロックの基板
支持面を多数本の針状支柱を並べた剣山で構成し、この
剣山の上に回路基板を支えて点接触式に支持するように
する(請求項2)。
In the soldering apparatus of the present invention used for carrying out the soldering method, a heating block is provided in a first half temperature rising zone and a cooling block is provided in a second half cooling zone along a substrate transfer path in a tunnel-shaped chamber. The circuit board and the chip element to which the pre-soldering is performed are carried into the soldering furnace constructed by laying, and the two are superimposed and transferred between the heating and cooling blocks. The soldering is performed by melting and solidifying the solder on the way. In the transfer area of the cooling zone in the furnace of the soldering furnace, the cooling block laid at the point where the solder solidifies from the liquid phase to the solid phase The substrate supporting surface is constituted by a sword mountain in which a number of needle-like columns are arranged, and the circuit board is supported on the sword mountain to support in a point contact manner.

【0018】かかる構成により、チップ素子をはんだ付
けした回路基板が炉内の降温ゾーンを移動する領域で、
予備はんだが液相から固相に凝固する地点に差しかかる
と、基板が剣山の上に載って点接触式に支持される。こ
れにより、ブロックとの間で殆ど伝熱的な影響を受ける
ことなしにはんだの凝固が進行するようになる。したが
って、このはんだ付け装置を採用することにより、はん
だ付け方法の項で述べたように、チップ下にはアンダー
カットのないはんだフィレットが形成されるようにな
る。
With such a configuration, in a region where the circuit board to which the chip element is soldered moves in the temperature lowering zone in the furnace,
When the pre-solder reaches the point where the pre-solder solidifies from the liquid phase to the solid phase, the substrate rests on the sword and is supported in a point contact manner. This allows the solidification of the solder to proceed with almost no thermal effect between the block. Therefore, by employing this soldering apparatus, as described in the section of the soldering method, a solder fillet without undercut is formed below the chip.

【0019】[0019]

【発明の実施の形態】以下、この発明の実施の形態を図
1(a),(b) に基づいて説明する。なお、実施例の図中で
図3〜図6に対応する同一部材には同じ符号が付してあ
る。すなわち、図示実施例に示したはんだ付け装置は、
基本的に図4〜図6で述べた従来装置と同じ構成である
が、炉内の降温ゾーンに敷設した冷却ブロック15のう
ち、特にはんだ付け付部9で溶融した予備はんだが液相
から固相に凝固する箇所に敷設した冷却ブロック15a
については、ブロックに水冷管を設けず、かつブロック
の上面側には多数本の針状支柱18aを植設して剣山1
8を構成してこの剣山18の上に回路基板1とチップ素
子2との組立体を点接触式に支えるようにしている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 (a) and 1 (b). In the drawings of the embodiment, the same members corresponding to FIGS. 3 to 6 are denoted by the same reference numerals. That is, the soldering device shown in the illustrated embodiment is
Basically, the configuration is the same as that of the conventional apparatus described with reference to FIGS. 4 to 6, but among the cooling blocks 15 laid in the temperature lowering zone in the furnace, in particular, the preliminary solder melted in the soldering part 9 is solidified from the liquid phase. Cooling block 15a laid at the point where it solidifies into a phase
With respect to the first embodiment, a water cooling tube is not provided in the block, and a large number of needle-like columns 18a are planted on the upper surface side of the block.
8, the assembly of the circuit board 1 and the chip element 2 is supported on the sword 18 in a point contact manner.

【0020】なお、剣山18の設置箇所を決定するに
は、回路基板1のチップ搭載位置に熱電対を搭載して実
際にはんだ付け炉に入口側から搬入し、その搬送途上に
おける各地点での基板温度の変化を熱電対で計測する。
そして、基板が昇温ゾーンを通過して降温ゾーンに入っ
た後、熱電対の測定温度がはんだの凝固する温度になる
位置を剣山18の設置箇所とする。
In order to determine the location of the blade 18, a thermocouple is mounted on the chip mounting position of the circuit board 1 and is actually loaded into the soldering furnace from the entrance side, and at each point during the transportation. The change in substrate temperature is measured with a thermocouple.
After the substrate passes through the heating zone and enters the cooling zone, the position where the measured temperature of the thermocouple becomes a temperature at which the solder solidifies is defined as the installation location of the sword mountain 18.

【0021】かかる構成により、回路基板1にチップ素
子2をはんだマウントするはんだ付け工程で、主チャン
バー4内のはんだ付け部9で基板1にチップ素子2がは
んだ付けされた後、基板1が炉内の後半の降温ゾーンに
移動して冷却ブロック15aに設置した剣山18の上に
差しかかると、この位置ではんだ液相から固相に凝固す
る。
With this configuration, after the chip element 2 is soldered to the substrate 1 at the soldering section 9 in the main chamber 4 in the soldering step of solder mounting the chip element 2 on the circuit board 1, the substrate 1 is placed in a furnace. When it moves to the temperature lowering zone in the latter half of the inside and reaches the sword mountain 18 installed in the cooling block 15a, it solidifies from the solder liquid phase to the solid phase at this position.

【0022】ここで、降温ゾーンにおけるはんだの温度
特性を図2に示す。図2において、グラフの横軸は回路
基板1をはんだ付け炉に搬入してからの経過時間を表
し、縦軸は基板1とチップ素子2との間を接合したはん
だ層3の温度を示す。また、温度t1 ははんだ3の液相
線温度、t2 は固相線温度、時間T1 ははんだ層3の温
度が液相線温度t1 になった時間、T2 は固相線温度t
2 になった時間を表しており、特性線Aで示すはんだ層
3の温度がt1 からt2 に低下する過程ではんだの凝固
が進行する。
FIG. 2 shows the temperature characteristics of the solder in the temperature lowering zone. In FIG. 2, the horizontal axis of the graph represents the elapsed time since the circuit board 1 was carried into the soldering furnace, and the vertical axis represents the temperature of the solder layer 3 joining the substrate 1 and the chip element 2. The temperature t1 is the liquidus temperature of the solder 3, t2 is the solidus temperature, time T1 is the time when the temperature of the solder layer 3 has reached the liquidus temperature t1, and T2 is the solidus temperature t.
The solidification of the solder proceeds as the temperature of the solder layer 3 shown by the characteristic line A decreases from t1 to t2.

【0023】ところで、先記のように図示実施例の構成
では、図2における時間T1 〜T2の時間帯では、回路
基板1が図1(b) で示すように冷却ブロック15aに設
けた剣山18の上に載って点接触で支持される。したが
って、基板1は冷却ブロック15aとの間の伝熱の影響
を殆ど受けることがなく、寧ろ炉内のガス雰囲気により
均温冷却されてはんだ温度がt1 からt2 に低下するよ
うな経緯を辿る。これにより、従来のように回路基板1
を冷却ブロックの上に面接触させた状態で生じる基板の
温度むらが解消され、はんだ層3の全域で凝固が同時に
進行するようになる。この結果、チップ素子2の下には
図1(a) で示すようにアンダーカットのない良好なはん
だフィレットが形成される。
By the way, as described above, in the configuration of the illustrated embodiment, the circuit board 1 is mounted on the cooling block 15a as shown in FIG. And is supported in point contact. Accordingly, the substrate 1 is hardly affected by the heat transfer between the substrate 1 and the cooling block 15a, but rather is uniformly cooled by the gas atmosphere in the furnace, and follows the process of lowering the solder temperature from t1 to t2. As a result, the circuit board 1 can be
The unevenness in the temperature of the substrate caused when the substrate is brought into surface contact with the cooling block is eliminated, and the solidification proceeds simultaneously in the entire region of the solder layer 3. As a result, a good solder fillet without undercut is formed under the chip element 2 as shown in FIG.

【0024】[0024]

【発明の効果】以上述べたように、この発明のはんだ付
け方法,および装置によれば、はんだ付け炉に搬入して
回路基板にチップ素子をはんだマウントするはんだ付け
工程において、はんだ付けした基板を降温ゾーンに移送
してはんだを液相から固相に凝固させる過程で、回路基
板に温度むらが生じるのを抑えてはんだ層の全体を同時
に凝固させることができる。これにより、チップ素子の
下にアンダーカットのない良好なはんだフィレットが形
成されて欠陥のない高品質なはんだ付けが実現できる。
As described above, according to the soldering method and apparatus of the present invention, in the soldering step of carrying a chip element onto a circuit board by carrying it into a soldering furnace, the soldered board is removed. In the process of transferring the solder to a solid phase from a liquid phase to a solid phase by transferring to a temperature lowering zone, it is possible to suppress the occurrence of temperature unevenness in the circuit board and simultaneously solidify the entire solder layer. As a result, a good solder fillet without undercut is formed under the chip element, and high quality soldering without defects can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の実施例によるはんだ付け装置の主要
部の構成図であり、(a) ははんだ付け炉の炉内構成図、
(b) は(a) 図における剣山付き冷却ブロックの断面図
FIG. 1 is a configuration diagram of a main part of a soldering apparatus according to an embodiment of the present invention, (a) is a configuration diagram in a furnace of a soldering furnace,
(b) is a cross-sectional view of the cooling block with a sword peak in (a).

【図2】回路基板がはんだ付け炉内の降温ゾーンを通過
する際におけるはんだ温度の推移を表す特性線図
FIG. 2 is a characteristic diagram showing a change in solder temperature when a circuit board passes through a cooling zone in a soldering furnace.

【図3】この発明の実施対象となるパワートランジスタ
モジュールの組立構造図であり、(a) は正常なはんだ付
けによるモジュール全体の組立図、(b) はチップ下にア
ンダーカットが生じた欠陥のあるはんだ付け状態を表す
部分図
3A and 3B are assembly diagrams of a power transistor module to which the present invention is applied; FIG. 3A is an assembly diagram of the entire module by normal soldering; FIG. Partial view showing a certain soldering state

【図4】はんだ付け装置の全体構成を略示的に示す平面
配置図
FIG. 4 is a plan view schematically showing the overall configuration of the soldering apparatus.

【図5】図4におけるはんだ付け炉の詳細図であり、
(a) は搬送経路に沿った断面側視図、(b) は炉内の温度
分布図
FIG. 5 is a detailed view of the soldering furnace in FIG. 4,
(a) is a cross-sectional side view along the transport path, and (b) is a temperature distribution diagram inside the furnace.

【図6】図4のはんだ付け炉に組み込んだウォーキング
ビーム式基板搬送機構の原理図であり、(a) は側面図、
(b) は正面図
6 is a principle view of a walking beam type substrate transfer mechanism incorporated in the soldering furnace of FIG. 4, (a) is a side view,
(b) is a front view

【符号の説明】[Explanation of symbols]

1 回路基板 2 チップ素子 3 はんだ層 4 はんだ付け炉の主チャンバー 9 はんだ付け部 14 加熱ブロック 15 冷却ブロック 17 ウォーキングビーム式基板搬送機構の基板支持
ビーム 18 剣山 18a 針状支柱
DESCRIPTION OF SYMBOLS 1 Circuit board 2 Chip element 3 Solder layer 4 Main chamber of soldering furnace 9 Soldering part 14 Heating block 15 Cooling block 17 Substrate support beam of walking beam type substrate transfer mechanism 18 Sword mountain 18a Needle-shaped support

───────────────────────────────────────────────────── フロントページの続き (72)発明者 柳沢 丈志 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takeshi Yanagisawa Fuji Electric Co., Ltd. 1-1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】チップ素子を回路基板の導体パターンには
んだマウントする電子部品のはんだ付け方法であり、炉
内にホットプレートを敷設したはんだ付け炉を用い、回
路基板,および予備はんだを施したチップ素子を炉内に
搬入して両者を重ね合わせ、その搬送途上ではんだを溶
融,凝固させてはんだ付けを行うものにおいて、炉内で
はんだが液相から固相に凝固する地点の搬送領域で、回
路基板を下面側から点接触式に支持するようにしたこと
を特徴とする電子部品のはんだ付け方法。
1. A method for soldering an electronic component in which a chip element is solder-mounted on a conductor pattern of a circuit board, using a soldering furnace in which a hot plate is laid in a furnace, using a circuit board and a pre-soldered chip. The element is carried into the furnace, the two are superimposed, and the solder is melted and solidified in the course of the conveyance to perform soldering. A method of soldering an electronic component, wherein a circuit board is supported in a point contact manner from a lower surface side.
【請求項2】請求項1記載のはんだ付け方法の実施に用
いるはんだ付け装置であり、トンネル状チャンバー内の
基板搬送経路に沿ってその前半の昇温ゾーンに加熱ブロ
ック,後半の降温ゾーンに冷却ブロックを敷設して構成
したはんだ付け炉に対して、回路基板,および予備はん
だを施したチップ素子を炉内に搬入するとともに、両者
を重ね合わせて前記加熱,冷却ブロックの間を乗り継ぎ
搬送し、その搬送途上ではんだを溶融,凝固させてはん
だ付けを行うようにしたものにおいて、はんだ付け炉の
炉内における降温ゾーンの搬送領域で、はんだが液相か
ら固相に凝固する地点に敷設した冷却ブロックの基板支
持面を多数本の針状支柱を並べた剣山で構成したことを
特徴とする電子部品のはんだ付け装置。
2. A soldering apparatus used for carrying out the soldering method according to claim 1, wherein a heating block is provided in a first half of the heating zone and a cooling block is provided in a second half of the cooling zone along a substrate transfer path in the tunnel-shaped chamber. The circuit board and the chip element subjected to the preliminary soldering are carried into the furnace in a soldering furnace configured by laying blocks, and the two are superimposed and transferred between the heating and cooling blocks. The soldering is performed by melting and solidifying the solder in the middle of the transfer. In the transfer area of the cooling zone in the furnace of the soldering furnace, cooling is laid at the point where the solder solidifies from the liquid phase to the solid phase. An electronic component soldering device, wherein a substrate supporting surface of a block is constituted by a sword mountain in which a large number of needle-like columns are arranged.
JP27677797A 1997-10-09 1997-10-09 Method and device for soldering electronic components Pending JPH11121921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27677797A JPH11121921A (en) 1997-10-09 1997-10-09 Method and device for soldering electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27677797A JPH11121921A (en) 1997-10-09 1997-10-09 Method and device for soldering electronic components

Publications (1)

Publication Number Publication Date
JPH11121921A true JPH11121921A (en) 1999-04-30

Family

ID=17574222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27677797A Pending JPH11121921A (en) 1997-10-09 1997-10-09 Method and device for soldering electronic components

Country Status (1)

Country Link
JP (1) JPH11121921A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6709890B2 (en) 2000-02-15 2004-03-23 Renesas Technology Corporation Method of manufacturing semiconductor integrated circuit device
JP2009010430A (en) * 2008-10-15 2009-01-15 Renesas Technology Corp Method of mounting semiconductor element
JP2010278087A (en) * 2009-05-26 2010-12-09 Panasonic Electric Works Co Ltd Mounting method
JP2012134189A (en) * 2010-12-01 2012-07-12 Athlete Fa Kk Heating apparatus and heating method
WO2018139670A1 (en) * 2017-01-30 2018-08-02 株式会社新川 Mounting device and mounting system
US11465224B2 (en) * 2020-06-18 2022-10-11 Kulicke And Soffa Industries, Inc. Ovens for equipment such as die attach systems, flip chip bonding systems, clip attach systems, and related methods

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6709890B2 (en) 2000-02-15 2004-03-23 Renesas Technology Corporation Method of manufacturing semiconductor integrated circuit device
JP2009010430A (en) * 2008-10-15 2009-01-15 Renesas Technology Corp Method of mounting semiconductor element
JP2010278087A (en) * 2009-05-26 2010-12-09 Panasonic Electric Works Co Ltd Mounting method
JP2012134189A (en) * 2010-12-01 2012-07-12 Athlete Fa Kk Heating apparatus and heating method
WO2018139670A1 (en) * 2017-01-30 2018-08-02 株式会社新川 Mounting device and mounting system
US11545462B2 (en) 2017-01-30 2023-01-03 Shinkawa Ltd. Mounting apparatus and mounting system
US11465224B2 (en) * 2020-06-18 2022-10-11 Kulicke And Soffa Industries, Inc. Ovens for equipment such as die attach systems, flip chip bonding systems, clip attach systems, and related methods

Similar Documents

Publication Publication Date Title
JPH0992682A (en) Soldering method and soldering device
US3710069A (en) Method of and apparatus for selective solder reflow
US20080223609A1 (en) Electronic device and electronic component mounting method
JP5778731B2 (en) Array of continuous linear heat treatment equipment
TWI258192B (en) Manufacturing apparatus of electronic device, manufacturing method of electronic device, and manufacturing program of electronic device
JPH11121921A (en) Method and device for soldering electronic components
JP5533650B2 (en) Automatic soldering equipment
KR20030076454A (en) Apparatus, method and program for manufacturing electronic device
JP4830635B2 (en) Soldering method and soldering apparatus
JP4785486B2 (en) Electronic device manufacturing method and manufacturing apparatus
JP3240876B2 (en) Mounting method of chip with bump
JPH10178268A (en) Method and device for soldering electronic parts
KR102212841B1 (en) Method and apparatus for manufacturing semiconductor devices
JP2002141658A (en) Method and device for flow soldering
JP2004214553A (en) Reflow furnace
JPH10163620A (en) Method and apparatus for soldering electronic components
JP2597695Y2 (en) Reflow furnace
JPH10233484A (en) Method and device for assembling semiconductor device
JP2006100492A (en) Fixing method of electronic component onto support plate
JP2003209347A (en) Method and apparatus for reflow soldering
JPH10202362A (en) Soldering method and soldering apparatus
KR20060115145A (en) Lead-free solder reflow apparatus having dip-type cooling unit
JP2006147880A (en) Method and device for bonding semiconductor with solder bump
JP2705280B2 (en) Reflow equipment
JPH09148729A (en) Solder reflowing device and manufacture of printed board