JP3240876B2 - Mounting method of chip with bump - Google Patents

Mounting method of chip with bump

Info

Publication number
JP3240876B2
JP3240876B2 JP08810795A JP8810795A JP3240876B2 JP 3240876 B2 JP3240876 B2 JP 3240876B2 JP 08810795 A JP08810795 A JP 08810795A JP 8810795 A JP8810795 A JP 8810795A JP 3240876 B2 JP3240876 B2 JP 3240876B2
Authority
JP
Japan
Prior art keywords
chip
bumps
substrate
solder
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP08810795A
Other languages
Japanese (ja)
Other versions
JPH08288630A (en
Inventor
省二 酒見
憲 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=13933659&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP3240876(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP08810795A priority Critical patent/JP3240876B2/en
Publication of JPH08288630A publication Critical patent/JPH08288630A/en
Application granted granted Critical
Publication of JP3240876B2 publication Critical patent/JP3240876B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、バンプ付きチップの実
装方法に関するものである。The present invention relates to relates to a method of mounting bar pump with a chip.

【０００２】[0002]

【従来の技術】バンプ（突出電極）付きのチップは、サ
イズを小さくでき、基板に高密度実装できることから、
近年、次第に広範囲に使用されるようになってきてい
る。2. Description of the Related Art A chip with bumps (protruding electrodes) can be reduced in size and mounted on a substrate at a high density.
In recent years, it has become increasingly widely used.

【０００３】従来、バンプ付きのチップは、一般に、次
のようにして製造されていた。すなわち、チップの電極
にフラックスを塗布して半田ボールを載せる。次にチッ
プを加熱炉へ送って加熱し、半田ボールを溶融させた
後、チップを冷却することにより、溶融した半田ボール
を固化させてバンプを生成する。Conventionally, a chip provided with bumps has been generally manufactured as follows. That is, a flux is applied to the electrodes of the chip, and the solder balls are mounted. Next, the chip is sent to a heating furnace where it is heated to melt the solder balls, and then the chips are cooled to solidify the melted solder balls to form bumps.

【０００４】[0004]

【発明が解決しようとする課題】上記従来方法では、半
田ボールは加熱炉の空気中にて加熱・溶融されていたた
め、バンプの表面に酸化膜が生じる。したがってバンプ
を基板の電極に搭載し、再度加熱・溶融させて基板の電
極に接着（半田付け）する際に、この酸化膜が半田のヌ
レ性を阻害し、半田付け状態が不良になりやすいという
問題点があった。In the above conventional method, the solder ball is heated and melted in the air of the heating furnace, so that an oxide film is formed on the surface of the bump. Therefore, when the bumps are mounted on the electrodes of the substrate, heated and melted again and adhered (soldered) to the electrodes of the substrate, the oxide film inhibits the wetting of the solder, and the soldering state is likely to be defective. There was a problem.

【０００５】したがって本発明は上記従来方法の問題点
を解消し、バンプのヌレ性を改善できるバンプ付きチッ
プの実装方法を提供することを目的とする。[0005] Accordingly, the present invention is to solve the above conventional methods, and to provide a Luba amplifier with chip mounting method can improve the wettability of the bumps.

【０００６】[0006]

【課題を解決するための手段】このために本発明のバン
プ付きチップの実装方法は、チップの電極上に半田を設
ける工程と、このチップを低酸素雰囲気中で加熱するこ
とにより半田を溶融させる工程と、チップを冷却し半田
を固化させてバンプを生成する工程と、以上の工程で作
られたバンプ付きチップを基板に搭載し、この基板を加
熱することによりバンプを基板の電極に半田付けする工
程とを含み、前記低酸素雰囲気を酸素濃度２０００ｐｐ
ｍ以下のチッソ雰囲気とした。For this purpose, a method for mounting a chip with bumps according to the present invention comprises the steps of providing solder on the electrode of the chip and melting the solder by heating the chip in a low oxygen atmosphere. work in process and a step of generating bumps solidify the solder to cool the chips, above steps
The mounted chip with bumps is mounted on a substrate, and this substrate is
Soldering the bumps to the electrodes on the board by heating
And a degree of oxygen concentration 2000pp the low oxygen atmosphere
m or less.

【０００７】また以上の工程で作られたバンプ付きチッ
プを基板に搭載し、この基板を加熱することによりバン
プを基板の電極に半田付けするようにした。Further, a chip with bumps manufactured in the above process is mounted on a substrate, and the bumps are soldered to electrodes of the substrate by heating the substrate.

【０００８】[0008]

【０００９】[0009]

【作用】上記構成によれば、半田は低酸素雰囲気中で加
熱・溶融されるので、バンプの表面に酸化膜が生じるこ
とはない。したがってこのバンプが形成されたバンプ付
きチップを基板の電極に搭載して加熱すると基板の電極
にヌレ性よく半田付けされる。According to the above construction, since the solder is heated and melted in a low oxygen atmosphere, no oxide film is formed on the surface of the bump. Therefore, when the chip with bumps on which the bumps are formed is mounted on the electrodes of the substrate and heated, the chips are soldered to the electrodes of the substrate with good wettability.

【００１０】[0010]

【実施例】次に、本発明の実施例を図面を参照しながら
説明する。図１は本発明の第一実施例のバンプ付きチッ
プの製造工程とバンプ付きチップの実装工程の説明図で
あり、工程順に示している。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram of a manufacturing process of a chip with bumps and a mounting process of a chip with bumps according to a first embodiment of the present invention, which is shown in the order of processes.

【００１１】まず図１（ａ）に示すように、チップ１の
上面にマトリクス状に多数個形成された電極２上にフラ
ックス３を塗布する。次に電極２上に半田ボール４を搭
載する（図１（ｂ）参照）。次にこの半田ボール４を加
熱・溶融させる。First, as shown in FIG. 1A, a flux 3 is applied to a plurality of electrodes 2 formed in a matrix on the upper surface of a chip 1. Next, the solder balls 4 are mounted on the electrodes 2 (see FIG. 1B). Next, the solder ball 4 is heated and melted.

【００１２】図２は本発明の第一実施例のチップの加熱
炉の断面図である。図中、１０は加熱炉であり、チッソ
ガス供給部１１からパイプ１２を通してチッソガスが供
給される。加熱炉１０の内部にはチップ１を右方へ搬送
するコンベア１３が設けられている。またコンベア１３
の上方にはファン１４とヒータ１５が設けられている。
右端部のファン１４の真下にはヒータ１５は設けられて
おらず、このファン１４は冷却用のファンとなってい
る。したがって図１（ｂ）に示すチップ１はコンベア１
３により右方へ搬送されながら、チッソ雰囲気中で半田
ボール４の溶融温度（１８３℃程度）以上まで加熱さ
れ、次いで冷却されることにより、溶融していた半田ボ
ール４は固化し、バンプ４が生成される。FIG. 2 is a sectional view of a chip heating furnace according to a first embodiment of the present invention. In the figure, reference numeral 10 denotes a heating furnace to which nitrogen gas is supplied from a nitrogen gas supply unit 11 through a pipe 12. A conveyor 13 for transporting the chips 1 to the right is provided inside the heating furnace 10. Conveyor 13
A fan 14 and a heater 15 are provided above.
The heater 15 is not provided directly below the fan 14 at the right end, and the fan 14 is a cooling fan. Therefore, the chip 1 shown in FIG.
While being conveyed to the right by 3, the solder ball 4 is heated to a temperature equal to or higher than the melting temperature (about 183 ° C.) of the solder ball 4 in a nitrogen atmosphere and then cooled, so that the molten solder ball 4 is solidified and the bump 4 Generated.

【００１３】図１（ｃ）は、図２に示す工程によりバン
プ４が生成されたチップ１を示している。次にこのチッ
プ１を基板５に搭載する（図１（ｄ）参照）。基板５の
上面には電極６がマトリクス状に多数個形成されてお
り、この電極６上にフラックス７を塗布し、バンプ４を
電極６に位置合わせしてチップ１を基板５に搭載する。FIG. 1C shows the chip 1 on which the bumps 4 have been formed by the process shown in FIG. Next, the chip 1 is mounted on a substrate 5 (see FIG. 1D). A large number of electrodes 6 are formed in a matrix on the upper surface of the substrate 5. A flux 7 is applied on the electrodes 6, the bumps 4 are aligned with the electrodes 6, and the chip 1 is mounted on the substrate 5.

【００１４】次にチップ１が積載された基板５を加熱炉
（図外）へ送り、バンプ４の溶融温度（１８３℃程度）
以上まで加熱し、次いで冷却する。するとバンプ４は溶
融・固化し、基板５の電極６に接着（半田付け）され
る。図１（ｅ）は以上のようにして基板５に実装された
チップ１を示している。図２に示す工程において、半田
ボール４はチッソ雰囲気中で加熱・溶融されているた
め、これにより生成されたバンプ４の表面には酸化膜は
ほとんど生じていない。したがって図１（ｅ）に示すよ
うにバンプ４はヌレ性よく基板５の電極６に接着され
る。Next, the substrate 5 on which the chip 1 is mounted is sent to a heating furnace (not shown), and the melting temperature of the bump 4 (about 183 ° C.)
Heat to above and then cool. Then, the bumps 4 are melted and solidified, and are bonded (soldered) to the electrodes 6 on the substrate 5. FIG. 1E shows the chip 1 mounted on the substrate 5 as described above. In the step shown in FIG. 2, since the solder ball 4 is heated and melted in a nitrogen atmosphere, almost no oxide film is formed on the surface of the bump 4 generated thereby. Therefore, as shown in FIG. 1E, the bump 4 is adhered to the electrode 6 of the substrate 5 with good wettability.

【００１５】なお低酸素雰囲気を実現する手段として
は、図２に示すようにチッソガスを用いる方法がコスト
や運転管理上有利である。本発明者の実験によれば、酸
素濃度を２０００ｐｐｍ以下、更に望ましくは１０００
ｐｐｍ以下にすれば、酸化膜の発生を防止するという所
期の目的は実質的に達成される。したがって本発明にお
いて低酸素雰囲気とは、このように酸素濃度が低く、バ
ンプ４の表面に酸化膜を実質的に生じない雰囲気を含む
ものである。As a means for realizing a low oxygen atmosphere, a method using nitrogen gas as shown in FIG. 2 is advantageous in terms of cost and operation management. According to the experiments of the present inventors, the oxygen concentration was set to 2000 ppm or less, more preferably 1000 ppm.
When the content is less than ppm, the intended purpose of preventing generation of an oxide film is substantially achieved. Therefore, in the present invention, the low oxygen atmosphere includes an atmosphere in which the oxygen concentration is low and an oxide film is not substantially formed on the surface of the bump 4.

【００１６】図３は本発明の第二実施例のバンプ付きチ
ップの製造工程の説明図である。第二実施例では、第一
実施例のフラックス３や半田ボール４に替えてクリーム
半田８をチップ１の電極２上に塗布する（図３（ａ）参
照）。以下の工程は第一実施例と同様であって、図２に
示す加熱炉１０でクリーム半田８を加熱・溶融・固化さ
せることにより、バンプ８を生成する。図３（ｂ）はバ
ンプ８が生成されたチップ１を示すものであって、図１
（ｃ）に相当している。以下、図１（ｄ）（ｅ）と同様
の工程によりチップ１を基板５に実装する。FIG. 3 is an explanatory view of a manufacturing process of a chip with bumps according to a second embodiment of the present invention. In the second embodiment, cream solder 8 is applied on the electrodes 2 of the chip 1 instead of the flux 3 and the solder balls 4 of the first embodiment (see FIG. 3A). The following steps are the same as those in the first embodiment. The bumps 8 are generated by heating, melting, and solidifying the cream solder 8 in the heating furnace 10 shown in FIG. FIG. 3B shows the chip 1 on which the bumps 8 have been generated.
(C). Hereinafter, the chip 1 is mounted on the substrate 5 by the same steps as those shown in FIGS.

【００１７】[0017]

【発明の効果】本発明は、半田ボールやクリーム半田な
どの半田を低酸素雰囲気中で加熱・溶融させるので、バ
ンプの表面に酸化膜を生じず、したがって基板の電極に
ヌレ性よく半田付けできる。また低酸素雰囲気として酸
素濃度２０００ｐｐｍ以下のチッソ雰囲気とすることに
より、コストを低減でき、また運転管理も容易となる。According to the present invention, since solder such as solder balls and cream solder is heated and melted in a low oxygen atmosphere, no oxide film is formed on the surface of the bump, and therefore, the solder can be soldered to the electrode of the substrate with good wettability. . By using a nitrogen atmosphere having an oxygen concentration of 2000 ppm or less as the low oxygen atmosphere, the cost can be reduced and the operation management can be facilitated.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第一実施例のバンプ付きチップの製造
工程とバンプ付きチップの実装工程の説明図FIG. 1 is an explanatory diagram of a manufacturing process of a chip with bumps and a mounting process of a chip with bumps according to a first embodiment of the present invention.

【図２】本発明の第一実施例のチップの加熱炉の断面図FIG. 2 is a sectional view of a chip heating furnace according to a first embodiment of the present invention.

【図３】本発明の第二実施例のバンプ付きチップの製造
工程の説明図FIG. 3 is an explanatory view of a manufacturing process of a chip with bumps according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ チップ ４ 半田ボール（バンプ） ５ 基板 ６ 電極 ８ クリーム半田 １０ 加熱炉 １１ チッソガス供給部 Reference Signs List 1 chip 4 solder ball (bump) 5 substrate 6 electrode 8 cream solder 10 heating furnace 11 nitrogen gas supply unit

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−145732（ＪＰ，Ａ) 特開 平４−280633（ＪＰ，Ａ) 特開 平４−73937（ＪＰ，Ａ) 特開 平７−58150（ＪＰ，Ａ) 特開 平５−243331（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/34 B23K 31/02 H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-145732 (JP, A) JP-A-4-280633 (JP, A) JP-A-4-73937 (JP, A) JP-A-7- 58150 (JP, A) JP-A-5-243331 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/34 B23K 31/02 H01L 21/60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】チップの電極上に半田を設ける工程と、こ
のチップを低酸素雰囲気中で加熱することにより半田を
溶融させる工程と、チップを冷却し半田を固化させてバ
ンプを生成する工程と、以上の工程で作られたバンプ付
きチップを基板に搭載し、この基板を加熱することによ
りバンプを基板の電極に半田付けする工程とを含み、前
記低酸素雰囲気が酸素濃度２０００ｐｐｍ以下のチッソ
雰囲気であることを特徴とするバンプ付きチップの実装
方法。A step of providing solder on the electrodes of the chip; a step of melting the solder by heating the chip in a low oxygen atmosphere; and a step of cooling the chip to solidify the solder to form bumps. , more bumped chips made mounted on the substrate in the step, and a step of soldering the bumps to the electrodes of the substrate by heating the substrate, wherein the low oxygen atmosphere the oxygen concentration 2000ppm following nitrogen atmosphere A method for mounting a chip with bumps, characterized in that:
JP08810795A 1995-04-13 1995-04-13 Mounting method of chip with bump Expired - Lifetime JP3240876B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP08810795A JP3240876B2 (en) 1995-04-13 1995-04-13 Mounting method of chip with bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08810795A JP3240876B2 (en) 1995-04-13 1995-04-13 Mounting method of chip with bump

Publications (2)

Publication Number Publication Date
JPH08288630A JPH08288630A (en) 1996-11-01
JP3240876B2 true JP3240876B2 (en) 2001-12-25

Family

ID=13933659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08810795A Expired - Lifetime JP3240876B2 (en) 1995-04-13 1995-04-13 Mounting method of chip with bump

Country Status (1)

Country Link
JP (1) JP3240876B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117323A (en) * 1997-06-23 1999-01-22 Matsushita Electric Ind Co Ltd Reflow equipment of conductive ball
JP4045517B2 (en) * 1998-09-25 2008-02-13 澁谷工業株式会社 Flux transfer device
JP4590783B2 (en) * 2001-06-13 2010-12-01 パナソニック株式会社 Method for forming solder balls
KR101881063B1 (en) 2011-12-12 2018-07-25 삼성전자주식회사 Manufacturing method of bump
JP6830935B2 (en) * 2018-09-25 2021-02-17 株式会社タムラ製作所 Method for manufacturing thermosetting flux composition and electronic substrate

Also Published As

Publication number Publication date
JPH08288630A (en) 1996-11-01

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