JP3965795B2 - Electronic component soldering method - Google Patents

Electronic component soldering method Download PDF

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Publication number
JP3965795B2
JP3965795B2 JP23725498A JP23725498A JP3965795B2 JP 3965795 B2 JP3965795 B2 JP 3965795B2 JP 23725498 A JP23725498 A JP 23725498A JP 23725498 A JP23725498 A JP 23725498A JP 3965795 B2 JP3965795 B2 JP 3965795B2
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Prior art keywords
solder
paste
electronic component
melting point
chips
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JP2000068637A (en
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典久 今泉
棚橋　　昭
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PROBLEM TO BE SOLVED: To prevent voids from being generated to the utmost in the soldered part of an electronic component in the case where the component is mounted on a board by reflow soldering. SOLUTION: This soldering method is executed as follow: a solder paste 8 is fed to a board 1 and thereafter, both sides of a power transistor 5 are supported by solder chips 9 and 10, which are mounted on the paste 8, have different melting points, have a melting point higher than that of the solder in the paste 8 and have a height higher than the thickness of the paste 8, and a reflow heating is performed in this state to heat the paste 8 and the chips 9 and 10. Whereupon, first, the paste 8 is molten and vapor, which is generated at the time of this melting, escapes out from the space, which is ensured by the chips 9 and 10 between the transistor 5 and the paste 8, to the outside. Then, the chip 9 on one side on the side of the low melting point of the chips 9 and 10 is molten, then, the other chip 10 is molten. As a result, the transistor 5 is slanted so that it comes into contact with the molten solder surface in its slanted state, air is eliminated and it is eliminated that the air is left as voids in the soldered part of the transistor 5.

Description

【０００１】
【発明の属する技術分野】
本発明は、電子部品をリフロー半田付けによって半田付けする方法に係り、特にリフロー半田付け時に半田ペーストから発生する蒸気がボイドとして残ることを防止しようとしたものに関する。
【０００２】
【従来の技術】
半田付け部にボイドが残留することを防止する技術として特開昭６３−３００５１９号公報に開示されたものがある。これは、半導体チップを半田付けによってヒートシンクにダイボンディングしてなる半導体装置において、ダイボンディング面を、その縁部よりも中央部ほど隆起した傾斜面として形成するというものである。
【０００３】
このようにすれば、半導体チップとダイボンディング面との間に介装された半田の厚みは、ダイボンディング面の中央部から縁部側にいくほど厚くなる。このため、ダイボンディング作業時における半田の溶融および凝固は、まず、ダイボンディング面の中央部付近から始まり、その縁部へと徐々に進んで行くことになる。このため、半導体チップとヒートシンクとの間に存在していた空気は順次押し出されて外部に放出されることとなり、半導体チップとヒートシンクとの間の隙間に存在する空気がボイドとして半田付け部に残留することを防止できるというものである。
【０００４】
また、特開平８−２９３６７０号公報には、回路基板に電子部品を半田付けする場合、回路基板の上に、半田箔と、この半田箔よりも融点が高く且つ高さが高い４個の半田チップとを置き、半田チップにて電子部品の四隅を支え、この状態で加熱を行うことが記載されている。
【０００５】
これによれば、加熱が行われると、まず半田箔が溶融し、このとき半田箔から発生する蒸気は半田チップによって確保されている空間から外部に逃げ出る。その後、半田チップが溶融し、電子部品が基板に半田付けされるため、蒸気がボイドとして半田付け部に残留することがない、というものである。
【０００６】
【発明が解決しようとする課題】
例えば、リフロー半田付けによって電子部品を回路基板に実装する場合、従来では、まず、回路基板に半田ペーストをスクリーン印刷或いはノズル等により塗布し、その後、半田ペーストの塗布部に電子部品を搭載し、そして、リフロー半田付けを行う。
【０００７】
上記半田ペーストは、粉末半田とフラックスとを混練したもので、そのフラックス中には、ロジン、活性剤、増粘剤、チクソ剤、溶剤などの様々な成分が含まれている。このため、リフロー半田付け時に、半田ペーストが加熱されると、フラックス中の低沸点の成分が蒸発し、半田付け部にいわゆるボイドとして残留するという問題を生ずる。特に、電子部品がパワートランジスタのような比較的大きな半田付け面積をもったものでは、リフロー半田付け時に発生した蒸気は電子部品と基板との間から抜け出し難く、ボイドとして残留する傾向が高い。
【０００８】
このように、半田ペースト中の低沸点成分が蒸発することによって発生した蒸気は、特開昭６３−３００５１９号公報に開示された構成では、外部に逃がすことはできない。また、特開平８−２９３６７０号公報に開示された構成では、４個の半田チップの融点が同じであるため、その４個の半田チップが同時に溶融し、その結果、電子部品の半田付け面が水平に下がって溶融半田面に接するようになり、このとき空気を巻き込み易く、ボイドとして残留し易くなるというあらたな問題を生ずる。
【０００９】
本発明は上記の事情に鑑みてなされたもので、その目的は、電子部品をリフロー半田付けする場合に、その半田付け部にボイドが発生することをより効果的に防止できる電子部品の実装方法を提供するにある。
【００１０】
【課題を解決するための手段】
上記の目的を達成するために、本発明は、
電子部品を半田付けしようとする部材に半田ペーストを供給し、その後、リフロー加熱することにより前記半田ペーストを溶融させて前記電子部品を前記部材に半田付けする方法において、
融点が互いに異なる半田材であって、前記部材に供給された前記半田ペースト中の半田よりも融点が高く且つ高さが前記半田ペーストの厚さよりも高い半田材によって前記電子部品の両側を支え、この状態で前記リフロー加熱を行って、前記半田ペースト中の前記半田が溶融し、その後に前記電子部品の両側を支えた前記半田材のうち低融点側の前記半田材が溶融し、最後に高融点側の前記半田材が溶融するようにしたことを特徴とするものである。
この場合、前記リフロー加熱はリフロー炉にて行い、前記電子部品の両側を支えた前記融点が互いに異なる前記半田材のうち低融点側の前記半田材の方が先に前記リフロー炉内に侵入するようにすることが好ましい。また、前記電子部品の両側を支えた前記融点が互いに異なる前記半田材の融点温度の差は、１０〜３０℃であることが好ましい。
【００１１】
この構成によれば、加熱が行われると、まず半田ペーストが溶融し、このとき発生する蒸気は、半田材によって確保されている空間から外部に逃げ出る。次に、半田材のうち、融点の低い側の一方の半田材が溶融し、これに遅れて他方の半田材が溶融するので、電子部品は傾いた状態で溶融半田面に接するようになる。このため、空気は排除され、半田付け部に空気がボイドとして残ることがなくなる。
【００１２】
【発明の実施の形態】
以下、本発明の一実施例を電子部品をセラミック基板にリフロー半田付けによって実装する場合に適用して図面を参照しながら説明する。
【００１３】
図１は電子部品を実装した後のセラミック基板（以下、基板）１を示すもので、基板１上の導体２に例えばセラミックコンデンサ３、ＩＣ４、パワートランジスタ５、ターミナル６等が半田７によって接続されている。
【００１４】
これらの電子部品のリフロー半田付けによる実装方法を説明するに、基板１には、図２に示すように、導体２が予め所定の回路パターンで形成されており、第１工程（ペースト塗布工程）では、その導体２上に半田ペースト８をスクリーン印刷手段、ノズル等による供給手段によって塗布する。この場合、半田ペースト８は、１００μｍ程度の厚さで塗布される。
【００１５】
次の第２工程（半田材搭載工程）では、図３および図４に示すように、半田付け面積の比較的大きなパワートランジスタ５を接続する導体２上の半田ペースト８に半田材としての半田チップ９，１０を載せる。この場合、その半田ペースト８が図４に示すように矩形状であったとすると、導体２上の半田ペースト８の一方側の２隅部に半田チップ９を搭載し、他方の側の２隅部に半田チップ１０を搭載する。これら半田チップ９，１０の表面には、粘着材が塗布されており、これにより、半田チップ９，１０を安定的に固定できるようにしている。
【００１６】
ところで、半田ペースト８の両側の半田チップ９，１０は、融点が互いに異なり、半田ペースト８中の半田の融点よりも１０℃〜５０℃程度高い半田によって形成されている。この場合、リフロー炉への基板１の侵入方向が矢印Ａ方向であるとすると、低融点側の半田チップ９は、先にリフロー炉内に侵入する側である図示右側の２隅部に搭載される。また、半田チップ９，１０の高さＨは、互いに同じか、若しくは多少の違い（数十μｍ）はあるが、半田ペースト８の厚さＴよりも高く形成されている。
【００１７】
具体的には、低融点側の半田チップ９は、半田ペースト８中の粉末半田（共晶半田）の融点よりも約２０℃高い半田材料（Ｓｎ７３重量％、Ｐｂ２７重量％ またはＳｎ５６重量％、Ｐｂ４４重量％等）により形成され、高融点側の半田チップ１０は、半田ペースト８中の半田の融点よりも約４０℃高い半田材料（Ｓｎ８２重量％、Ｐｂ１８重量％ またはＳｎ５３重量％、Ｐｂ４７重量％等）により形成されている。なお、半田チップ９，１０の融点の差は、１０℃〜３０℃が好ましい。また、半田チップ９，１０の高さＨは、１５０μｍ程度に形成されている。
【００１８】
さて、パワートランジスタ５の半田ペースト８上に半田チップ９，１０を搭載した後の第３工程（電子部品搭載工程）では、図５に示すように、半田チップ９，１０上にパワートランジスタ５を搭載すると共に、他の半田ペースト８上にセラミックコンデンサ３、ＩＣ４、ターミナル６等を搭載する。
【００１９】
その後の第４工程（リフロー加熱工程）では、基板１をリフロー炉内に入れて加熱する。ところで、半田ペースト８は、粉末半田とフラックスとを混練したもので、そのフラックス中には、ロジン、活性剤、増粘剤、チクソ剤、溶剤などの様々な成分を含んでいる。
【００２０】
そして、リフロー炉での加熱により、まず、半田ペースト８中に含まれている上記のような成分のうち、低沸点成分（１５０℃よりも低い温度で蒸発する成分）が蒸発する。また、半田ペースト８中には、吸湿した水分が含まれているが、この水分も蒸発する。このとき、半田チップ９，１０により半田ペースト８とパワートランジスタ５との間には、図６に示すように、空間Ｇが確保されているため、半田ペースト８から蒸発した蒸気は、矢印Ｂで示すように、半田ペースト８とパワートランジスタ５との間の空間Ｇから外部に逃げ出る。なお、上記の低沸点成分とは、ロジンなどの常温固体成分を溶解し、ペースト化するために用いられる溶剤（従って、導体２への印刷後は不要）や、部品粘着性、リフロー特性に影響を与えない成分である。
【００２１】
次いで、図７に示すように、半田ペースト８（粉末半田）が溶融する。その後、半田ペースト８の次に融点の低い半田チップ９が溶融し、最後に半田チップ１０が溶融する。このように、半田チップ９，１０が時間的に前後して溶融するので、半田チップ９の溶融時には、パワートランジスタ５は、一方側が自重により下がって図８に示すように傾いた状態となり、そして、半田チップ１０が溶融する際には、他方が自重により下がって行き、図９に示すように、溶融半田にパワートランジスタ５の接続面全体が接するようになる。
【００２２】
このため、パワートランジスタ５の下面（接続面）は、溶融半田面に対して低融点側の半田チップ９側から高融点側の半田チップ１０側に向かって順次接触してゆくようになるので、溶融半田面との間にある空気は、溶融半田内に巻き込まれることなく、円滑に外部に排除される。従って、パワートランジスタ５の半田付け部にボイドが残ることなく、良好に半田付けできる。
【００２３】
もちろん、パワートランジスタ５以外の他のセラミックコンデンサ３、ＩＣ４、ターミナル６は、半田付け面積が小さいので、半田チップ９，１０のようなものがなくても、リフロー加熱によってボイドを発生させることなく、良好に半田付けできる。
【００２４】
なお、本発明は、上記し勝つ図面に示す実施例に限定されるものではなく、次のような変形或いは拡張が可能である。
半田材は、半田チップ９，１０に代えて、半田ボールであっても良く、その形状は問わない。
半田チップ９，１０は、両側に２個ずつに限られず、３個ずつでも良い。棒状のものでは、１個ずつで済む。
電子部品を半田付けする対象物は基板１に限られない。
【図面の簡単な説明】
【図１】本発明の一実施例を示す実装後の基板の断面図
【図２】基板に半田ペーストを塗布した状態で示す断面図
【図３】半田ペースト上に半田チップを搭載した状態で示す断面図
【図４】半田ペースト上に半田チップを搭載した状態で示す平面図
【図５】電子部品を搭載した状態で示す断面図
【図６】リフロー加熱の初期の状態を説明するための拡大断面図
【図７】リフロー加熱時の半田ペーストが溶融した状態で示す断面図
【図８】一方の半田チップが溶融した状態で示す断面図
【図９】他方の半田チップが溶融した状態で示す断面図
【符号の説明】
図中、１は基板、２は導体、５はパワートランジスタ（電子部品）、８は半田ペースト、９，１０は半田チップ（半田材）である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of soldering an electronic component by reflow soldering, and more particularly to an attempt to prevent vapor generated from a solder paste from remaining as a void during reflow soldering.
[0002]
[Prior art]
Japanese Patent Laid-Open No. Sho 63-300519 discloses a technique for preventing voids from remaining in a soldered portion. This is a semiconductor device in which a semiconductor chip is die-bonded to a heat sink by soldering, and the die-bonding surface is formed as an inclined surface that protrudes from the edge toward the center.
[0003]
In this way, the thickness of the solder interposed between the semiconductor chip and the die bonding surface increases as it goes from the center of the die bonding surface to the edge side. For this reason, the melting and solidification of the solder during the die bonding operation starts from the vicinity of the center of the die bonding surface and gradually proceeds to the edge thereof. For this reason, the air existing between the semiconductor chip and the heat sink is sequentially pushed out and released to the outside, and the air existing in the gap between the semiconductor chip and the heat sink remains as a void in the soldering portion. It is possible to prevent that.
[0004]
Japanese Patent Application Laid-Open No. 8-293670 discloses that when an electronic component is soldered to a circuit board, a solder foil and four solders having a higher melting point and higher height than the solder foil are provided on the circuit board. It is described that a chip is placed, the four corners of the electronic component are supported by solder chips, and heating is performed in this state.
[0005]
According to this, when heating is performed, the solder foil is first melted, and the vapor generated from the solder foil escapes from the space secured by the solder chip to the outside. Thereafter, the solder chip is melted and the electronic component is soldered to the substrate, so that the vapor does not remain as a void in the soldering portion.
[0006]
[Problems to be solved by the invention]
For example, when an electronic component is mounted on a circuit board by reflow soldering, conventionally, first, a solder paste is first applied to the circuit board by screen printing or a nozzle, and then the electronic component is mounted on the solder paste application portion. Then, reflow soldering is performed.
[0007]
The solder paste is a mixture of powder solder and flux, and the flux contains various components such as rosin, activator, thickener, thixotropic agent and solvent. For this reason, when the solder paste is heated during reflow soldering, a component having a low boiling point in the flux evaporates and remains as a so-called void in the soldered portion. In particular, when the electronic component has a relatively large soldering area such as a power transistor, the vapor generated during reflow soldering is difficult to escape from between the electronic component and the substrate, and tends to remain as a void.
[0008]
As described above, the vapor generated by the evaporation of the low boiling point component in the solder paste cannot be released to the outside in the configuration disclosed in Japanese Patent Application Laid-Open No. 63-300519. In the configuration disclosed in Japanese Patent Laid-Open No. 8-293670, since the melting points of the four solder chips are the same, the four solder chips are melted at the same time. As a result, the soldering surface of the electronic component is reduced. It comes down horizontally and comes into contact with the molten solder surface. At this time, it is easy to entrain air, and it becomes easy to remain as a void.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic component mounting method that can more effectively prevent voids from being generated in a soldered portion of an electronic component when reflow soldering is performed. To provide.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides:
In a method of soldering the electronic component to the member by supplying a solder paste to the member to be soldered to the electronic component and then melting the solder paste by reflow heating,
Solder materials having different melting points, supporting both sides of the electronic component by a solder material having a melting point higher than the solder in the solder paste supplied to the member and a height higher than the thickness of the solder paste, In this state, the reflow heating is performed , the solder in the solder paste is melted, and then the solder material on the low melting point side of the solder material supporting both sides of the electronic component is melted. The solder material on the melting point side is melted .
In this case, the reflow heating is performed in a reflow furnace, and among the solder materials having different melting points that support both sides of the electronic component, the solder material on the low melting point side first enters the reflow furnace. It is preferable to do so. Moreover, it is preferable that the difference in melting point temperature of the solder materials having different melting points supporting both sides of the electronic component is 10 to 30 ° C.
[0011]
According to this configuration, when heating is performed, the solder paste is first melted, and the vapor generated at this time escapes from the space secured by the solder material to the outside. Next, among the solder materials, one solder material having a lower melting point is melted, and the other solder material is melted after this, so that the electronic component comes into contact with the molten solder surface in an inclined state. For this reason, air is excluded and air does not remain as a void in the soldering portion.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings by applying to an electronic component mounted on a ceramic substrate by reflow soldering.
[0013]
FIG. 1 shows a ceramic substrate (hereinafter referred to as a substrate) 1 after mounting electronic components. For example, a ceramic capacitor 3, an IC 4, a power transistor 5, a terminal 6, and the like are connected to a conductor 2 on the substrate 1 by solder 7. ing.
[0014]
A method for mounting these electronic components by reflow soldering will be described. As shown in FIG. 2, a conductor 2 is formed in advance in a predetermined circuit pattern on the substrate 1, and the first step (paste application step). Then, the solder paste 8 is applied onto the conductor 2 by a screen printing means, a supply means such as a nozzle. In this case, the solder paste 8 is applied with a thickness of about 100 μm.
[0015]
In the next second step (solder material mounting step), as shown in FIGS. 3 and 4, a solder chip as a solder material is applied to the solder paste 8 on the conductor 2 connecting the power transistor 5 having a relatively large soldering area. Put 9,10. In this case, assuming that the solder paste 8 has a rectangular shape as shown in FIG. 4, solder chips 9 are mounted on two corners on one side of the solder paste 8 on the conductor 2, and two corners on the other side. The solder chip 10 is mounted on. An adhesive material is applied to the surfaces of the solder chips 9 and 10, so that the solder chips 9 and 10 can be stably fixed.
[0016]
Incidentally, the solder chips 9 and 10 on both sides of the solder paste 8 are formed of solder having different melting points and higher by about 10 ° C. to 50 ° C. than the melting point of the solder in the solder paste 8. In this case, assuming that the intrusion direction of the substrate 1 into the reflow furnace is the arrow A direction, the solder chip 9 on the low melting point side is mounted at the two corners on the right side in the drawing, which is the side that enters the reflow furnace first. The The heights H of the solder chips 9 and 10 are the same as each other or slightly different (several tens of μm), but are formed higher than the thickness T of the solder paste 8.
[0017]
Specifically, the solder chip 9 on the low melting point side is made of a solder material (Sn 73 wt%, Pb 27 wt% or Sn 56 wt%, Pb 44) that is about 20 ° C. higher than the melting point of the powder solder (eutectic solder) in the solder paste 8. The solder chip 10 on the high melting point side is formed of a solder material (Sn 82 wt%, Pb 18 wt% or Sn 53 wt%, Pb 47 wt%, etc.) higher than the melting point of the solder in the solder paste 8. ). The difference in melting point between the solder chips 9 and 10 is preferably 10 ° C to 30 ° C. Further, the height H of the solder chips 9 and 10 is formed to be about 150 μm.
[0018]
In the third process (electronic component mounting process) after mounting the solder chips 9 and 10 on the solder paste 8 of the power transistor 5, as shown in FIG. 5, the power transistor 5 is mounted on the solder chips 9 and 10. In addition to mounting, the ceramic capacitor 3, IC 4, terminal 6, etc. are mounted on another solder paste 8.
[0019]
In the subsequent fourth step (reflow heating step), the substrate 1 is placed in a reflow furnace and heated. By the way, the solder paste 8 is obtained by kneading powder solder and a flux, and the flux contains various components such as rosin, activator, thickener, thixotropic agent, and solvent.
[0020]
Then, by the heating in the reflow furnace, first, of the above components contained in the solder paste 8, the low boiling point component (the component that evaporates at a temperature lower than 150 ° C.) evaporates. The solder paste 8 contains moisture that has been absorbed, but this moisture also evaporates. At this time, a space G is secured between the solder paste 8 and the power transistor 5 by the solder chips 9 and 10 as shown in FIG. As shown, escape from the space G between the solder paste 8 and the power transistor 5 to the outside. The above low boiling point components affect the solvent used to dissolve and paste a room temperature solid component such as rosin (and therefore not required after printing on the conductor 2), component adhesion, and reflow characteristics. It is a component that does not give.
[0021]
Next, as shown in FIG. 7, the solder paste 8 (powder solder) is melted. Thereafter, the solder chip 9 having the next lowest melting point after the solder paste 8 is melted, and finally the solder chip 10 is melted. Thus, since the solder chips 9 and 10 are melted before and after the time, when the solder chip 9 is melted, the power transistor 5 is tilted as shown in FIG. When the solder chip 10 is melted, the other is lowered by its own weight, and as shown in FIG. 9, the entire connection surface of the power transistor 5 comes into contact with the molten solder.
[0022]
For this reason, the lower surface (connection surface) of the power transistor 5 comes into contact with the molten solder surface sequentially from the solder chip 9 side on the low melting point side toward the solder chip 10 side on the high melting point side. The air between the molten solder surface is smoothly removed outside without being caught in the molten solder. Therefore, it is possible to perform good soldering without leaving voids in the soldering portion of the power transistor 5.
[0023]
Of course, since the ceramic capacitor 3, IC4, and terminal 6 other than the power transistor 5 have a small soldering area, even if there is no solder chip 9, 10, no voids are generated by reflow heating. Can be soldered well.
[0024]
The present invention is not limited to the embodiments shown in the above-described drawings, and the following modifications or expansions are possible.
The solder material may be a solder ball instead of the solder chips 9 and 10, and the shape thereof is not limited.
The number of solder chips 9 and 10 is not limited to two on both sides, but may be three. For rod-shaped ones, only one piece is enough.
The object to which the electronic component is soldered is not limited to the substrate 1.
[Brief description of the drawings]
1 is a cross-sectional view of a substrate after mounting according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a substrate with a solder paste applied. FIG. 3 is a state in which a solder chip is mounted on the solder paste. FIG. 4 is a plan view showing a state where a solder chip is mounted on a solder paste. FIG. 5 is a cross-sectional view showing a state where an electronic component is mounted. FIG. 6 is a diagram for explaining an initial state of reflow heating. Enlarged cross-sectional view [FIG. 7] Cross-sectional view showing a state where a solder paste is melted during reflow heating [FIG. 8] Cross-sectional view showing a state where one solder chip is melted [FIG. 9] In a state where the other solder chip is melted Sectional view shown
In the figure, 1 is a substrate, 2 is a conductor, 5 is a power transistor (electronic component), 8 is a solder paste, and 9 and 10 are solder chips (solder material).

Claims (3)

電子部品を半田付けしようとする部材に半田ペーストを供給し、その後、リフロー加熱することにより前記半田ペーストを溶融させて前記電子部品を前記部材に半田付けする方法において、
融点が互いに異なる半田材であって、前記部材に供給された前記半田ペースト中の半田よりも融点が高く且つ高さが前記半田ペーストの厚さよりも高い半田材によって前記電子部品の両側を支え、この状態で前記リフロー加熱を行って、前記半田ペースト中の前記半田が溶融し、その後に前記電子部品の両側を支えた前記半田材のうち低融点側の前記半田材が溶融し、最後に高融点側の前記半田材が溶融するようにしたことを特徴とする電子部品の半田付け方法。In a method of soldering the electronic component to the member by supplying a solder paste to the member to be soldered to the electronic component and then melting the solder paste by reflow heating,
Solder materials having different melting points, supporting both sides of the electronic component by a solder material having a melting point higher than the solder in the solder paste supplied to the member and a height higher than the thickness of the solder paste, In this state, the reflow heating is performed , the solder in the solder paste is melted, and then the solder material on the low melting point side of the solder material supporting both sides of the electronic component is melted. An electronic component soldering method , wherein the solder material on the melting point side is melted . 前記リフロー加熱はリフロー炉にて行い、前記電子部品の両側を支えた前記融点が互いに異なる前記半田材のうち低融点側の前記半田材の方が先に前記リフロー炉内に侵入することを特徴とする請求項１記載の電子部品の半田付け方法。The reflow heating is performed in a reflow furnace, and among the solder materials having different melting points that support both sides of the electronic component, the solder material on the low melting point side first enters the reflow furnace. The method of soldering an electronic component according to claim 1. 前記電子部品の両側を支えた前記融点が互いに異なる前記半田材の融点温度の差は、１０〜３０℃であることを特徴とする請求項１または２記載の電子部品の半田付け方法。The method of soldering an electronic component according to claim 1 or 2, wherein a difference in melting point temperature of the solder materials having different melting points supporting both sides of the electronic component is 10 to 30 ° C.
JP23725498A 1998-08-24 1998-08-24 Electronic component soldering method Expired - Fee Related JP3965795B2 (en)

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US20150069599A1 (en) * 2013-05-14 2015-03-12 Semikron Elektronik Gmbh & Co., Kg Power electronic switching device and assembly

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JP2006303173A (en) 2005-04-20 2006-11-02 Mitsubishi Electric Corp Circuit board device and manufacturing method therefor
ES2366922T3 (en) * 2005-11-25 2011-10-26 Israel Aerospace Industries Ltd. SYSTEM AND PROCEDURE TO PRODUCE A SET OF SOLAR CELLS.
CN104025727B (en) * 2011-09-26 2017-08-29 阿尔发装配解决方案有限公司 System and method for solder joint void reduction
JP5955370B2 (en) * 2014-10-29 2016-07-20 株式会社神戸製鋼所 Method for producing metal joined body

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150069599A1 (en) * 2013-05-14 2015-03-12 Semikron Elektronik Gmbh & Co., Kg Power electronic switching device and assembly
US9530712B2 (en) * 2013-05-14 2016-12-27 Semikron Elektronik Gmbh & Co., Kg Power electronic switching device and assembly

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