JP2007142146A - Electronic circuit board and mounting method - Google Patents

Electronic circuit board and mounting method Download PDF

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Publication number
JP2007142146A
JP2007142146A JP2005333887A JP2005333887A JP2007142146A JP 2007142146 A JP2007142146 A JP 2007142146A JP 2005333887 A JP2005333887 A JP 2005333887A JP 2005333887 A JP2005333887 A JP 2005333887A JP 2007142146 A JP2007142146 A JP 2007142146A
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Japan
Prior art keywords
printed wiring
wiring board
board
wiring layer
electronic circuit
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JP2005333887A
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Japanese (ja)
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JP4802679B2 (en
Inventor
Hisahiko Yoshida
久彦 吉田
Masahiko Hirata
昌彦 平田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in the case of the mounting of a semiconductor module, since reflow heatings are performed by the twice processes of the mounting on its printed wiring sub-board and the mounting on its printed wiring main board, thermal damage of its semiconductor package has been so increased conventionally that the reliability of its components has been lost. <P>SOLUTION: By having the mounting of the semiconductor module, soldering of each passive component 11 on a printed wiring sub-board 1 is performed by solders printed on a printed wiring main board 8 via pierced-through-hole wiring portions 4. Consequently, soldering on the printed wiring sub-board 1 and soldering on the main printed wiring board 8 can be performed collectively. Therefore, the number of reflow heatings can be decreased. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電子機器において用いられているプリント配線板に電子部品を実装する電子回路基板および実装方法に係り、特に半導体素子を含む複数の電子部品を実装した半導体モジュール基板および実装方法に関するものである。   The present invention relates to an electronic circuit board and a mounting method for mounting electronic components on a printed wiring board used in electronic equipment, and more particularly to a semiconductor module substrate and a mounting method for mounting a plurality of electronic components including semiconductor elements. is there.

携帯型電子機器などに搭載される回路基板は小型かつ高機能化が進み、電子部品を高密度に実装する技術に対するニーズが高い。なかでもプリント配線板との接続端子が多い制御用半導体素子と、これに比べて接続端子が少なく汎用的なメモリ用半導体素子および複数の受動部品を組み合わせて所定の機能を実現する回路モジュールをブロックとした実装が求められている。   Circuit boards mounted on portable electronic devices and the like are becoming smaller and more functional, and there is a great need for technology for mounting electronic components at high density. In particular, block control circuit elements that have a large number of connection terminals to the printed wiring board, circuit modules that have a small number of connection terminals and a general-purpose memory semiconductor element and multiple passive components to achieve a specific function. Implementation is required.

このとき、接続端子の多い制御用半導体素子を接続端子とプリント配線板を対向させて接続するフリップチップ実装を用いて狭ピッチ実装し、汎用的な樹脂封止によるパッケージ形態ではんだボールによる接続端子を形成したメモリ用半導体素子を３次元的に実装することで小型化を実現することができる。   At this time, the control semiconductor element with many connection terminals is mounted at a narrow pitch using flip chip mounting in which the connection terminals and the printed wiring board are connected to face each other, and the connection terminals by solder balls in a general resin-sealed package form Miniaturization can be realized by three-dimensionally mounting the semiconductor element for memory formed with.

フリップチップ実装のような狭ピッチ実装をする場合、プリント配線板に高精度な配線パターンが必要であることから、このプリント配線板の製造コストは高くなってしまう。プリント配線板の製造コストは基板面積に依存するため、メインプリント配線板とは別に比較的小さなサブプリント配線板を設け、このサブプリント配線板に制御用半導体素子、メモリ用半導体素子および複数の受動部品を実装して回路モジュールとしたものをメインプリント配線板に実装する構造をとることが一般的である。   When a narrow pitch mounting such as flip chip mounting is performed, a high-accuracy wiring pattern is required for the printed wiring board, and the manufacturing cost of the printed wiring board is increased. Since the manufacturing cost of a printed wiring board depends on the board area, a relatively small sub printed wiring board is provided separately from the main printed wiring board, and a control semiconductor element, a memory semiconductor element, and a plurality of passive circuits are provided on the sub printed wiring board. Generally, a circuit module is formed by mounting components on a main printed wiring board.

このような構造を実現する方法として、例えば特許文献１に記載されているようにサブプリント配線板上に電子部品をはんだ付けした後、メインプリント配線板に回路モジュールをはんだ付けするといった技術がある。   As a method for realizing such a structure, for example, as described in Patent Document 1, after electronic components are soldered on a sub-printed wiring board, a circuit module is soldered on the main printed wiring board. .

図３は、従来の電子回路基板の断面図を示している。図３（ａ）に示すように、サブプリント配線板１０１の上面および下面には、表面に銅箔による回路パターンを形成した配線層１０２および配線層１０３がそれぞれ設けられている。半導体素子１０４はフリップチップ実装方法で熱硬化性樹脂１０５の加熱加圧によりサブプリント配線板１０１に固定されると共に、半導体素子１０４の接続端子がサブプリント配線板１０４の配線層１０２に対して電気的に接続される。   FIG. 3 shows a cross-sectional view of a conventional electronic circuit board. As shown in FIG. 3A, the upper and lower surfaces of the sub-printed wiring board 101 are provided with a wiring layer 102 and a wiring layer 103, respectively, on which a circuit pattern made of copper foil is formed. The semiconductor element 104 is fixed to the sub printed wiring board 101 by heating and pressurizing the thermosetting resin 105 by a flip chip mounting method, and the connection terminals of the semiconductor element 104 are electrically connected to the wiring layer 102 of the sub printed wiring board 104. Connected.

次に図３（ｂ）に示すように、配線層１０２上にはんだペーストがマスク印刷により供給され、セラミックコンデンサなどの受動部品１０６と、接続端子に予めはんだボール１１１が形成された半導体パッケージ１０７が配置されて、リフロー炉にてサブプリント配線板１０１の１回目の加熱を行い、はんだ付けが行われる。   Next, as shown in FIG. 3B, a solder paste is supplied onto the wiring layer 102 by mask printing, and a passive component 106 such as a ceramic capacitor and a semiconductor package 107 in which solder balls 111 are previously formed on connection terminals are formed. Then, the sub-printed wiring board 101 is heated for the first time in the reflow furnace, and soldering is performed.

次に図３（ｃ）に示すように、メインプリント配線板１０８に形成された配線層１０９の上にはんだペースト１１２がマスク印刷により供給され、他の電子部品１１０を配置すると共に、メインプリント配線板１０８の配線層１０９と面が対向するようにサブプリント配線板１０１の配線層１０３が配置された後に、サブプリント配線板１０１とメインプリント配線板１０８および他の電子部品をまとめてリフロー炉にて２回目の加熱を行い、はんだ付けが行われ電子回路基板が実装される。
特開２００３−６９１８１号公報（第３図） Next, as shown in FIG. 3C, the solder paste 112 is supplied by mask printing on the wiring layer 109 formed on the main printed wiring board 108, and another electronic component 110 is arranged, and the main printed wiring After the wiring layer 103 of the sub-printed wiring board 101 is arranged so that the surface of the wiring layer 109 of the board 108 faces, the sub-printed wiring board 101, the main printed wiring board 108, and other electronic components are put together in a reflow furnace. The second heating is performed, soldering is performed, and the electronic circuit board is mounted.
Japanese Patent Laying-Open No. 2003-69181 (FIG. 3)

しかしながら、上述のような従来の技術では、サブプリント配線板への実装とメインプリント配線板への実装のときに鉛フリーはんだを用いてはんだ付けする場合、２２０℃〜２６０℃の温度でリフロー加熱する工程を２回設ける必要がある。このため電子回路基板上の半導体素子や半導体パッケージに加わる実装時のダメージが増加し、部品の信頼性が損なわれるといった問題点があった。   However, in the conventional technology as described above, when soldering using lead-free solder at the time of mounting on the sub printed wiring board and mounting on the main printed wiring board, reflow heating is performed at a temperature of 220 ° C. to 260 ° C. It is necessary to provide the process to do twice. For this reason, there has been a problem that damage at the time of mounting applied to the semiconductor element or the semiconductor package on the electronic circuit board is increased, and the reliability of the component is impaired.

上記問題点を解決するために、本発明は、上面および下面に設けられた配線層と、貫通スルーホール配線部とを有する第１のプリント配線板と、上面に設けられた前記配線層を介して樹脂固定により前記第１のプリント配線板に実装された半導体素子と、前記貫通スルーホール配線部を介してはんだ付けにより前記第１のプリント配線板に実装された受動部品と、上面に設けられた配線層を有する第２のプリント配線板とからなる電子回路基板であって、前記第１のプリント配線板に実装された前記受動部品は、前記貫通スルーホール配線部を介して前記第２のプリント配線板の前記配線層とはんだ付けされており、互いに対向する前記第１のプリント配線板の下面の前記配線層と、前記第２のプリント配線板の前記配線層がはんだ付けされていることを特徴とするものである。   In order to solve the above problems, the present invention provides a first printed wiring board having a wiring layer provided on the upper surface and the lower surface and a through-hole wiring portion, and the wiring layer provided on the upper surface. A semiconductor element mounted on the first printed wiring board by resin fixing, a passive component mounted on the first printed wiring board by soldering through the through-through-hole wiring portion, and provided on the upper surface. An electronic circuit board comprising a second printed wiring board having a wiring layer, wherein the passive component mounted on the first printed wiring board passes through the through-through-hole wiring portion. The wiring layer of the printed wiring board is soldered to the wiring layer on the lower surface of the first printed wiring board facing each other, and the wiring layer of the second printed wiring board is soldered. It is characterized in that there.

また、半導体パッケージがはんだボールにより前記第１のプリント配線板の上面の前記配線層にはんだ付けされていることを特徴とするものである。   Further, the semiconductor package is soldered to the wiring layer on the upper surface of the first printed wiring board by solder balls.

また、上面および下面に設けられた配線層と、貫通スルーホール配線部とを有する第１のプリント配線板と、上面に設けられた前記配線層を介して前記第１のプリント配線板に実装された半導体素子と、上面に設けられた配線層を有する第２のプリント配線板と、前記貫通スルーホール配線部を介して前記第２のプリント配線板の前記配線層とはんだ付けされ、かつ前記第１のプリント配線板に実装された受動部品とからなる電子回路基板の実装方法であって、前記第１のプリント配線板に樹脂固定により前記半導体素子を実装する第１の工程と、前記半導体素子が実装された前記第１のプリント配線板を前記第２のプリント配線板上に配置すると共に、前記受動部品を前記第１のプリント配線板上に配置する第２の工程と、前記貫通スルーホール配線部を介して前記受動部品を前記第２のプリント配線板の前記配線層とはんだ付けすると同時に、互いに対向する前記第１のプリント配線板の下面の前記配線層と第２のプリント配線板の前記配線層をはんだ付けする第３の工程からなることを特徴とするものである。   Further, the first printed wiring board having a wiring layer provided on the upper surface and the lower surface and a through-hole wiring portion and the first printed wiring board mounted on the first printed wiring board via the wiring layer provided on the upper surface. A semiconductor element, a second printed wiring board having a wiring layer provided on the upper surface, soldered to the wiring layer of the second printed wiring board via the through-hole wiring portion, and the second printed wiring board An electronic circuit board mounting method comprising a passive component mounted on one printed wiring board, the first step of mounting the semiconductor element on the first printed wiring board by resin fixation, and the semiconductor element The first printed wiring board on which is mounted is disposed on the second printed wiring board, and the passive component is disposed on the first printed wiring board; and the through-through The passive component is soldered to the wiring layer of the second printed wiring board via a loop wiring portion, and at the same time, the wiring layer and the second printed wiring on the lower surface of the first printed wiring board facing each other It consists of the 3rd process of soldering the said wiring layer of a board, It is characterized by the above-mentioned.

また、前記スルーホール配線部に液状フラックスを塗布した後、前記受動部品が配置されることを特徴とするものである。   Further, the passive component is disposed after applying a liquid flux to the through-hole wiring portion.

さらに、前記第２の工程において、半導体パッケージをはんだボールにより第１のプリント配線板上に配置する工程と、前記第３の工程において、前記半導体パッケージを前記はんだボールにより前記第１のプリント配線板上にはんだ付けする工程をさらに有することを特徴とするものである。   Further, in the second step, the semiconductor package is disposed on the first printed wiring board by a solder ball, and in the third step, the semiconductor package is disposed by the solder ball in the first printed wiring board. It further has the process of soldering on.

本発明によれば、電子回路基板へ半導体素子を実装するときのリフロー加熱の回数を減らすことができるので、熱ダメージによって部品信頼性を損なうことなく、信頼性の高い電子回路基板を提供することができるものである。また本発明による電子回路基板では、リフローの加熱回数を減らし、加熱工程数の少ない簡略化した製造工程で製作することが可能となる。   According to the present invention, it is possible to reduce the number of times of reflow heating when mounting a semiconductor element on an electronic circuit board. Therefore, it is possible to provide a highly reliable electronic circuit board without impairing component reliability due to thermal damage. It is something that can be done. Further, the electronic circuit board according to the present invention can be manufactured by a simplified manufacturing process in which the number of reflow heating steps is reduced and the number of heating steps is small.

以下、本発明の実施の形態について、図を用いて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（実施の形態１）
図１は本発明の実施の形態１における電子回路基板の断面図である。図２は実施の形態１におけるサブプリント配線板と受動部品の実装部分の拡大断面図である。 (Embodiment 1)
FIG. 1 is a cross-sectional view of an electronic circuit board according to Embodiment 1 of the present invention. FIG. 2 is an enlarged cross-sectional view of the mounting portion of the sub-printed wiring board and the passive component in the first embodiment.

図１（ａ）に示すように第１のプリント配線板であるサブプリント配線板１の上面および下面には表面に銅箔による回路パターンを形成した配線層２および配線層３を設ける。さらに、サブプリント配線板１には上面から下面にかけて貫通した穴によって形成された貫通スルーホール配線部４が設けられている。   As shown in FIG. 1A, a wiring layer 2 and a wiring layer 3 having a circuit pattern made of copper foil are provided on the upper and lower surfaces of a sub-printed wiring board 1 as a first printed wiring board. Further, the sub printed wiring board 1 is provided with a through through-hole wiring portion 4 formed by a hole penetrating from the upper surface to the lower surface.

半導体素子５はフリップチップ実装方法で熱硬化性樹脂６の加熱加圧によりサブプリント配線板１に固定されると共に、半導体素子５の接続端子がサブプリント配線板１の配線層２に対して電気的に接続される。さらに活性作用を有する液状フラックス７を配線層２の表面に噴霧する。   The semiconductor element 5 is fixed to the sub printed wiring board 1 by heating and pressurizing the thermosetting resin 6 by a flip chip mounting method, and the connection terminal of the semiconductor element 5 is electrically connected to the wiring layer 2 of the sub printed wiring board 1. Connected. Further, a liquid flux 7 having an active action is sprayed on the surface of the wiring layer 2.

次に図１（ｂ）に示すように第２のプリント配線板であるメインプリント配線板８の上面に形成された配線層９にマスク印刷によりはんだペースト１３が供給され、他の電子部品１０が配置される。サブプリント配線板１は、下面の配線層３がメインプリント配線板８の上面の配線層９に対向するようにはんだペースト１３を介して配置される。次にセラミックコンデンサなどの受動部品１１がサブプリント配線板１の上に配置される。   Next, as shown in FIG. 1B, the solder paste 13 is supplied to the wiring layer 9 formed on the upper surface of the main printed wiring board 8 as the second printed wiring board by mask printing, and the other electronic components 10 are Be placed. The sub-printed wiring board 1 is disposed via the solder paste 13 so that the lower wiring layer 3 faces the upper wiring layer 9 of the main printed wiring board 8. Next, a passive component 11 such as a ceramic capacitor is disposed on the sub-printed wiring board 1.

図２（ａ）に示すように受動部品１１の端子１１ａ、１１ｂは貫通スルーホール配線部４を形成する４ａ、４ｂの上に合わせて配置され、液状フラックス７の粘着力によって位置固定されている。貫通スルーホール配線部４を形成する４ａ、４ｂの内径は、溶融したはんだペースト１３の毛細管現象が発生しやすい内径として形成している。   As shown in FIG. 2A, the terminals 11 a and 11 b of the passive component 11 are arranged on the 4 a and 4 b forming the through-hole wiring portion 4 and are fixed in position by the adhesive force of the liquid flux 7. . The inner diameters of 4a and 4b forming the through-hole wiring portion 4 are formed as inner diameters in which the capillary phenomenon of the molten solder paste 13 is likely to occur.

さらに図１（ｂ）に示すように接続端子に予めはんだボール１４が形成された半導体パッケージ１２がサブプリント配線板１上に配置された後、サブプリント配線板１、メインプリント配線板８およびこれらに配置した全ての電子部品と共にまとめて１回だけリフロー炉にて加熱することにより、すべての箇所のはんだ付けを一度に行うものである。   Further, as shown in FIG. 1B, after the semiconductor package 12 in which the solder balls 14 are formed in advance on the connection terminals is arranged on the sub printed wiring board 1, the sub printed wiring board 1, the main printed wiring board 8, and these All the electronic components arranged in the above are collectively heated once in a reflow furnace, so that all the parts are soldered at once.

このとき図２（ｂ）に示すように、はんだペースト１３は溶融して流動性を持ちながら貫通スルーホール配線部４を形成する４ａ、４ｂの内部へ毛細管現象により吸い上がっていき、はんだペースト１３ａとなって液状フラックス７で表面活性化された受動部品１１の端子１１ａ、１１ｂおよびメインプリント配線板８の上面の配線層９にはんだ付けされ固定される。   At this time, as shown in FIG. 2B, the solder paste 13 melts and has fluidity, and is sucked up into capillaries 4a and 4b forming the through-hole wiring portions 4 by a capillary phenomenon. Thus, the terminals 11 a and 11 b of the passive component 11 whose surface is activated by the liquid flux 7 and the wiring layer 9 on the upper surface of the main printed wiring board 8 are soldered and fixed.

また、サブプリント配線板１の下面の配線層３と、互いに対向するメインプリント配線板８の上面の配線層９が、はんだペースト１３によりはんだ付けされる。さらに、半導体パッケージ１２は端子のはんだボール１４が溶融してサブプリント配線板１の上面の配線層２にはんだ付けされ固定される。他の電子部品１０もはんだペースト１３が溶融して、メインプリント配線板８の上面の配線層９にはんだ付けされ固定される。   Further, the wiring layer 3 on the lower surface of the sub-printed wiring board 1 and the wiring layer 9 on the upper surface of the main printed wiring board 8 facing each other are soldered with a solder paste 13. Furthermore, the solder balls 14 of the terminals are melted in the semiconductor package 12 and are soldered and fixed to the wiring layer 2 on the upper surface of the sub-printed wiring board 1. The other electronic component 10 is also soldered and fixed to the wiring layer 9 on the upper surface of the main printed wiring board 8 by melting the solder paste 13.

以上のような構成で、電子回路基板を一括で実装することでリフロー加熱工程の回数を少なくし、半導体素子や半導体パッケージなどの電子部品の熱ダメージを少なくすると共に製造工程を簡略化できる。   With the configuration as described above, the electronic circuit boards are collectively mounted, thereby reducing the number of reflow heating steps, reducing the thermal damage of electronic components such as semiconductor elements and semiconductor packages, and simplifying the manufacturing process.

本発明の電子回路基板および実装方法は、半導体素子や半導体パッケージなどの電子部品の熱ダメージを少なくして信頼性品質を高めるとともに実装工程を簡略化することが可能であるといったことから高密度電子回路基板の実装用途に有用である。   Since the electronic circuit board and the mounting method of the present invention can reduce the thermal damage of electronic components such as semiconductor elements and semiconductor packages to improve the reliability quality and simplify the mounting process, Useful for circuit board mounting applications.

本発明の実施の形態１における電子回路基板の断面図Sectional drawing of the electronic circuit board in Embodiment 1 of this invention 本発明の実施の形態１におけるサブプリント配線板と受動部品の実装部分の拡大断面図The expanded sectional view of the mounting part of the sub printed wiring board and passive component in Embodiment 1 of this invention 従来の電子回路基板の断面図Sectional view of a conventional electronic circuit board

符号の説明Explanation of symbols

１ サブプリント配線板
２、３、９ 配線層
４ 貫通スルーホール配線部
５ 半導体素子
６ 熱硬化性樹脂
７ 液状フラックス
８ メインプリント配線板
１１ 受動部品
１２ 半導体パッケージ
１３ はんだペースト
１４ はんだボール
DESCRIPTION OF SYMBOLS 1 Sub printed wiring board 2, 3, 9 Wiring layer 4 Through-through-hole wiring part 5 Semiconductor element 6 Thermosetting resin 7 Liquid flux 8 Main printed wiring board 11 Passive component 12 Semiconductor package 13 Solder paste 14 Solder ball

Claims (5)

上面および下面に設けられた配線層と、貫通スルーホール配線部とを有する第１のプリント配線板と、上面に設けられた前記配線層を介して樹脂固定により前記第１のプリント配線板に実装された半導体素子と、前記貫通スルーホール配線部を介してはんだ付けにより前記第１のプリント配線板に実装された受動部品と、上面に設けられた配線層を有する第２のプリント配線板とからなる電子回路基板であって、前記第１のプリント配線板に実装された前記受動部品は、前記貫通スルーホール配線部を介して前記第２のプリント配線板の前記配線層とはんだ付けされており、互いに対向する前記第１のプリント配線板の下面の前記配線層と、前記第２のプリント配線板の前記配線層がはんだ付けされていることを特徴とする電子回路基板。 Mounted on the first printed wiring board by resin fixing via the wiring layer provided on the upper surface and the lower surface, the first printed wiring board having a through-hole wiring portion, and the wiring layer provided on the upper surface And a passive component mounted on the first printed wiring board by soldering via the through-through-hole wiring portion, and a second printed wiring board having a wiring layer provided on the upper surface. The passive component mounted on the first printed wiring board is soldered to the wiring layer of the second printed wiring board via the through-hole wiring portion. An electronic circuit board, wherein the wiring layer on the lower surface of the first printed wiring board facing each other is soldered to the wiring layer of the second printed wiring board. 半導体パッケージがはんだボールにより前記第１のプリント配線板の上面の前記配線層にはんだ付けされていることを特徴とする請求項１に記載の電子回路基板。 2. The electronic circuit board according to claim 1, wherein a semiconductor package is soldered to the wiring layer on the upper surface of the first printed wiring board by solder balls. 上面および下面に設けられた配線層と、貫通スルーホール配線部とを有する第１のプリント配線板と、上面に設けられた前記配線層を介して前記第１のプリント配線板に実装された半導体素子と、上面に設けられた配線層を有する第２のプリント配線板と、前記貫通スルーホール配線部を介して前記第２のプリント配線板の前記配線層とはんだ付けされ、かつ前記第１のプリント配線板に実装された受動部品とからなる電子回路基板の実装方法であって、前記第１のプリント配線板に樹脂固定により前記半導体素子を実装する第１の工程と、前記半導体素子が実装された前記第１のプリント配線板を前記第２のプリント配線板上に配置すると共に、前記受動部品を前記第１のプリント配線板上に配置する第２の工程と、前記貫通スルーホール配線部を介して前記受動部品を前記第２のプリント配線板の前記配線層とはんだ付けすると同時に、互いに対向する前記第１のプリント配線板の下面の前記配線層と第２のプリント配線板の前記配線層をはんだ付けする第３の工程からなることを特徴とする電子回路基板の実装方法。 A first printed wiring board having a wiring layer provided on the upper surface and the lower surface, and a through-hole wiring portion, and a semiconductor mounted on the first printed wiring board via the wiring layer provided on the upper surface An element, a second printed wiring board having a wiring layer provided on the upper surface, and soldered to the wiring layer of the second printed wiring board via the through-hole wiring portion; and An electronic circuit board mounting method comprising a passive component mounted on a printed wiring board, wherein the semiconductor element is mounted on the first printed wiring board by resin fixing, and the semiconductor element is mounted. A second step of disposing the first printed wiring board formed on the second printed wiring board and disposing the passive component on the first printed wiring board; and the through-through hole. The passive component is soldered to the wiring layer of the second printed wiring board via the wire portion, and at the same time, the wiring layer on the lower surface of the first printed wiring board facing each other and the second printed wiring board An electronic circuit board mounting method comprising a third step of soldering the wiring layer. 前記スルーホール配線部に液状フラックスを塗布した後、前記受動部品が配置されることを特徴とする請求項３に記載の電子回路基板の実装方法。 4. The electronic circuit board mounting method according to claim 3, wherein the passive component is disposed after applying a liquid flux to the through-hole wiring portion. 前記第２の工程において、半導体パッケージをはんだボールにより第１のプリント配線板上に配置する工程と、前記第３の工程において、前記半導体パッケージを前記はんだボールにより前記第１のプリント配線板上にはんだ付けする工程をさらに有することを特徴とする請求項３または４に記載の電子回路基板の実装方法。 In the second step, the semiconductor package is disposed on the first printed wiring board by solder balls, and in the third step, the semiconductor package is disposed on the first printed wiring board by the solder balls. 5. The electronic circuit board mounting method according to claim 3, further comprising a soldering step.
JP2005333887A 2005-11-18 2005-11-18 Electronic circuit board mounting method Expired - Fee Related JP4802679B2 (en)

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JP2007221133A (en) * 2006-02-14 2007-08-30 Integrant Technologies Inc Integrated circuit package

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JPS6167292A (en) * 1984-09-10 1986-04-07 株式会社日立製作所 Method and device for mounting surface attached part
JPH0184463U (en) * 1987-11-27 1989-06-05
JPH1012990A (en) * 1996-04-26 1998-01-16 Ngk Spark Plug Co Ltd Interconnecting board and production thereof, structure comprising board, interconnecting board and fixing board, and connector between board and interconnecting board
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JP2003108963A (en) * 2001-09-28 2003-04-11 Matsushita Electric Ind Co Ltd Card type recording medium and its manufacturing method
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JP2007221133A (en) * 2006-02-14 2007-08-30 Integrant Technologies Inc Integrated circuit package

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