JP2007258654A - Circuit board land connection method and the circuit board - Google Patents

Circuit board land connection method and the circuit board Download PDF

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JP2007258654A
JP2007258654A JP2006114995A JP2006114995A JP2007258654A JP 2007258654 A JP2007258654 A JP 2007258654A JP 2006114995 A JP2006114995 A JP 2006114995A JP 2006114995 A JP2006114995 A JP 2006114995A JP 2007258654 A JP2007258654 A JP 2007258654A
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circuit board
short
lands
pair
land
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Minoru Yuasa
穂 湯浅
Masaya Shimamura
雅哉 島村
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board land connection method for readily making short-circuiting when land is unnecessary land and avoiding short-circuit in mounting an electronic component. <P>SOLUTION: This method bores a hole 3 between the paired lands 2, in such a way that a conductor 4 for short-circuit is exposed via the hole 3 from within a circuit board 1. When the land is not required, it fills a solder paste in the hole 3 and then fuses it there to short-circuit the lands 2. When an electronic component is to be mounted, it uses the hole 3 to prevent a capillary phenomenon to avoid unnecessary short-circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子機器に用いられる回路基板において、回路設計上不要になったランドを短絡させる方法及びそれを簡易に実施できる構造を有する回路基板に関するものである。  The present invention relates to a method of short-circuiting a land that is no longer necessary for circuit design in a circuit board used in an electronic apparatus, and a circuit board having a structure that can be easily implemented.

電子機器に用いられる回路基板は、セラミックまたは樹脂等の絶縁基板に配線導体及びランドと呼ばれる電子部品の端子電極を電気的に接続する部分が形成されている。ランドの部分では、一対のランド導体が所定の間隔を介して向かい合っており、このランド導体に電子部品の端子電極が接続されることで回路が接続される。ランドは通常設計上必要な電子部品の分が形成されているが、要求される特性等によって設計が変更されて、必要な部品数が削減されることがあり、不要になるランドが発生することがあった。このように不要になったランドはジャンパチップ等によって短絡され、通常の配線と同様にされる。  A circuit board used in an electronic device has a portion for electrically connecting a wiring conductor and a terminal electrode of an electronic component called a land to an insulating substrate such as ceramic or resin. In the land portion, a pair of land conductors face each other with a predetermined interval, and a circuit is connected by connecting terminal electrodes of electronic components to the land conductors. The lands are usually made up of electronic parts that are necessary for design, but the design may be changed depending on the required characteristics, etc., and the number of necessary parts may be reduced, resulting in unnecessary lands. was there. The land that has become unnecessary in this manner is short-circuited by a jumper chip or the like, and is made the same as normal wiring.

しかしながら、ジャンパチップを搭載するために、マウンターを動作させるため、その分のマウンターのセッティングや搭載の工数がかかる。そのため、ジャンパチップを用いないで不要になったランドを短絡させる方法が提案されている。これらの方法では、ランド導体間の間隔を狭くして、半田ブリッジによって短絡させる方法が採られている。  However, since the mounter is operated in order to mount the jumper chip, it takes time to set and mount the mounter. Therefore, a method for short-circuiting a land that has become unnecessary without using a jumper chip has been proposed. In these methods, the distance between the land conductors is narrowed and short-circuited by a solder bridge.

特開2000−223826号公報JP 2000-223826 A 特開平6−232537号公報JP-A-6-232537

従来の方法に用いられるランドでは、不要でない場合、すなわち電子部品を搭載する場合にも図8に示すように、半田ブリッジが発生して、短絡を起こしてしまう問題があった。特に近年の電子部品の小型化によって、電子部品と基板との隙間がより狭くなり、これに起因する毛細管現象により半田がこの隙間を通って半田ブリッジが形成されて、不要な短絡が発生しやすくなるという問題があった。  The land used in the conventional method has a problem that a solder bridge is generated and a short circuit occurs as shown in FIG. 8 even when it is not necessary, that is, when an electronic component is mounted. In particular, due to the recent miniaturization of electronic components, the gap between the electronic component and the substrate has become narrower, and due to the capillary phenomenon resulting from this, a solder bridge is formed through this gap, and unnecessary short circuits are likely to occur. There was a problem of becoming.

本発明は、このような問題点を解決し、不要な場合は容易に短絡させることができ、電子部品を搭載する場合は短絡が発生しない回路基板のランド接続方法及びそれを簡易に実施できる構造を有する回路基板を提案するものである。  The present invention solves such problems, and can easily be short-circuited when unnecessary, and a circuit board land connection method that does not cause short-circuiting when an electronic component is mounted, and a structure that can be easily implemented. The circuit board which has this is proposed.

本発明は、電子部品の端子電極と電気的に接続される一対のランドを有する回路基板のランド接続方法であって、前記一対のランドの間に短絡用導体を配置し、前記短絡用導体と前記一対のランドを接続することによって短絡させることを特徴とする回路基板のランド接続方法を提案する。  The present invention is a land connection method for a circuit board having a pair of lands electrically connected to terminal electrodes of an electronic component, wherein a short-circuiting conductor is disposed between the pair of lands, A circuit board land connection method is proposed in which the pair of lands are short-circuited by connection.

また、本発明では、前記短絡用導体は、前記一対のランドとは異なる面上に配置され、前記一対のランドの間に穴を設け、前記穴に半田を充填して溶融することによって前記短絡用導体と前記一対のランドを短絡させることを特徴とする回路基板のランド接続方法を提案する。  Further, in the present invention, the short-circuiting conductor is disposed on a surface different from the pair of lands, a hole is provided between the pair of lands, and the hole is filled with solder to melt the short-circuit. A land connection method for a circuit board is proposed in which the conductor for use and the pair of lands are short-circuited.

さらに、本発明では、電子部品の端子電極と電気的に接続される一対のランドを有する回路基板であって、前記一対のランドの間に短絡用導体が配置され、前記短絡用導体は前記一対のランドとは異なる面上に配置され、前記一対のランドの間に、半田を充填して溶融することによって前記一対のランドと前記短絡用導体を短絡させるための穴が設けられていることを特徴とする回路基板を提案する。  Furthermore, in the present invention, a circuit board having a pair of lands electrically connected to terminal electrodes of an electronic component, wherein a shorting conductor is disposed between the pair of lands, and the shorting conductor is the pair of lands. A hole for short-circuiting the pair of lands and the short-circuiting conductor by being filled with solder and melted between the pair of lands. A feature circuit board is proposed.

さらに、本発明では、前記短絡用導体が前記一対のランドが形成されている面と反対側の面に形成されていることを特徴とする回路基板を提案する。  Furthermore, the present invention proposes a circuit board characterized in that the short-circuiting conductor is formed on a surface opposite to the surface on which the pair of lands are formed.

さらに、本発明では、前記短絡用導体が回路基板の内部に内蔵されていることを特徴とする回路基板を提案する。  Furthermore, the present invention proposes a circuit board in which the short-circuiting conductor is built in the circuit board.

本発明によれば、ランドが不要な場合は簡便な方法で容易に短絡させることができ、電子部品を搭載する場合は半田ブリッジによる短絡が発生しないようにすることができる。  According to the present invention, when a land is unnecessary, it can be easily short-circuited by a simple method, and when an electronic component is mounted, a short-circuit due to a solder bridge can be prevented from occurring.

本発明に係る回路基板のランド接続方法の第一の実施形態を、図面に基づいて説明する。図1は本発明のランド接続方法に用いられる回路基板を示す図で、図1(a)は側断面図、図1(b)は上から見た平面図である。回路基板1は、一対のランド2とこのランド2の間に形成された穴3と、回路基板1に内蔵されかつ穴3を通じて露出している短絡用導体4を有している多層回路基板である。なお、ランド2に接続する配線等は省略してある。  A first embodiment of a circuit board land connection method according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a circuit board used in the land connection method of the present invention. FIG. 1 (a) is a side sectional view and FIG. 1 (b) is a plan view seen from above. The circuit board 1 is a multilayer circuit board having a pair of lands 2, a hole 3 formed between the lands 2, and a short-circuit conductor 4 that is built in the circuit board 1 and exposed through the hole 3. is there. Incidentally, wirings connected to the land 2 are omitted.

この回路基板1のランド2を短絡する方法を図2に示す。メタルマスク印刷等により穴3に半田ペースト5を充填し且つランド2及び短絡用導体4に半田ペースト5を付着させる。これをリフロー炉に通して半田ペースト5を溶融させる。このようにすると、ランド2と短絡用導体4が半田によって導通し、ランド2は短絡する。  A method for short-circuiting the lands 2 of the circuit board 1 is shown in FIG. The hole 3 is filled with the solder paste 5 by metal mask printing or the like, and the solder paste 5 is adhered to the land 2 and the shorting conductor 4. This is passed through a reflow furnace to melt the solder paste 5. In this way, the land 2 and the short-circuiting conductor 4 are electrically connected by solder, and the land 2 is short-circuited.

一方、短絡させずに電子部品を搭載する場合を図3に示す。まず、図3(a)のように、半田ペースト5をランド2上にメタルマスク印刷等によって塗布する。続いて図3(b)のように電子部品6を搭載し、これをリフロー炉に通して半田ペースト5を溶融させる。このような本発明のランド接続方法では、一対のランド2の間隔を大きく取れるとともに、毛細管現象によって溶融半田が電子部品と基板との隙間に流れ込むのを穴3が阻止するため、電子部品を搭載するときに不要な短絡を防止することができる。なお、穴の形状については特に制限はないが、半田が電子部品と基板との隙間に流れ込むのを阻止する効果を充分に発揮させるために、図1(b)に示すように穴の長さL(ランド2の幅方向と平行な方向の長さ)をランド2の幅寸法よりも長くすることが好ましい。また、穴の長さLをメタルマスクのパターン寸法よりも長くすることにより、空気の逃げ場を確保できるため、穴に半田を充分に充填できる。  On the other hand, FIG. 3 shows a case where electronic components are mounted without being short-circuited. First, as shown in FIG. 3A, the solder paste 5 is applied onto the land 2 by metal mask printing or the like. Subsequently, as shown in FIG. 3B, the electronic component 6 is mounted, and this is passed through a reflow furnace to melt the solder paste 5. In such a land connection method of the present invention, the gap between the pair of lands 2 can be increased, and the hole 3 prevents the molten solder from flowing into the gap between the electronic component and the substrate due to the capillary phenomenon. This can prevent unnecessary short circuits. The shape of the hole is not particularly limited, but in order to sufficiently exhibit the effect of preventing the solder from flowing into the gap between the electronic component and the substrate, the length of the hole as shown in FIG. L (length in a direction parallel to the width direction of the land 2) is preferably longer than the width dimension of the land 2. Further, by making the length L of the hole longer than the pattern size of the metal mask, it is possible to secure an air escape space, so that the hole can be sufficiently filled with solder.

次に第一の実施形態の変形例を図4に示す。前述の実施形態と異なる点は、図4(a)に示すように、穴3が貫通穴であり、短絡用導体4がランド2を形成している面と反対側の面に形成されている点である。この回路基板1のランド2を短絡する方法を、図4(b)及び図4(c)に基づいて説明する。まず、図4(b)に示すように、半田ペースト5をランド2側から充填する。続いて図4(c)に示すように、短絡用導体4側から半田ぺースト5を充填する。これをリフロー炉に通して半田ペースト5を溶融させる。このようにすると、ランド2と短絡用導体4が導通し、ランド2は短絡する。一方、電子部品を搭載する場合は、前述の実施形態と同様に穴3によって不要な短絡を防止することができる。  Next, a modification of the first embodiment is shown in FIG. The difference from the above-described embodiment is that, as shown in FIG. 4A, the hole 3 is a through hole, and the shorting conductor 4 is formed on the surface opposite to the surface on which the land 2 is formed. Is a point. A method for short-circuiting the lands 2 of the circuit board 1 will be described with reference to FIGS. 4B and 4C. First, as shown in FIG. 4B, the solder paste 5 is filled from the land 2 side. Subsequently, as shown in FIG. 4C, the solder paste 5 is filled from the shorting conductor 4 side. This is passed through a reflow furnace to melt the solder paste 5. In this way, the land 2 and the short-circuiting conductor 4 are conducted, and the land 2 is short-circuited. On the other hand, when an electronic component is mounted, an unnecessary short circuit can be prevented by the hole 3 as in the above-described embodiment.

次に第一の実施形態の別の変形例を図5に示す。前述の実施形態と異なる点は、図5(a)に示すように、穴3が一つであり、短絡用導体4が穴3で2つに分割されており、ランド2と短絡用導体4がスルーホールを通じて接続されている点である。この回路基板1のランド2を短絡する方法を、図5(b)に基づいて説明する。まず、図5(b)に示すように、半田ペースト5を穴3に充填する。これをリフロー炉に通して半田ペースト5を溶融させる。このようにすると、分割された短絡用導体4が導通し、ランド2は短絡する。一方、電子部品を搭載する場合は、前述の実施形態と同様に穴3によって不要な短絡を防止することができる。なお、補助導体7は穴3に半田ペースト5を充填させるときの補助の役目を有しているが、特に必須のものではない。  Next, another modification of the first embodiment is shown in FIG. The difference from the above-described embodiment is that, as shown in FIG. 5 (a), there is one hole 3, the shorting conductor 4 is divided into two by the hole 3, and the land 2 and the shorting conductor 4 are divided. Are connected through through-holes. A method for short-circuiting the lands 2 of the circuit board 1 will be described with reference to FIG. First, as shown in FIG. 5 (b), the solder paste 5 is filled into the holes 3. This is passed through a reflow furnace to melt the solder paste 5. If it does in this way, the divided shorting conductor 4 is conducted, and the land 2 is short-circuited. On the other hand, when an electronic component is mounted, an unnecessary short circuit can be prevented by the hole 3 as in the above-described embodiment. The auxiliary conductor 7 has an auxiliary function when the hole 3 is filled with the solder paste 5, but is not particularly essential.

次に、本発明に係る回路基板のランド接続方法の第二の実施形態を、図6に示す。図6は、一対のランド2の間に、短絡用導体として導電性接合材8を付与することによってランド2を短絡する方法を示している。導電性接合材8に用いる材料としては、エポキシ樹脂等の熱硬化性樹脂に金属粒子を分散させた導電性樹脂や、他の電子部品の実装に用いられる半田よりも溶融温度の高い高温半田、あるいはSn−Ag系接合材、Sn−Ag−Cu系接合材、Sn−Cu系接合材およびSn−Zn系接合材のようにランドへの濡れ拡がりが殆ど無い接合材料もしくは一度目の加熱で合金層を形成し二度目の加熱では殆ど溶融や移動のない接合材料が挙げられる。この実施形態では、ジャンパチップを用いないで短絡させるので、マウンターを用いる必要がなく、メタルマスクを用いた印刷法のような簡易な方法で短絡させることができる。  Next, a second embodiment of the circuit board land connection method according to the present invention is shown in FIG. FIG. 6 shows a method of short-circuiting the lands 2 by applying a conductive bonding material 8 as a short-circuiting conductor between the pair of lands 2. Examples of the material used for the conductive bonding material 8 include a conductive resin in which metal particles are dispersed in a thermosetting resin such as an epoxy resin, a high-temperature solder having a melting temperature higher than that of a solder used for mounting other electronic components, Alternatively, a bonding material that hardly has wet spread to the land, such as a Sn-Ag bonding material, a Sn-Ag-Cu bonding material, a Sn-Cu bonding material, and a Sn-Zn bonding material, or an alloy by first heating. A bonding material that forms a layer and hardly melts or moves in the second heating is mentioned. In this embodiment, since the short circuit is performed without using the jumper chip, it is not necessary to use a mounter, and the short circuit can be performed by a simple method such as a printing method using a metal mask.

次に、本発明に係る回路基板のランド接続方法の第三の実施形態を、図7に示す。図7(a)は、ランド2と短絡用導体4が一体化、すなわち予めランド2を短絡させた状態にしたものを示している。電子部品を搭載する場合は、図7(b)に示すように、エッチングまたはレーザートリミング等で短絡用導体4を除去し、ギャップを形成する。このような方法では、必要なランドのみエッチングやトリミングで形成し、不要なランドは短絡したままにしておくことができる。  Next, a third embodiment of the circuit board land connection method according to the present invention is shown in FIG. FIG. 7A shows that the land 2 and the short-circuiting conductor 4 are integrated, that is, the land 2 is short-circuited in advance. When an electronic component is mounted, as shown in FIG. 7B, the short-circuit conductor 4 is removed by etching or laser trimming to form a gap. In such a method, only necessary lands can be formed by etching or trimming, and unnecessary lands can be kept short-circuited.

本発明の第一の実施形態を示す図である。It is a figure which shows 1st embodiment of this invention. 本発明の第一の実施形態を示す図である。It is a figure which shows 1st embodiment of this invention. 本発明の第一の実施形態を示す図である。It is a figure which shows 1st embodiment of this invention. 本発明の第一の実施形態の変形例を示す図である。It is a figure which shows the modification of 1st embodiment of this invention. 本発明の第一の実施形態の別の変形例を示す図である。It is a figure which shows another modification of 1st embodiment of this invention. 本発明の第二の実施形態を示す図である。It is a figure which shows 2nd embodiment of this invention. 本発明の第三の実施形態を示す図である。It is a figure which shows 3rd embodiment of this invention. 従来の実施形態を示す図である。It is a figure which shows the conventional embodiment.

符号の説明Explanation of symbols

1 回路基板
2 ランド
3 穴
4 短絡用導体
5 半田ペースト
6 電子部品
7 補助導体
8 導電性接合材
DESCRIPTION OF SYMBOLS 1 Circuit board 2 Land 3 Hole 4 Shorting conductor 5 Solder paste 6 Electronic component 7 Auxiliary conductor 8 Conductive joining material

Claims (5)

電子部品の端子電極と電気的に接続される一対のランドを有する回路基板のランド接続方法であって、前記一対のランドの間に短絡用導体を配置し、前記短絡用導体と前記一対のランドを接続することによって短絡させることを特徴とする回路基板のランド接続方法。  A circuit board land connection method comprising a pair of lands electrically connected to terminal electrodes of an electronic component, wherein a short-circuit conductor is disposed between the pair of lands, and the short-circuit conductor and the pair of lands. A method for connecting lands on a circuit board, characterized in that the circuit board is short-circuited. 前記短絡用導体は、前記一対のランドとは異なる面上に配置され、前記一対のランドの間に穴を設け、前記穴に半田を充填して溶融することによって前記短絡用導体と前記一対のランドを短絡させることを特徴とする請求項1に記載の回路基板のランド接続方法。  The shorting conductor is disposed on a surface different from the pair of lands, and a hole is provided between the pair of lands, and the hole is filled with solder and melted to melt the shorting conductor and the pair of lands. 2. The circuit board land connection method according to claim 1, wherein the lands are short-circuited. 電子部品の端子電極と電気的に接続される一対のランドを有する回路基板であって、前記一対のランドの間に短絡用導体が配置され、前記短絡用導体は前記一対のランドとは異なる面上に配置され、前記一対のランドの間に、半田を充填して溶融することによって前記一対のランドと前記短絡用導体を短絡させるための穴が設けられていることを特徴とする回路基板。  A circuit board having a pair of lands electrically connected to terminal electrodes of an electronic component, wherein a shorting conductor is disposed between the pair of lands, and the shorting conductor is different from the pair of lands. A circuit board, which is disposed above and has a hole between the pair of lands for short-circuiting the pair of lands and the short-circuiting conductor by filling and melting the solder. 前記短絡用導体は、前記一対のランドが形成されている面と反対側の面に形成されていることを特徴とする請求項3に記載の回路基板。  The circuit board according to claim 3, wherein the short-circuiting conductor is formed on a surface opposite to the surface on which the pair of lands are formed. 前記回路基板は多層回路基板であり、前記短絡用導体は、回路基板の内部に内蔵されていることを特徴とする請求項3に記載の回路基板。  The circuit board according to claim 3, wherein the circuit board is a multilayer circuit board, and the short-circuiting conductor is built in the circuit board.
JP2006114995A 2006-03-22 2006-03-22 Circuit board land connection method and the circuit board Withdrawn JP2007258654A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130290A (en) * 2007-11-27 2009-06-11 Sharp Corp Printed board and conductor pattern structure of the same
WO2013088493A1 (en) * 2011-12-12 2013-06-20 パイオニアデジタルデザインアンドマニュファクチャリング株式会社 Circuit substrate, and method of manufacturing circuit substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130290A (en) * 2007-11-27 2009-06-11 Sharp Corp Printed board and conductor pattern structure of the same
WO2013088493A1 (en) * 2011-12-12 2013-06-20 パイオニアデジタルデザインアンドマニュファクチャリング株式会社 Circuit substrate, and method of manufacturing circuit substrate

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