KR20130059356A - Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies - Google Patents

Abstract

A printed circuit board manufacturing method using parallel processing to interconnect with a subassembly is provided. In one embodiment, the present invention provides a core subassembly comprising at least one metal layer, providing the plurality of single-metal layer carriers after parallel processing each of the plurality of single-metal layer carriers, And attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly.

Description

Printed circuit board manufacturing method using parallel processing to interconnect subassemblies {METHODS OF MANUFACTURING PRINTED CIRCUIT BOARDS USING PARALLEL PROCESSES TO INTERCONNECT WITH SUBASSEMBLIES}

Field of invention

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to printed circuit boards and methods of manufacturing the same, and more particularly to methods of manufacturing printed circuit boards using a parallel process to interconnect with subassemblies.

BACKGROUND OF THE INVENTION

Most electronic systems include printed circuit boards with high density electronic interconnects. The printed circuit board (PCB) may comprise one or more circuit cores, substrates, or carriers. In one fabrication scheme for a printed circuit board having one or more circuit carriers, electronic circuitry (eg, pads, electronic interconnects, etc.) is assembled on opposite sides of the individual circuit carriers so that a pair of circuits Form a layer. The circuit layer pairs of such circuit boards thus form an adhesive (or prepreg or bond ply), laminate the circuit layer pairs and adhesive in a press, cure the resulting circuit board structure, drill through-holes, The through-holes are then plated with copper material to interconnect circuit layer pairs, thereby physically and electronically bonding to form a printed circuit board.

A curing process is used to cure the adhesive to provide a permanent material bond of the circuit board structure. However, the adhesive generally shrinks significantly during the curing process. Shrinkage, together with later through-hole drilling and plating processes, can cause significant stress on the entire structure, which leads to damage or unreliable interconnections or couplings between circuit layers. Thus, there is a need for materials and processes that can compensate for this shrinkage and can provide more stress free and reliable electronic interconnection between pairs of circuit layers.

In addition, plating through-holes (or vias) with copper material requires additional, expensive, and time consuming process sequences that are difficult to perform with rapid turnaround times. 1 is a flow chart of a sequential lamination process for printed circuit board fabrication with stacked vias including expensive and time consuming sequential lamination and plating steps. Thus, printing that can be manufactured quickly and easily and / or ensures alignment of interconnects (i.e. through-holes or micro vias) on a printed circuit board by reducing the repetition of key processes and thereby reducing manufacturing time and costs There is a need to provide a circuit board and a method of manufacturing the same.

Summary of the Invention

Aspects of embodiments of the invention relate to methods of manufacturing printed circuit boards using parallel processing to interconnect with subassemblies. One embodiment of the present invention provides a method of manufacturing a printed circuit board, the method comprising: providing a core subassembly comprising at least one metal layer carrier; Providing the plurality of single-metal layer carriers after parallel processing each of the plurality of single-metal layer carriers, wherein at least one parallel processing of the plurality of single-metal layer carriers comprises a first surface of the substrate. Imaging a photoresist on at least one part of the substrate having at least one copper foil formed thereon, etching a portion of the at least one copper foil from the substrate, at least one photoresist Removing at least one part of the at least one copper foil to thereby form at least one copper foil pad, applying a lamination adhesive to the second surface of the substrate, a protective film Applying to the lamination adhesive, at least one micro via in the second surface of the substrate Exposing the at least one copper foil pad to form a fill, filling a conductive paste into the at least one micro via, and removing the protective film for attachment to expose the lamination adhesive on the substrate. Includes; And attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly.

Another embodiment of the present invention provides a method of manufacturing a printed circuit board, the method comprising: providing a core subassembly comprising at least one metal layer carrier; Providing the plurality of single-metal layer carriers after parallel processing each of the plurality of single-metal layer carriers, wherein at least one parallel processing of the plurality of single-metal layer carriers is a minimum formed on the first surface of the substrate. Imaging a photoresist on at least one part of the substrate having one copper foil, etching a portion of the at least one copper foil from the substrate, removing at least one photoresist to remove the at least one Exposing at least one part of a copper foil to thereby form at least one copper foil pad, applying a lamination adhesive to the second surface of the substrate, applying a protective film to the lamination adhesive, at least one Micro vias in the second surface of the substrate to form the at least one copper Exposing a foil pad, filling a conductive paste into the at least one micro via, and removing the protective film for attachment to expose the lamination adhesive on the substrate; Attaching at least two of the plurality of single-metal layer carriers to each other and to a first surface of the core subassembly; And attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly.

Another embodiment of the present invention provides a method of manufacturing a printed circuit board, the method comprising: providing a core subassembly comprising at least one metal layer carrier; Attaching the plurality of single-metal layer carriers together to form a first subassembly after parallel processing each of the plurality of single-metal layer carriers, wherein the parallel processing of at least one of the plurality of single-metal layer carriers comprises a substrate Imaging a photoresist on at least one part of the substrate having at least one copper foil formed on a first surface of the, etching a portion of the at least one copper foil from the substrate, at least one photo Removing the resist to expose at least one part of the at least one copper foil to thereby form at least one copper foil pad, applying a lamination adhesive to the second surface of the substrate, applying a protective film to the lamination Applying to the adhesive, at least one micro via in the second surface of the substrate Forming to expose the at least one copper foil pad, filling a conductive paste into the at least one micro via, and removing the protective film for attachment to expose the lamination adhesive on the substrate. box; Attaching the plurality of single-metal layer carriers to each other after parallel processing each of the plurality of single-metal layer carriers to form a second subassembly; Attaching the first subassembly to a first surface of the core subassembly; And attaching the second subassembly to a second surface of the core subassembly.

Brief Description of Drawings
1 is a flowchart of a sequential lamination process for printed circuit board fabrication with stacked vias including sequential lamination and plating steps.
2 is a flow chart of a printed circuit board fabrication process with stacked vias including a single lamination process in accordance with one embodiment of the present invention.
3A-3G illustrate a single metal layer substrate manufacturing process for a printed circuit board having stacked (or staggered) micro vias and used in a single lamination cycle or process sequence, according to one embodiment of the invention.
4A is a mixed printed circuit comprising four etched single metal layer substrates and two etch-unetched single metal layer substrates of FIGS. 3A-3G, sandwiching the core subassembly, according to one embodiment of the invention. Cross-sectional exploded view of the substrate.
FIG. 4B is a cross-sectional exploded view of a mixed printed circuit board including six etched single metal layer substrates of FIG. 3G sandwiching a core subassembly, in accordance with an embodiment of the present invention.
4C is a cross-sectional exploded view of a mixed printed circuit board including six single metal layer substrates of FIG. 3G in pre-compressed form, sandwiching core subassemblies, according to one embodiment of the invention.
5 is a cross section of the final mixed printed circuit board of FIG. 4B or 4C.
FIG. 6 is a cross section of a mixed printed circuit board including an outer build up layer sandwiching two single metal layer substrates on both sides of a four metal layer core subassembly, according to one embodiment of the invention.
7 is a cross-sectional view of a mixed printed circuit board including one buildup layer attached to one of two single metal layer substrates, sandwiching four metal layer core subassemblies in accordance with one embodiment of the present invention. to be.
FIG. 8 is a cross-sectional view of a mixed printed circuit board including the six single metal layer substrates of FIG. 3G sandwiching a core subassembly comprising active elements, in accordance with one embodiment of the present invention.
9 is a cross-sectional view of a mixed printed circuit board including the six single metal layer substrates of FIG. 3G sandwiching a core subassembly comprising active elements, in accordance with one embodiment of the present invention.
FIG. 10 is a cross section of a printed circuit board assembly including a cutout region to separate the soft portion of the assembly from the rigid section, in accordance with one embodiment of the present invention. FIG.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, some exemplary embodiments of the invention are presented and described for purposes of illustration. As will be appreciated by one of ordinary skill in the art, the disclosed exemplary embodiments may be modified in various ways without departing from the spirit or scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. There may be parts shown in the drawings that are not described in the detailed description or parts not shown in the drawings, because they are not essential to a full understanding of the invention. Similar reference numerals are indicated for similar configurations.

2 is a flow chart of a printed circuit board manufacturing process with stacked vias including a single lamination process in accordance with one embodiment of the present invention. Compared with the prior art process of FIG. 1, the single lamination process of FIG. 2 includes substantially fewer process steps. More specifically, the single lamination process of FIG. 2 eliminates many of the lamination and plating process steps required in the sequential lamination process for manufacturing multi-layer printed circuit boards. Aspects of a single lamination process for circuit board manufacture are further described in US Pat. No. 7,523,545 and US Provisional Patent Application 61/189171, the entire contents of each of which are incorporated herein by reference.

In the flowchart shown in FIG. 2, the process performs a number of process steps associated with a printed circuit board. In another embodiment, another suitable printed circuit board technique may be used instead of the presented technique, including conventional PCB fabrication techniques, for example. In some embodiments, the process does not perform all of the operations described. In another embodiment, the process performs additional work. In one embodiment, the processes perform the operations in a different order than the ones presented. In some embodiments, the process performs some work simultaneously. In one embodiment, the process moves directly from "LAYUP AND LAMINATE" to "FINAL FINISH". In one embodiment, "developing, plating, stripping, etching, strip (DEVELOP, PLATE, STRIP, ETCH, STRIP)" is replaced by "developing, etching, strip (DEVELOP, ETCH, STRIP)".

3A-3G illustrate a single metal layer substrate manufacturing process for a printed circuit board having stacked (or staggered) micro vias and used in a single lamination cycle or process sequence, according to one embodiment of the invention.

As shown in FIG. 3A, a two-sided substrate or carrier 10 is prepared. Substrate 10 includes copper foil 10a and metal, ceramic, or insulating materials (e.g., FR4, LCP, Thermount, BT, GPY, such as Teflon) formed on opposite sides or surfaces of substrate 10. Teflon), thermally conductive carbon (stablecor), halogen-free insulating material, etc., where GPY is a laminate not suitable for the FR4 category, such as polyimide, polyimide films such as apton® aziri A core material 10b consisting of aziridine cured epoxy, bismalimide, and another electrical grade of laminate). However, the present invention is not limited to this. For example, in one embodiment of the present invention, a single sided core or substrate is used having a copper foil (eg, a single foil 10a) formed on only one side of the substrate. In another embodiment, another suitable substrate or conductive layer material may be used.

In the embodiment shown in FIG. 3A, the substrate 10 has a thickness in the range of 3-4 mils (or about 3-4 mils). However, in another embodiment, the substrate and another component may have another suitable dimension.

In FIG. 3B, two photoresists 20 are imaged on the substrate 10. Here, the two photoresists 20 presented are laser-direct-image (or printed) on one side (ie, bottom side) of the substrate 10. However, the present invention is not limited to this. For example, two photoresists can be imaged using any suitable printing technique such as, for example, photo, silkscreen, offset, inkjet, and the like. In another embodiment, more than two or less photoresists may be imaged on the substrate.

In FIG. 3C, the copper foil 10a is etched from the substrate 10 except for the portion of the copper foil 10a covered by the two photoresists 20, the photoresist 20 being then stripped The corresponding copper foil pad 11 is exposed. However, the present invention is not limited to this. For example, in another embodiment of the present invention, one or more single-metal layer carriers (eg, one or more single side circuits) are formed by providing a metal plate (eg, stainless steel sheet).

In more detail for the process using the metal plate, copper flash (about 5 microns) is electrolytic flash plated on one or more sides of the metal plate. One or more photoresists are applied on one or more flash surfaces of the metal plate. The photoresist is then imaged (eg, negatively imaged) to develop one or more cavities. Copper is then plated in the cavity. The photoresist is then stripped to form one or more copper foil pads for one or more circuit layers. In addition, one or more prepregs are applied on the copper foil pad to laminate the prepregs and the metal plate. The prepreg is then cured. The prepregs are thus laminated and cured with metal plates, copper foil pads and copper flashes therebetween. The copper foil pad and copper flash together with the cured prepreg are then peeled off the metal plate. The copper flash is then etched to expose the copper foil pads on the cured prepreg.

The previously described circuit layer comprising a copper foil pad (e.g., pad 11 or a circuit layer comprising the copper pad has already been formed), protective film (or mylar sheet) 40 shown in FIG. Attachment to the core material 10b of the substrate 10 (or cured prepreg) by a lamination adhesive (or prepreg or uncured prepreg) 30 inserted between the sheet 40 and the core material 10b. do. In FIG. 3D, the protective layer or mylar sheet 40 is shown attached to the side of the substrate 10 opposite the side of the substrate 10 where the two copper foil pads 11 are located. However, the protective film of the present invention is not limited to only mylar sheets, and may be any suitable material such as polyester, directional polypropylene, polyvinylfluoride, polyethylene, high density polyethylene, polyethylene naphthalate, pacotan, polymethylpentene, or It can be prepared by a combination of these.

In FIG. 3E, vias or micro via holes 50 are formed in the substrate 10 (or cured prepreg). Each of the micro via holes 50 is formed by laser drilling (and / or mechanical drilling) in the substrate 10 (or hardened prepreg) with holes in the range of 4 to 10 mils (or about 4 to 10 mils) in diameter. . In another embodiment, other suitable diameter micro via holes can be used. In another embodiment, vias or micro via holes may be created using a photo imagable dielectric process, plasma process, stamping process, or another suitable via generation process. Can

In FIG. 3F, a conductive paste (or ink) 60 is filled in each micro via 50 formed in the substrate 10 (or cured prepreg), and in FIG. 3G, the mylar sheet 40 It is then peeled off to form a single-metal layer carrier 70 for lay-up and lamination.

In another embodiment, the metal layer carrier can include additional layers or components. In one embodiment, for example, the metal layer carrier may comprise a buried resistor or buried capacitor implemented using a particular layer or lamination. The metal layer carrier may also be surface treated prior to the adhesive, including but not limited to organometallic, immersion gold, immersion silver, immersion tin, and / or outer copper. It may include. Such surface treatment can improve both electrical and thermal conductivity.

Metal layer carriers include, but are not limited to, cut sheet laminators, lamination presses, hot roll laminators, vacuum laminators, quick lamination presses ), Or several lamination machines, including another suitable lamination machine.

4A shows four etched single metal layer substrates 70-1 and two etch-free single metal layers of FIGS. 3A-3G, sandwiching core subassembly 102, according to one embodiment of the invention. A cross sectional exploded view of a mixed printed circuit board 100-1 including a substrate 70-2. The outer single metal layer substrate, ie the non-etched substrate 70-2, has an unetched copper layer on its outer surface. The inner single metal layer substrate 70-1 has a copper layer etched on its outer surface.

Core subassembly 102 has two plated or filled through-hole vias 104 and four metal layers formed using a lamination process. In another embodiment, core subassembly 102 includes more than two or fewer vias, including through-hole vias and / or micro vias. Each single metal layer substrate or carrier 70-1, 70-2 includes multiple micro vias 150 filled with a conductive paste that forms two stacked vias per assembly. To assemble the mixed PCB 100, the single metal layer substrates 70-1, 70-2 can be aligned above and below the core subassembly 102 and are all pressed together to form one or more bonds. The layers are used to sandwich the subassembly 102.

In the embodiment shown in FIG. 4A, the core subassembly has four metal layer carriers. In another embodiment, the core subassembly has more than four or less metal layer carriers. In one such case, the core subassembly is assembled using a process involving only one stack. In another such embodiment, the core subassembly is assembled using a process that does not include lamination (eg, the core subassembly has no vias). In some embodiments, the layers of the core subassembly are stacked when single metal layer carriers are stacked together to form a PCB. In another embodiment, the layers of the core subassembly are stacked before single metal layer carriers are stacked together to form a mixed PCB.

In the embodiment shown in FIG. 4A, three single metal layer carriers are located above the core subassembly and three single metal layer carriers are located below the core subassembly. In still other embodiments, more than three or less than three single metal layer carriers may be located above the core subassembly. Similarly, in another embodiment, more than three or less than three single metal layer carriers may be located underneath the core subassembly. In one embodiment, one or more core subassembly layers are replaced with a single metal layer substrate having conductive paste micro vias. In the embodiment shown in FIG. 4A, the mixed PCB includes two stacked vias. In another embodiment, a mixed PCB may include more than two or less stacked vias.

FIG. 4B illustrates a mixed printed circuit board 100-2 including six etched single metal layer substrates 70-1 of FIG. 3G, sandwiching the core subassembly, according to one embodiment of the invention. Cross section exploded view. 4B is substantially similar to FIG. 4A except that the outer single metal layer carrier is not etched away in FIG. 4A but rather is etched according to the process described in FIGS. 3A-3G. In another aspect, FIG. 4B may act as described above with respect to FIG. 4A. In FIG. 4B, one stack of micro vias 151 is aligned with one through hole via 104 below it, while another micro via 150 is offset from the through hole via 104. have.

FIG. 4C illustrates a mixed printed circuit board 100 comprising six single metal layer substrates 70-1 of FIG. 3G in pre-compressed form, sandwiching the core subassembly, according to one embodiment of the invention. Is a cross-sectional exploded view of -3). The pre-compressed form is a top assembly 80-1 comprising three of six single metal layer substrates 70-1 and a bottom assembly comprising three of six single metal layer substrates 70-1. (80-2). The embodiment of FIG. 4C is similar to the embodiment of FIG. 4B except that the single metal layer substrate of FIG. 4B starts in a compressed state. In another aspect, FIG. 4C may act as described above with respect to FIG. 4B.

5 is a cross-sectional view of the final mixed printed circuit board 100-4 according to the embodiment of FIG. 4B or 4C. In some embodiments, the final mixed printed circuit board for FIG. 4A may be similar to FIG. 5, except that the outer layer may include etched copper.

6 illustrates a buildup layer 270-2 sandwiching two single metal layer substrates 270-1 on both sides of a four metal layer core subassembly 202, in accordance with one embodiment of the present invention. A cross section of a mixed PCB 200 that includes. In some embodiments, mixed PCB 200 includes the advantages of both a sequential laminated plate manufacturing process and a single laminated plate manufacturing process. For example, the mixed PCB 200 can provide a substantially or exactly flat outer surface. In some embodiments, such substantially or exactly flat surfaces may be very desirable. In addition, the mixed PCB 200 manufacturing process can dramatically improve manufacturing time and cost by eliminating multiple lamination and plating steps.

Four single metal layer substrates 270-1 include multiple stacked micro vias 250 and can be formed using any of the processes described above. The four metal layer core subassembly 202 includes multiple through-hole vias 204 and can be formed using the sequential deposition process described above. In some embodiments, the through-hole vias can be replaced with micro vias filled with copper or conductive paste. Two buildup layers 270-2 include multiple plated or filled micro vias (eg, through-hole vias) 284 and can be formed using the PCB fabrication process described in FIG. 1.

In the embodiment shown in FIG. 6, the PCB includes two single metal layer substrates above and below the core subassembly. In another embodiment, the PCB may comprise more than two single metal layer substrates. In the embodiment shown in FIG. 6, one build up layer 270-2 is positioned over a single metal layer substrate and one build up layer 270-2 is positioned under a single metal layer substrate. In yet other embodiments, two or more buildup layers may be located above a single metal layer substrate and two or more buildup layers may be located below a single metal layer substrate. In one embodiment, one or more buildup layers are replaced or all removed with another layer of one of the single metal layer substrates.

In the embodiment shown in FIG. 6, four metal layer core subassemblies 202 are located in the center of the mixed PCB 200. In another embodiment, the core subassembly can include more or less than four layers. In the embodiment shown in FIG. 6, the four metal layer core subassemblies include two plated or filled through-hole vias 204. In another embodiment, the core subassembly can be implemented with more than two or fewer vias. In one such embodiment, the core subassembly can be implemented without any vias. In the embodiment shown in FIG. 6, the mixed PCB includes two stacked vias. In yet other embodiments, the mixed PCB may include more than two or less stacked vias.

5 and 6, core subassemblies 102 and 202 include two through hole vias 104 and 204 per subassembly, which through hole vias 104 and 204 are formed of a single metal layer substrate 70-1, 270-1 is offset from stacked via 150. In yet other embodiments, core subassemblies 102 and 202 can include one or more micro vias. In some embodiments, the micro vias are filled with a conductive paste, conductive ink or copper. In one such embodiment, the conductive ink microvia has a trapezoidal cross section where the wider opening of the microvia is close to the centerline of the core subassembly of the core subassembly (eg, microvia 150 of FIG. 5). Note the direction of). In some embodiments, through hole vias in subassemblies 102 and 202 are not offset from stacked vias of a single metal layer substrate.

FIG. 7 shows one buildup layer 270 attached to two of four single metal layer substrates 270-1, sandwiching the four metal layer core subassemblies 202 in accordance with one embodiment of the present invention. Cross-section of the mixed PCB 300, including -2). The mixed PCB 300 includes a buildup layer 270-2 sandwiching two single metal layer substrates 270-1 on one side of the core subassembly 202. The mixed PCB 300 further includes two single metal layer substrates 270-1 sandwiching the four layer core subassembly 202 on the other side of the core subassembly 202. The embodiment shown in FIG. 7 is similar to the embodiment of FIG. 6 except that one of the outer buildup layers has been removed. In another embodiment, one or both of the top single metal layer carriers 270-1 may also be removed. In some embodiments, the structure of the mixed PCB of FIG. 7 can be modified in a similar manner to the variations described above for the mixed PCB of FIG. 6.

8 illustrates six single metal layer substrates 470-1, 470-2 of FIG. 3G sandwiching a core subassembly 402 that includes an active element 406, according to one embodiment of the invention. A cross section of a mixed printed circuit board 400 that includes. The mixed PCB 400 shown in FIG. 8 is similar to that of FIG. 5 except that the core subassembly 402 includes a buried active element 406 and the top single metal layer substrate 470-2 has an active element ( The difference is that it includes additional micro vias 450 that form stacked vias for connection to 406. The active element 406 may be a transistor, an integrated circuit, or another active element typically used in conjunction with a printed circuit board. In the embodiment shown in FIG. 8, the mixed PCB 400 includes a single active element 406. In another embodiment, additional active elements can be used with additional vias to support the various connections required. In some embodiments, the structure of the mixed PCB of FIG. 8 may be modified similar to the variations described above for the mixed PCB of FIGS. 4A, 4B, 4C, 5 and 6. In one embodiment, the active element may be located on or inside either one of the single metal layer substrates. In still other embodiments, the active device can be located on or inside any of the single metal layer substrate and the core subassembly.

FIG. 9 shows two single metal layer substrates 570-1, 570-2 of FIG. 3G sandwiching a core subassembly 502 including an active element 506, according to one embodiment of the invention. A cross section of a mixed printed circuit board 500 comprising a. The PCB shown in FIG. 9 is substantially similar to that shown in FIG. 8 except that it includes additional vias 584 for connecting with active elements 506 embedded in the core assembly 502 more than in FIG. 8. different. In another aspect, the mixed PCB of FIG. 9 may function and be modified to function like the mixed PCB of FIG. 8.

FIG. 10 illustrates a printed circuit board assembly including a cutout region to separate the flexible portion 606 of the assembly from the rigid sections 602, 604, according to one embodiment of the invention. 600 is the cross section. Via 608 may provide electrical interconnection between various soft, rigid, and rigid-soft layers.

In some embodiments, circuit board assembly 600 may be formed using any of the manufacturing processes described herein, including, for example, the single lamination process described above in FIGS. 3A-3G, 4A-4C. Conventional lamination processes, including sequential lamination type processes, require relatively many process steps that can damage the flexible or rigid-flex substrates during the manufacturing process. More specifically, conventional process steps such as plating, cleaning, scrubbing, and planarization can damage flexible or rigid-flex substrates and cause problems related to achieving specific positional tolerances. In connection with the manufacturing process described herein, circuit board assembly 600 avoids many of the repetitive steps that are common in conventional processes, including, for example, intrusive plating, cleaning, scrubbing, and planarization process steps. Or can be formed with substantially reduced.

While the foregoing description includes many specific embodiments of the invention, they should not be considered as limiting the scope of the invention, but rather as examples of such specific embodiments of the invention. Accordingly, the scope of the invention should not be determined by the presented embodiments, but should be determined by the appended claims and their equivalents.

For example, the manufacturing processes described herein include, but are not limited to, flip chips, MEMS circuits, ceramic packages, organic packages, high density substrates, BGA substrates, rigid substrates, flexible substrates, and rigid substrates. It can be used in combination with many techniques, including rigid-flex substrates.

In some embodiments, micro vias and vias described herein may be referred to as Z-axis interconnects.

In the above embodiments, the circuit board assembly is formed using through hole vias, vias, micro vias, blind vias or another via. In another embodiment, these vias are interchangeable and / or may be replaced with other suitable vias known in the art.

Claims (18)

In a printed circuit board manufacturing method, the method
Providing a core subassembly comprising at least one metal layer carrier;
Providing the plurality of single-metal layer carriers after parallel processing each of the plurality of single-metal layer carriers, wherein the parallel processing of at least one of the plurality of single-metal layer carriers is:
Imaging a photoresist on at least one part of the substrate having at least one copper foil formed on a first surface of the substrate;
Etching a portion of the at least one copper foil from the substrate;
Removing at least one photoresist to expose at least one part of the at least one copper foil to thereby form at least one copper foil pad;
Applying a lamination adhesive to the second surface of the substrate;
Applying a protective film to the lamination adhesive;
Forming at least one micro via in the second surface of the substrate to expose the at least one copper foil pad;
Filling a conductive paste into said at least one micro via; And
Removing the protective film for attachment to expose the lamination adhesive on the substrate; And
Attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly
A printed circuit board manufacturing method comprising a. The method of claim 1, wherein attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly
Attaching at least two of the plurality of single-metal layer carriers to each other and to a first surface of the core subassembly; And
Attaching at least two of the plurality of single-metal layer carriers to each other and to a second surface of the core subassembly
A printed circuit board manufacturing method comprising a. The method of claim 1, wherein attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly
Attaching at least two of the plurality of single-metal layer carriers to each other to form a first single lamination subassembly and attaching to the first surface of the core subassembly; And
Attaching a first buildup layer having at least one micro via to the surface of the first single lamination subassembly
A printed circuit board manufacturing method comprising a. The method of claim 1, wherein attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly
Attaching at least two of the plurality of single-metal layer carriers to each other to form a first single lamination subassembly and attaching to the first surface of the core subassembly;
Attaching at least two of the plurality of single-metal layer carriers together to form a second single lamination subassembly and attaching to a second surface of the core subassembly;
Attaching a first buildup layer having at least one micro via to the surface of the first subassembly; And
Attaching a second buildup layer having at least one micro via to the surface of the second subassembly
A printed circuit board manufacturing method comprising a. The method of claim 1, wherein the core subassembly comprises at least one micro via. The method of claim 1, wherein the core subassembly comprises at least one active element. 7. The method of claim 6, wherein the at least one active device comprises a device selected from the group consisting of transistors and integrated circuits. The method of claim 1,
Providing at least one second single-metal layer carrier after paralleling the single-metal layer carrier, wherein the parallel processing of the second single-metal layer carrier is:
Applying a second lamination adhesive to a second surface of the second substrate having a copper foil formed on the first surface of the second substrate;
Applying a second protective film to the second lamination adhesive;
Forming at least one micro via in the second surface of the second substrate to expose a portion of the copper foil;
Filling a conductive paste into said at least one micro via; And
Removing the second protective film for attachment to expose the second lamination adhesive on the second substrate,
Wherein attaching at least two of the plurality of single-metal layer carriers to each other and to a surface of the core subassembly
Attaching at least two of the plurality of single-metal layer carriers to each other to form a first single lamination subassembly and attaching to a surface of the core subassembly; And
Attaching at least one second single-metal layer carrier to a surface of the first single lamination subassembly. The method of claim 8,
Attaching at least two of the plurality of single-metal layer carriers together to form a second single lamination subassembly and attaching to a second surface of the core subassembly; And
Attaching a second single-metal layer carrier of at least one second single-metal layer carrier to the surface of the second single lamination subassembly
Further comprising, a printed circuit board manufacturing method. The method of claim 1,
Attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly attaching at least two of the plurality of single-metal layer carriers to each other to form a first single lamination subassembly; Attaching to a surface of the core subassembly;
Wherein the core subassembly comprises a via;
Wherein the position of the via of the core subassembly is offset from the position of the micro via of the first single lamination subassembly. The method of claim 10 wherein the vias of the core subassembly are plated through hole vias. The method of claim 10 wherein the vias of the core subassembly are micro vias. The method of claim 10, wherein the vias of the core subassembly are copper filled micro vias. The method of claim 10 wherein the vias of the core subassembly are micro vias filled with a conductive paste. The method of claim 1,
Attaching at least two of the plurality of single-metal layer carriers to each other and to the core subassembly attaching at least two of the plurality of single-metal layer carriers to each other to form a first single lamination subassembly; Attaching to a surface of the core subassembly;
Wherein the core subassembly comprises a via;
Wherein the position of the via of the core subassembly is substantially aligned with the position of the micro via of the first single lamination subassembly. The method of claim 1, wherein the substrate comprises a substrate selected from the group consisting of a flexible substrate and a rigid-flex substrate. In a printed circuit board manufacturing method, the method
Providing a core subassembly comprising at least one metal layer carrier;
Providing the plurality of single-metal layer carriers after parallel processing each of the plurality of single-metal layer carriers, wherein the parallel processing of at least one of the plurality of single-metal layer carriers is:
Imaging a photoresist on at least one part of the substrate having at least one copper foil formed on a first surface of the substrate;
Etching a portion of the at least one copper foil from the substrate;
Removing at least one photoresist to expose at least one part of the at least one copper foil to thereby form at least one copper foil pad;
Applying a lamination adhesive to the second surface of the substrate;
Applying a protective film to the lamination adhesive;
Forming at least one micro via in the second surface of the substrate to expose the at least one copper foil pad;
Filling a conductive paste into said at least one micro via; And
Removing the protective film for attachment to expose the lamination adhesive on the substrate;
Attaching at least two of the plurality of single-metal layer carriers to each other and to a first surface of the core subassembly; And
Attaching at least two of the plurality of single-metal layer carriers to each other and to a second surface of the core subassembly
A printed circuit board manufacturing method comprising a. In a printed circuit board manufacturing method, the method
Providing a core subassembly comprising at least one metal layer carrier;
Attaching the plurality of single-metal layer carriers to each other after parallel processing each of the plurality of single-metal layer carriers to form a first subassembly, wherein the parallel processing of at least one of the plurality of single-metal layer carriers is:
Imaging a photoresist on at least one part of the substrate having at least one copper foil formed on a first surface of the substrate;
Etching a portion of the at least one copper foil from the substrate;
Removing at least one photoresist to expose at least one part of the at least one copper foil to thereby form at least one copper foil pad;
Applying a lamination adhesive to the second surface of the substrate;
Applying a protective film to the lamination adhesive;
Forming at least one micro via in the second surface of the substrate to expose the at least one copper foil pad;
Filling a conductive paste into said at least one micro via; And
Removing the protective film for attachment to expose the lamination adhesive on the substrate;
Attaching the plurality of single-metal layer carriers to each other after parallel processing each of the plurality of single-metal layer carriers to form a second subassembly;
Attaching the first subassembly to a first surface of the core subassembly; And
Attaching the second subassembly to a second surface of the core subassembly
A printed circuit board manufacturing method comprising a.

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