TW201318500A - Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies - Google Patents

Abstract

Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies are provided. In one embodiment, the invention relates to a method of manufacturing a printed circuit board including providing a core subassembly including at least one metal layer, providing a plurality of one-metal layer carriers after parallel processing each of the plurality of one-metal layer carriers, and attaching at least two of the plurality of one-metal layer carriers with each other and with the core subassembly.

Description

Printed circuit board manufacturing method using parallel processing interconnect sub-components Field of invention

The present invention relates generally to printed circuit boards and methods of fabricating the same, and more particularly to a method of fabricating printed circuit boards using parallel processing interconnect sub-assemblies.

Background of the invention

Most electronic systems include printed circuit boards with high density electronic interconnects. A printed circuit board (PCB) can include one or more circuit cores, substrates or carriers. In a manufacturing process for a printed circuit board having the one or more circuit carriers, electronic circuits (eg, pads, electronic interconnects, etc.) are fabricated on opposite sides of a separate circuit carrier to form A pair of circuit layers. The circuit layer pairs of the circuit board can then be laminated by pressing an adhesive (or a prepreg or a bonding polymer) to laminate the circuit layer pairs and the adhesive, and the resulting circuit is cured. The plate structure is formed by drilling through holes, and then the through holes are plated with a copper material, and the circuit layers are interconnected to be physically or electronically connected to form the printed circuit board.

The curing process is used to cure the adhesive to provide a permanent physical bond to the board construction. However, the adhesive generally shrinks significantly during the curing process. This shrinkage, coupled with later through hole drilling and plating procedures, can result in considerable stresses in the overall construction, resulting in damage or unreliable interconnection or bonding between the circuit layers. Accordingly, there is a need in the industry for materials and related procedures that can compensate for this shrinkage and provide reliable electrical connections between pairs of circuit layers that are unaffected by stress.

In addition, penetration or via plating with copper material requires an additional, expensive and time consuming process that cannot be performed in a fast and flexible manner. Figure 1 is a sequential lamination process for fabricating a printed circuit board having laminated vias that includes expensive and time consuming sequential lamination and plating steps. Thus, the industry is concerned with a printed circuit board that can be manufactured quickly and easily, and/or that can ensure the alignment of interconnects on a printed circuit board, by reducing the number of repetitions of critical processes, thereby reducing manufacturing time and cost. The method has requirements.

Summary of invention

The views of embodiments of the present invention are related to and intended to use a printed circuit board manufacturing method that interconnects interconnected sub-assemblies. An embodiment of the present invention provides a method of fabricating a printed circuit board, the method comprising: providing a core material assembly including at least one metal layer carrier, after providing for processing each of the plurality of single metal layer carriers in parallel a plurality of single metal layer supports, wherein parallel processing of at least one of the plurality of single metal layer supports comprises imaging a photoresist onto at least a portion of a substrate, the at least a portion of the substrate having a base formed thereon At least one copper foil on the first surface of the material; etching the substrate to have at least one portion of the copper foil; removing at least one layer of photoresist to expose at least a portion of the at least one copper foil to form at least one copper foil liner Applying a laminating adhesive to the second surface of the substrate; applying a protective film to the laminating adhesive; forming at least one microvia in the second surface of the substrate to expose the at least one copper a foil liner; filling a conductive paste into the at least one microvia; and removing the protective film to expose a laminate adhesion on the substrate for adhesion , And the other a plurality of single carrier wherein the at least two metal layers adhere to each other, and secondary adhesion with the core assembly.

Another embodiment of the present invention provides a method of fabricating a printed circuit board, the method comprising: providing a core material assembly including at least one metal layer carrier, after processing each of the plurality of single metal layer carriers in parallel Providing a plurality of single metal layer supports, wherein parallel processing of at least one of the plurality of single metal layer supports comprises imaging the photoresist onto at least a portion of a substrate, the at least a portion of the substrate having a formation At least one copper foil on the first surface of the substrate; etching the substrate to have at least one portion of the copper foil; removing at least one layer of photoresist to expose at least a portion of the at least one copper foil, thereby forming at least one copper foil a pad; applying a laminating adhesive to the second surface of the substrate; applying a protective film to the laminating adhesive; forming at least one microvia in the second surface of the substrate to expose the at least a copper foil liner; filling a conductive paste into the at least one microvia; and removing the protective film to expose a laminate on the substrate for adhesion And adhering at least two of the plurality of single metal layer carriers to each other and adhering to the first surface of the core material assembly; and adhering at least two of the plurality of single metal layer carriers to each other, and Adhered to the core sub-assembly.

Yet another embodiment of the present invention provides a method of fabricating a printed circuit board, the method comprising providing a core material assembly including at least one metal layer carrier, after processing each of the plurality of single metal layer carriers in parallel And adhering the plurality of single metal layer carriers to each other to form a first subassembly, wherein parallel processing of at least one of the plurality of single metal layer carriers comprises imaging the photoresist to at least one substrate In one part, the substrate has at least one copper foil formed on the first surface of the substrate in the at least one portion; etching the substrate to have at least one portion of the copper foil; removing at least one layer of photoresist to expose the portion At least a portion of at least one layer of copper foil to form at least one copper foil liner; a laminating adhesive applied to the second surface of the substrate; a protective film applied to the laminating adhesive; and a second in the substrate Forming at least one microvia in the surface to expose the at least one copper foil liner; filling the conductive paste into the at least one microvia; and removing the protective film In order to expose the laminating adhesive on the substrate for adhesion, after processing the plurality of single metal layer carriers in each of the single metal layer carriers in parallel, the plurality of single metal layer carriers are adhered to each other to form a second time. The assembly, the first assembly is adhered to one of the first surfaces of the core sub-assembly, and the second sub-assembly is adhered to the second surface of the core sub-assembly.

Simple illustration

Figure 1 is a flow diagram of a sequential lamination process for fabricating a printed circuit board having laminated vias including sequential lamination and plating steps.

2 is a flow diagram of a sequential lamination process for fabricating a printed circuit board having laminated vias, including a separate lamination process, in accordance with an embodiment of the present invention.

Figures 3a-3g show a procedure for fabricating a single metal layer substrate for a separate lamination cycle or treatment with stacked (or staggered) microvias in accordance with an embodiment of the present invention. In the program.

4a is a cross-sectional exploded view of a hybrid printed circuit board including four etched single metal layer substrates of the 3a-3g pattern and two unetched layers, in accordance with an embodiment of the present invention. A single metal layer substrate sandwiches a core sub-assembly.

Figure 4b is a cross-sectional exploded view of a hybrid printed circuit board in accordance with an embodiment of the present invention, comprising six etched single metal layer substrates shown in Figure 3g, sandwiching a core material to make.

Figure 4c is a cross-sectional exploded view of a hybrid printed circuit board in accordance with an embodiment of the present invention, comprising a single metal layer substrate in the form of a pre-compression shown in Figures 3g, sandwiching a core Material sub-assembly.

Figure 5 is a cross-sectional view of one of the completed hybrid printed circuit boards of Figure 4b or 4c.

Figure 6 is a cross-sectional view of a hybrid printed circuit board including an external hybrid layer sandwiching two single sides on a side of a four-layer metal core sub-assembly, in accordance with an embodiment of the present invention. Metal layer substrate.

Figure 7 is a cross-sectional view of a hybrid printed circuit board according to an embodiment of the present invention, comprising a hybrid layer adhered to two single metal layer bases sandwiching a four-layer metal core assembly One of the materials.

8 is a cross-sectional view of a hybrid printed circuit board including six core metal substrates shown in FIG. 3g sandwiching a core material including an active device, in accordance with an embodiment of the present invention. Sub-assembly.

Figure 9 is a cross-sectional view of a hybrid printed circuit board according to an embodiment of the present invention, comprising six single metal layer substrates shown in Figure 3g sandwiching a core material including an active device Sub-assembly.

Figure 10 is a cross-sectional view of a hybrid printed circuit board including a cut-away region separating the flexible portion of the assembly from the rigid portion, in accordance with an embodiment of the present invention.

Detailed description of the preferred embodiment

In the following detailed description, embodiments of the invention are shown and described. The exemplified embodiments can be modified in various different ways without departing from the spirit and scope of the invention. Therefore, the drawings and description are to be regarded as illustrative rather than limiting. The presence or absence of a component in the figures, which is shown or not shown in the drawings, is not discussed in this specification as such components are not essential to a comprehensive understanding of the invention. The same reference numbers represent the same elements.

2 is a flow diagram of a procedure for fabricating a printed circuit board having one of stacked vias in accordance with an embodiment of the present invention, the program including a single lamination process. The single lamination procedure of Figure 2 essentially involves fewer processing steps than the prior art procedure of Figure 1. More specifically, the single lamination process of Figure 2 eliminates the lamination and plating process steps of the sequential lamination process required to fabricate a multilayer printed circuit board. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

In the flow chart shown in Figure 2, the program implements some processing steps relating to the printed circuit board. In other embodiments, other suitable printed circuit board technologies can be used in place of those shown in the drawings, including conventional printed circuit board fabrication techniques. In some embodiments, the program does not perform all of the described homework. In other embodiments, the program performs additional work. In an embodiment, the program performs the jobs in an order different from the display. In some embodiments, the program performs certain jobs simultaneously. In one embodiment, the program proceeds directly from "stacking and lamination" to "final finished product." In one embodiment, "developing, plating, stripping, etching, stripping" is replaced by "developing, etching, stripping".

Figures 3a-3g show a procedure for fabricating a single metal layer substrate for a separate lamination cycle or treatment with stacked (or staggered) microvias in accordance with an embodiment of the present invention. In the program.

As shown in Figure 3a, a double-sided substrate or carrier 10 is prepared. The substrate 10 includes a copper foil 10a formed on the opposite side or surface of the substrate, and a core material 10b made of metal, ceramic or insulating material (for example, FR4, liquid crystal polymer (LCP), heat bonding. (Thermount), diiminamide-triazabenzene (BT), GPY, such as Teflon, heat conducting carbon (stablecor), halogen-free insulating materials, etc., of which GPY is a non- A laminate of the FR4 type, such as polyamine, a film such as Kapton polyamine, aziridine hardened epoxy, bismalimide, and other electrical grade laminates. However, the invention is not limited to this. For example, in one embodiment of the invention, a single layer of core material or substrate is used, and a copper foil (e.g., a single layer film) is formed only on one side of the substrate. In other embodiments, other suitable substrate and conductive layer materials can be used.

In the embodiment shown in Figure 3a, the substrate has a thickness ranging from 3 to 4 mils (mil, one thousandth of an inch) (or about 3 to 4 mils). However, in other embodiments, the substrate and other components can have other suitable dimensions.

In Figure 3b, two layers of photoresist 20 are imaged onto the substrate 10. Herein, the two-layer photoresist is shown directly imaged (or printed) by laser onto one side (ie, the bottom side) of the substrate 10. However, the invention is not limited to this. For example, the two layer photoresist can be imaged using any suitable printing method, such as optical, screen, offset, ink jet, and the like. In one embodiment, more or less than two layers of photoresist can be imaged onto the substrate.

In the 3c figure, the copper foil 10a is etched away from the substrate except for the portion of the copper foil 10a covered by the two layers of photoresist 20, and then the covered portion is stripped to expose the corresponding copper. Foil liner 11. However, the invention is not limited to this. For example, in another embodiment of the invention, one or more single metal layer carriers (e.g., one or more single side circuits) are formed by making a metal sheet, such as a stainless steel sheet.

In more detail regarding the procedure for using the metal sheet, a thin copper plating is thinly plated onto one or more sides of the metal sheet by copper rapid plating. One or more layers of photoresist are applied to one or more of the thin plated surfaces of the metal sheet. The photoresist is then imaged (e.g., negative imaged) to develop one or more chambers. Copper is then electroplated into the chambers. The photoresist is then stripped to form one or more copper foil pads for one or more circuit layers. In addition, one or more prepreg systems are applied to the copper foil liners to laminate the prepregs and the metal sheets. The prepregs are then hardened. The prepregs are thus laminated and hardened with the metal layer with a copper foil liner and a thin copper coating. The copper foil liner is then stripped from the copper thin layer and the hardened prepreg from the metal sheet. The copper thin coating is then etched away to expose the copper foil liner on the hardened prepreg.

The circuit layer including the copper foil pad described above (for example, the pad 11 or the circuit layer including the copper pad) is formed, and one of the protective films (or Mylar) shown in FIG. 3d is formed. 40 is attached to the substrate 10 by laminating the adhesive between the Mylar sheet 40 and the core material 10b (or a prepreg or an uncured prepreg) 30 (or a hardened pre-process) The core material 10b of the dip). In Fig. 3d, the protective layer or Mylar sheet 40 is attached to the other side of the substrate having two sides of the copper foil liner 11. However, the present invention is not limited to this case using only Mylar sheets, and it can be made of any other suitable material such as polyester, oriented polypropylene, polyvinyl fluoride, polyethylene, high density polyethylene, poly 2, 6 naphthalate, pacothane, polymethylpentene or a combination thereof.

In Figure 3e, a via or microvia 50 is formed in the substrate 10 (or hardened prepreg). Each microvia 50 is drilled in the substrate 10 (or hardened prepreg) by a laser drilling (and/or mechanical drilling) to a diameter ranging from 4 to 10 mils (or about 4 to 10). The hole of mil) is formed. In other embodiments, microvias having other suitable diameters can be used. In another embodiment, the vias or microvias can be created using a photoimageable dielectric program, a plasma program, an imprint program, or other suitable via generation program.

In Fig. 3f, a conductive paste (or ink) 60 is filled into each of the microvias 50 formed in the substrate 10 (or hardened prepreg), and in the 3g diagram, the Mylar is subsequently stripped. Sheet 40 is formed to form a single metal layer carrier 70 for lamination and lamination.

In other embodiments, the metal layer carrier can include additional layers or components. In one embodiment, for example, the metal layer carrier can include a buried or a buried capacitor using a special layer or laminate. The metal layer carrier can also include a surface treatment including, but not limited to, organometallic, immersion gold, immersion silver, immersion tin, and/or application of outer layer copper prior to adhesion. These surface treatments can improve electron and thermal conductivity.

The metal layer supports can be laminated using a variety of different laminating machines including, but not limited to, all laminating presses, a laminating press, a hot rolling laminator, a vacuum laminator, a fast Laminating embossing machine, or other suitable laminating machine.

Figure 4a is a cross-sectional exploded view of a hybrid printed circuit board 100-1 in accordance with an embodiment of the present invention, the printed circuit board including four single metal layer substrates 70 shown in Figures 3a-3g -1 and two unetched single metal layer substrates 70-2 sandwich a core subassembly 102. The outer single metal layer substrate or the unetched substrate 70-2 has an unetched copper layer on its outer surface.

The core subassembly 102 has four metal layers formed using a lamination process and two plated or filled through vias 104. In other embodiments, the core sub-assembly 102 includes more or less than two through holes including through holes and/or micro vias. The single metal layer substrate or carrier (70-1, 70-2) each includes a plurality of microvias 150 that are filled with a conductive paste such that each component forms two stacked vias. To combine the hybrid printed circuit board 100, the single metal layer substrates (70-1, 70-2) can be aligned above and below the core material subassembly 102 and one or more adhesive layers can be used. And squeezing to clamp the secondary assembly 102.

In the embodiment shown in Figure 4a, the core subassembly has four metal layer carriers. In other embodiments, the core subassembly can have more or less than four metal layer carriers. In this case, the core subassembly is assembled using a procedure that utilizes only a single lamination. In other such embodiments, the core subassembly is assembled using a procedure for no lamination (e.g., the core subassembly has no through holes). In some embodiments, the layers of the core subassembly are laminated while the single metal layer carriers are laminated together to form the PCB. In other embodiments, the layers of the core subassembly are laminated prior to laminating the single metal layer carriers together.

In the embodiment shown in Figure 4a, three single metal layer carriers are disposed over the core subassembly and three single metal layer carriers are disposed thereunder. In other embodiments, more or less than three single metal layer carriers can be disposed over the core subassembly. Likewise, in other embodiments, more or less than three single metal layer carriers can be disposed beneath the core subassembly. In one embodiment, one or more of the core sub-assemblies are replaced by a single metal layer substrate having conductive microvias. In the embodiment shown in Figure 4a, the hybrid PCB includes two stacked vias. In other embodiments, the hybrid PCB can have more or less than two stacked vias.

Figure 4b is a cross-sectional exploded view of a hybrid printed circuit board including six etched single metal layer substrates shown in Figure 3g sandwiching the core subassembly. 4b is substantially similar to Figure 4a except that the outer single metal layer carrier is etched according to the procedure described in Figures 3a-3g, rather than being etched as in Figure 4a. Among other points of view, Figure 4b can be implemented as shown in Figure 4a. In Fig. 4b, a stack of microvias 151 are aligned with the underlying through vias 104, while other microvias 150 are offset from the through vias 104.

Figure 4c is a cross-sectional exploded view of a hybrid printed circuit board 100-3 in accordance with an embodiment of the present invention comprising six single metal layer substrates 70 in a pre-extrusion form as shown in Figure 3g. -1 clamps a core material subassembly. The pre-extrusion form includes an upper assembly 80-1 comprising three of the six single metal layer substrates 70-1 and a lower assembly 80-2 including the six single metal layers The other three of the substrates 70-1. The embodiment of Figure 4c is similar to that of Figure 4b except that the single metal layer substrate of Figure 4b is initially in a squeezed state. Among other points of view, Figure 4c can be implemented as shown in Figure 4b.

Figure 5 is a cross-sectional view of a completed hybrid printed circuit board 100-4 in accordance with the embodiments of Figure 4b or 4c. In many embodiments, the hybrid printed circuit board completed in one of Figures 4a is similar in appearance to Figure 5 except that the outer layer comprises unetched copper.

Figure 6 is a cross-sectional view of a hybrid PCB 200 in accordance with an embodiment of the present invention including a composite layer 270-2 sandwiching two of the two sides of a four-layer metal core sub-assembly 202. Single metal layer substrate 270-1. In many embodiments, the hybrid PCB 200 includes the advantages of a sequential laminate fabrication process as well as a single laminate fabrication process. For example, the hybrid PCB 200 can provide an outer surface that is substantially or indeed flat. In some embodiments, the substantially or indeed flat surfaces are highly desirable in the industry. In addition, the manufacturing process of the hybrid PCB 200 can improve manufacturing time and cost by removing many different lamination and plating steps.

The four single metal layer substrates 270-1 include a plurality of stacked microvias 250 and can be formed using any of the procedures described above. The four metal layer core sub-assemblies 202 include a plurality of through vias 204 and can be formed using the sequential lamination procedure described above. In some embodiments, the through vias are replaced by microvias filled with copper or a conductive paste. The two combined layers 270-2 include a plurality of plated or filled microvias (e.g., through vias) 284 and can be formed using the procedure for fabricating the PCB shown in FIG.

In the embodiment shown in Figure 6, the PCB includes two single metal layer substrates above and below the core subassembly. In other embodiments, the PCB can include more than two single metal layer substrates. In the embodiment shown in FIG. 6, a combined layer 270-2 is disposed over the single metal layer substrates, and a combined layer 270-2 is disposed under the single metal layer substrates. In other embodiments, more than one combined layer can be disposed over the single metal layer substrates, and more than one combined layer can be disposed beneath the single metal layer substrates. In one embodiment, one or more of the combined layers are replaced with one of the other single metal layer substrates, or are removed together.

In the embodiment shown in FIG. 6, a four metal core sub-assembly 202 is disposed in the center of the hybrid PCB 200. In other embodiments, the core sub-assembly can include more or less than four layers. In the embodiment shown in FIG. 6, the four metal core component subassembly includes two plated or filled through vias 204. In other embodiments, the core subassembly can include more or less than two through holes. In one such embodiment, the core subassembly can have no through holes. In the embodiment shown in Figure 6, the hybrid PCB includes two stacked vias. In other embodiments, the hybrid PCB can include more or less than two stacked vias.

In Figures 5 and 6, the core sub-assemblies 102 and 202 each include two through vias (104, 204) that are offset from the stacked vias 150 of the single metal layer substrate (70-1, 270-1). In other embodiments, the core sub-assemblies 102 and 202 can include one or more micro-through holes. In some embodiments, the microvias are filled with conductive paste ink or copper. In this embodiment, the conductive ink microvia has a trapezoidal cross section, wherein one of the microvias has a wider opening closest to a centerline of the core subassembly (see, for example, the micrograph in FIG. 5) The direction of the through hole 150). In some embodiments, the through vias of the sub-assemblies 102 and 202 are not offset from the stacked vias of the single metal layer substrate.

Figure 7 is a cross-sectional view of a hybrid PCB 300 in accordance with an embodiment of the present invention, including a composite layer 270-2 adhered to the four single metal substrate substrates Both of the four metal layer core sub-assemblies 202. The hybrid PCB 300 includes a combination layer 270-2 that sandwiches two single metal layer substrates 270-1 on one side of the core material subassembly 202. The hybrid PCB 300 further includes two single metal layer substrates 270-1 that sandwich the four metal core material subassembly 202 on the other side of the core material subassembly 202. The embodiment shown in Fig. 7 is similar to the embodiment of Fig. 6, except that the outer combined layer is removed. In other embodiments, one or both of the upper single metal layer carriers 270-1 can also be removed. In many embodiments, the configuration of the hybrid PCB of Figure 7 can be modified in a manner similar to that described above for the hybrid PCB of Figure 6.

Figure 8 is a cross-sectional view of a hybrid printed circuit board 400 in accordance with an embodiment of the present invention, comprising a single metal layer substrate (470-1, 470-2) of six 3g views sandwiching an active A core subassembly 402 of device 406. In addition to the core subassembly 402 including the active device 406 of the embodiment, and the upper single metal layer substrate 470-2 includes additional micro vias 450 that form a stacked via for connection to the active device 406, The hybrid PCB 400 shown in Fig. 8 is similar to the embodiment of Fig. 5. The active device 406 can be a transistor, an integrated circuit, or other active device commonly used in conjunction with a printed circuit board. In the embodiment shown in FIG. 8, the hybrid PCB 400 includes a separate active device 406. In other embodiments, additional active devices and additional through holes can be used to support a variety of different desired connections. In many embodiments, the hybrid PCB of Figure 8 can be modified in a manner similar to that described above for the hybrid PCBs of Figures 4a, 4b, 4c, 5 and 6. In an embodiment, the active device can be located on or in one of the single metal layer substrates. In other embodiments, the active device can be located on or within any of the single metal layer substrate and the core material subassembly.

Figure 9 is a cross-sectional view of a hybrid printed circuit board 500 in accordance with an embodiment of the present invention, comprising two single metal layer substrates (570-1, 570-2) of the 3g pattern sandwiched including an active A core subassembly 502 of device 506. In addition to including an additional via 584 for connecting the active device 506, which is further implemented within the core sub-assembly 502 of FIG. 8, the PCB shown in FIG. 9 is substantially identical to FIG. Similar. Among other points of view, the hybrid PCB of FIG. 9 can function as the hybrid PCB of FIG. 8, and can be modified as usual.

Figure 10 is a cross-sectional view of a printed circuit board assembly 600 in accordance with an embodiment of the present invention including a cut-away region separating the flexible region 606 of the assembly from the rigid segments (602, 604). The vias 608 are capable of providing electrical interconnection between different flexible, rigid, and hard-flex layers.

In many embodiments, the board assembly 600 can be formed using any of the fabrication procedures described herein, including, for example, the separate lamination procedures described above in Figures 3a-3g, 4a-4c. Conventional lamination procedures, including sequential lamination procedures, require a significant amount of processing steps that can damage a flexible or rigid-flexible substrate during the manufacturing process. More specifically, conventional processing steps such as electroplating, cleaning, wiping, and planarization can damage flexible or rigid-flexible substrates and cause problems associated with some positioning tolerances. In accordance with the fabrication procedures described herein, the circuit board assembly 600 can be formed while avoiding or significantly reducing the repetitive steps commonly used in many conventional applications, including, for example, invasive plating, cleaning, wiping, and planarization processing steps.

Although the description above contains many specific embodiments of the invention, it should not be construed as a limitation of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is defined by the scope of the appended claims and their equivalents.

For example, the fabrication procedures described herein can be used in conjunction with a number of techniques including, but not limited to, flip chip, microelectromechanical systems (MEMS) circuits, ceramic packages, organic packages, high density substrates, ball grid array (BGA) based Materials, rigid substrates, flexible substrates, and hard-flex substrates.

In some embodiments, the microvias described herein may be referred to as Z-axis interconnects.

In the above embodiments, the circuit board assembly is formed using through vias, vias, micro vias, blind vias or other vias. In other embodiments, the through holes can be interchangeably used and/or can be replaced with other suitable through holes well known in the art.

10. . . Double-sided substrate

10a. . . Copper foil

10b. . . Core

11. . . Copper foil liner

20. . . Photoresist

30. . . Laminated adhesive

40. . . Protective film

50. . . Through hole / micro through hole

60. . . Conductive pulp

70. . . Single metal layer carrier

70-1. . . Single metal layer substrate

70-2. . . Single metal layer substrate

80-1. . . Upper assembly

80-2. . . Lower assembly

100-1. . . Mixed printed circuit board

100-2. . . Mixed printed circuit board

100-3. . . Mixed printed circuit board

100-4. . . Mixed printed circuit board

102. . . Core subassembly

104. . . Through hole

150. . . Micro via

151. . . Micro via

200. . . Mixed printed circuit board

202. . . Core subassembly

204. . . Through hole

250. . . Stacked micro vias

270-1. . . Single metal layer substrate

270-2. . . Combination layer

284. . . Micro via

300. . . Mixed printed circuit board

400. . . Mixed printed circuit board

402. . . Core subassembly

406. . . Active device

450. . . Micro via

470-1. . . Single metal layer substrate

470-2. . . Single metal layer substrate

500. . . Mixed printed circuit board

502. . . Core subassembly

504. . . Through hole

506. . . Active device

550. . . Micro via

570-1. . . Single metal layer substrate

570-2. . . Single metal layer substrate

584. . . Through hole

600. . . Printed circuit board assembly

602. . . Hard section

604. . . Hard section

606. . . Flexible area

608. . . Through hole

Figure 1 is a flow diagram of a sequential lamination process for fabricating a printed circuit board having laminated vias including sequential lamination and plating steps.

2 is a flow diagram of a sequential lamination process for fabricating a printed circuit board having laminated vias, including a separate lamination process, in accordance with an embodiment of the present invention.

Figures 3a-3g show a procedure for fabricating a single metal layer substrate for a separate lamination cycle or treatment with stacked (or staggered) microvias in accordance with an embodiment of the present invention. In the program.

4a is a cross-sectional exploded view of a hybrid printed circuit board including four etched single metal layer substrates of the 3a-3g pattern and two unetched layers, in accordance with an embodiment of the present invention. A single metal layer substrate sandwiches a core sub-assembly.

Figure 4b is a cross-sectional exploded view of a hybrid printed circuit board in accordance with an embodiment of the present invention, comprising six etched single metal layer substrates shown in Figure 3g, sandwiching a core material to make.

Figure 4c is a cross-sectional exploded view of a hybrid printed circuit board in accordance with an embodiment of the present invention, comprising a single metal layer substrate in the form of a pre-compression shown in Figures 3g, sandwiching a core Material sub-assembly.

Figure 5 is a cross-sectional view of one of the completed hybrid printed circuit boards of Figure 4b or 4c.

Figure 6 is a cross-sectional view of a hybrid printed circuit board including an external hybrid layer sandwiching two single sides on a side of a four-layer metal core sub-assembly, in accordance with an embodiment of the present invention. Metal layer substrate.

Figure 7 is a cross-sectional view of a hybrid printed circuit board according to an embodiment of the present invention, comprising a hybrid layer adhered to two single metal layer bases sandwiching a four-layer metal core assembly One of the materials.

8 is a cross-sectional view of a hybrid printed circuit board including six core metal substrates shown in FIG. 3g sandwiching a core material including an active device, in accordance with an embodiment of the present invention. Sub-assembly.

Figure 9 is a cross-sectional view of a hybrid printed circuit board according to an embodiment of the present invention, comprising six single metal layer substrates shown in Figure 3g sandwiching a core material including an active device Sub-assembly.

Figure 10 is a cross-sectional view of a hybrid printed circuit board including a cut-away region separating the flexible portion of the assembly from the rigid portion, in accordance with an embodiment of the present invention.

Claims (18)

A method for manufacturing a printed circuit board comprising the steps of: providing a core sub-assembly comprising at least one single metal layer carrier; after processing each of the plurality of single metal layer carriers in parallel, setting a plurality a single metal layer carrier, wherein parallel processing of at least one of the plurality of single metal layer carriers comprises: imaging a photoresist onto at least a portion of a substrate, the at least a portion of the substrate having a substrate formed on the substrate At least one copper foil on the first surface; etching at least one portion of the copper foil from the substrate; removing the at least one photoresist to expose at least a portion of the at least one copper foil, thereby forming at least one copper foil liner Applying a laminating adhesive to a second surface of the substrate; applying a protective film to the laminating adhesive; forming at least one micro via in the second surface of the substrate to expose the at least one copper foil a pad; filling the conductive paste into the at least one microvia; and removing the protective film to expose an adhesive for adhesion on the substrate; and making the plurality of single gold Wherein the at least two carrier layers adhere to each other, and the adhesion of the core sub-assembly. The method of claim 1, wherein the step of adhering at least two of the plurality of single metal layer carriers to each other and adhering to the core subassembly comprises: at least two of the plurality of single metal layer carriers Adhering to each other and adhering to a first surface of the core subassembly; and adhering at least two of the plurality of single metal layer carriers to each other and to a second surface of the core subassembly. The method of claim 1, wherein the step of adhering at least two of the plurality of single metal layer carriers to each other and adhering to the core subassembly comprises: at least two of the plurality of single metal layer carriers Adhering to each other to form a first separate laminated subassembly and adhering to the first surface of the core subassembly; bonding a first composite layer having at least one micro via to the first separate lamination A surface of the component. The method of claim 1, wherein the step of adhering at least two of the plurality of single metal layer carriers to each other and adhering to the core subassembly comprises: at least two of the plurality of single metal layer carriers Adhering to each other to form a first individual laminated subassembly and adhering to one of the first surfaces of the core subassembly; causing at least two of the plurality of single metal layer carriers to adhere to each other to form a second Laminating the subassembly separately and adhering to a second surface of the one of the core subassemblies; bonding a first combination layer having at least one microvia to a surface of the first individual laminated subassembly; A second combination of one of the microvias is adhered to a surface of the second individual laminated subassembly. The method of claim 1, wherein the core subassembly comprises at least one micro via. The method of claim 1, wherein the core subassembly comprises at least one active device. The method of claim 6, wherein the at least one active device comprises a device selected from the group consisting of a transistor or an integrated circuit. The method of claim 1, further comprising: after processing the single metal layer carrier in parallel, providing at least one second single metal layer carrier, wherein the parallel processing of the second single metal layer carrier comprises: applying a a second adhesive layer to a second surface of a second substrate, the second substrate having a copper foil formed on one of the first surfaces of the second substrate; applying a second protective film to the first a second laminating adhesive; forming at least one microvia in the second surface of the second substrate to expose a portion of the copper foil; filling the conductive paste into the at least one microvia; and removing the second a protective film to expose a second laminating adhesive for adhesion on the second substrate; wherein at least two of the plurality of single metal layer carriers adhere to each other and adhere to a surface of the core sub-assembly Adhesively bonding at least two of the plurality of single metal layer carriers to each other to form a first separate laminated subassembly and adhering to a surface of the core subassembly: and the at least one second single metal layer The carrier is adhered to one of the surfaces of the first individual laminated subassembly. The method of claim 8, further comprising: adhering at least two of the plurality of single metal layer carriers to each other to form a second separate laminated subassembly, and one of the core subassemblies Adhesion of the second surface; and adhering one of the second single metal layer carriers of the at least one second single metal layer carrier to one surface of the second individual laminated subassembly. The method of claim 1, wherein the at least two of the plurality of single metal layer carriers are adhered to each other and to the core sub-assembly comprises adhering at least two of the plurality of single metal layer carriers to each other Forming a first separate laminated subassembly and adhering to a surface of the core subassembly; wherein the core subassembly comprises a through hole; wherein one of the through holes of the core subassembly is associated with the first One of the microvias of a single laminated subassembly is phase shifted. The method of claim 10, wherein the through hole of the core subassembly is a plated through hole. The method of claim 10, wherein the through hole of the core sub-assembly is a micro-via. The method of claim 10, wherein the through hole of the core material sub-assembly is a micro-via hole filled with copper. The method of claim 10, wherein the through hole of the core material sub-assembly is a micro-via hole filled with a conductive paste. The method of claim 1, wherein the at least two of the plurality of single metal layer carriers are adhered to each other and the bonding to the core sub-assembly comprises adhering at least two of the plurality of single metal layer carriers to each other, Forming a first separate laminated subassembly and adhering to a surface of the core subassembly; wherein the core subassembly comprises a through hole; wherein a position of the through hole of the core subassembly is substantially A position of the first individual laminated subassembly is aligned. The method of claim 1, wherein the substrate comprises a substrate selected from the group consisting of a flexible substrate and a rigid-flexible substrate. A method of manufacturing a printed circuit board comprising the steps of: providing a core subassembly comprising at least one single metal layer carrier; and after processing each of the plurality of single metal layer carriers in parallel, providing a plurality of single metal layers a carrier, wherein the parallel processing of at least one of the plurality of single metal layer carriers comprises: imaging a photoresist onto at least a portion of a substrate, the substrate having at least a first surface formed on the substrate a copper foil; etching the portion of the at least one copper foil from the substrate; removing the at least one photoresist to expose at least a portion of the at least one copper foil to form at least one copper foil liner; applying a laminating adhesive to a second surface of the substrate; applying a protective film to the laminating adhesive; forming at least one micro via hole in the second surface of the substrate to expose the at least one copper foil pad; filling the conductive paste Into the at least one microvia; and removing the protective film to expose an adhesive for adhesion on the substrate; and at least two of the plurality of single metal layer carriers This adhesion, and the adhesion to the surface of one sub-assembly of the first core member; such that the plurality of single carrier wherein the at least two metal layers adhere to each other, and the adhesion surface of one of the second sub-assembly of the core. A method of manufacturing a printed circuit board comprising the steps of: providing a core subassembly comprising at least one single metal layer carrier; and after processing each of the plurality of single metal layer carriers in parallel, causing the plurality of single metal layers The carriers are adhered to each other to form a first subassembly, wherein the parallel processing of at least one of the plurality of single metal layer carriers comprises: imaging the photoresist onto at least a portion of a substrate having the At least one copper foil on the first surface of the substrate; etching at least one portion of the copper foil from the substrate; removing the at least one photoresist to expose at least a portion of the at least one copper foil to form at least one copper a foil liner; applying a lamination adhesive to a second surface of the substrate; applying a protective film to the lamination adhesive; forming at least one microvia in the second surface of the substrate to expose the at least a copper foil liner; filling a conductive paste into the at least one microvia; and removing the protective film to expose an adhesive for adhesion on the substrate; After each of the single metal layer carriers, the plurality of single metal layer carriers are adhered to each other to form a second sub-assembly; the first sub-assembly is adhered to the first surface of one of the core sub-assemblies; The second assembly is adhered to a second surface of the core subassembly.