KR20130054283A - Device and method for producing electronic device, and pair of compressed members thereof - Google Patents

Device and method for producing electronic device, and pair of compressed members thereof Download PDF

Info

Publication number
KR20130054283A
KR20130054283A KR1020127030656A KR20127030656A KR20130054283A KR 20130054283 A KR20130054283 A KR 20130054283A KR 1020127030656 A KR1020127030656 A KR 1020127030656A KR 20127030656 A KR20127030656 A KR 20127030656A KR 20130054283 A KR20130054283 A KR 20130054283A
Authority
KR
South Korea
Prior art keywords
laminated body
terminal
electronic component
groove
laminate
Prior art date
Application number
KR1020127030656A
Other languages
Korean (ko)
Inventor
도루 메우라
히로키 니카이도
Original Assignee
스미또모 베이크라이트 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 스미또모 베이크라이트 가부시키가이샤 filed Critical 스미또모 베이크라이트 가부시키가이샤
Publication of KR20130054283A publication Critical patent/KR20130054283A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/36—Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
    • B23K35/3612—Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest with organic compounds as principal constituents
    • B23K35/3613—Polymers, e.g. resins
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101—Chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101—Chamber
    • H01L2224/7511—High pressure chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75272—Oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/75303—Shape of the pressing surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/75303—Shape of the pressing surface
    • H01L2224/75305—Shape of the pressing surface comprising protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75312—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/75981—Apparatus chuck
    • H01L2224/75985—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H01L2224/81075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81091—Under pressure
    • H01L2224/81093—Transient conditions, e.g. gas-flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81906—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Medicinal Chemistry (AREA)
  • Polymers & Plastics (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

표면에 땜납층을 갖는 제 1 단자를 갖는 제 1 전자 부품 (1) 과, 이 제 1 전자 부품 (1) 의 제 1 단자에 접합되는 제 2 단자를 갖는 제 2 전자 부품 (2) 을 구비하는 전자 장치의 제조 방법은, 복수의 제 1 전자 부품 (1) 의 제 1 단자와 복수의 제 2 전자 부품 (2) 의 제 2 단자를 각각 대향 배치시키고, 각 제 1 단자와 각 제 2 단자 사이에 수지층 (3) 을 배치하여 복수의 적층체를 형성하고, 복수의 적층체를 가열하면서, 복수의 적층체를 동시에 적층체의 적층 방향으로부터 협압한다.A first electronic component 1 having a first terminal having a solder layer on its surface, and a second electronic component 2 having a second terminal joined to the first terminal of the first electronic component 1 are provided. The manufacturing method of an electronic device arrange | positions the 1st terminal of the some 1st electronic component 1, and the 2nd terminal of the some 2nd electronic component 2, respectively, and between each 1st terminal and each 2nd terminal. A plurality of laminates are formed by arranging the resin layer 3 in the plurality, and the plurality of laminates are pinched from the lamination direction of the laminate at the same time while the plurality of laminates are heated.

Description

전자 장치의 제조 방법 및 장치, 그 1 쌍의 협압 부재{DEVICE AND METHOD FOR PRODUCING ELECTRONIC DEVICE, AND PAIR OF COMPRESSED MEMBERS THEREOF}The manufacturing method and apparatus of an electronic device, its pair of pinching members TECHNICAL FIELD [DEVICE AND METHOD FOR PRODUCING ELECTRONIC DEVICE, AND PAIR OF COMPRESSED MEMBERS THEREOF}

본 발명은, 대립되는 단자가 땜납으로 접합되어 있는 전자 장치의 제조 방법 및 장치, 그 1 쌍의 협압 부재에 관한 것이다.TECHNICAL FIELD This invention relates to the manufacturing method and apparatus of the electronic device in which the opposing terminal is joined by solder, and its pair of pinching members.

전자 장치는, 예를 들어, 반도체 소자의 단자와 다른 반도체 소자의 단자, 반도체 소자의 단자와 기판의 단자, 또는, 기판의 단자와 다른 기판의 단자를, 땜납을 사용하여 접합하는 공정을 실시함으로써 제조된다.For example, the electronic device performs a process of joining a terminal of a semiconductor element with a terminal of another semiconductor element, a terminal of the semiconductor element and a terminal of the substrate, or a terminal and a terminal of the other substrate using solder. Are manufactured.

땜납을 사용하여 접합을 실시한 후의 반도체 소자간, 반도체 소자와 기판 사이, 또는 기판간 (이하, 반도체 소자간 등이라고 한다) 에는, 간극이 발생하기 때문에, 수지의 경화물로 간극을 매립할 필요가 있다.Since the gap is generated between the semiconductor elements after the bonding is performed using solder, or between the semiconductor elements and the substrate, or between the substrates (hereinafter, referred to as semiconductor elements, etc.), it is necessary to fill the gaps with the cured resin. have.

종래에는, 땜납을 사용하여 접합한 후에, 반도체 소자간 등에, 유동성 열경화성 수지를 흘려넣고, 이어서, 수지를 경화시킴으로써, 반도체 소자간 등의 간극을 매립하고 있었다. 그런데, 상기 서술한 방법에서는 반도체 소자간 등에, 간극없이 유동성의 열경화성 수지를 흘려넣는 것이 어렵기 때문에, 이하와 같은 방법이 특허문헌 1 에서 제안되어 있다.Conventionally, after joining using solder, the fluid thermosetting resin was poured in between semiconductor elements etc., and then hardening resin, and the clearance gap between semiconductor elements was filled. By the way, in the method mentioned above, since it is difficult to flow a flowable thermosetting resin between semiconductor elements etc. without a clearance, the following method is proposed by patent document 1. As shown in FIG.

특허문헌 1 에는, 기판 표면에 필름상의 언더 필 수지를 배치하고, 그 후, 언더 필 수지 상에 반도체 소자를 탑재하는 방법 및 장치가 개시되어 있다. 특허문헌 1 에서는, 언더 필 수지 상에 반도체 소자를 탑재한 후, 반도체 소자를 기판에 압접하고, 반도체 소자와 기판의 적층체를 형성한 후, 고압 분위기 중에서 언더 필 수지를 경화시키고 있다.Patent Document 1 discloses a method and an apparatus for disposing a film-like underfill resin on a substrate surface, and then mounting a semiconductor element on the underfill resin. In patent document 1, after mounting a semiconductor element on underfill resin, a semiconductor element is crimped | bonded to a board | substrate, and after forming a laminated body of a semiconductor element and a board | substrate, underfill resin is hardened in high pressure atmosphere.

일본 공개특허공보 2004-311709호Japanese Unexamined Patent Publication No. 2004-311709

본 발명자들은, 전자 장치의 양산시에, 이하의 방법을 생각하였다. 먼저, 열판 상에, 열경화성 수지층이 각각 형성된 복수의 기판을 배치한다. 그 후, 열경화성 수지층 상에, 반도체 소자를 배치한다.The present inventors considered the following method at the time of mass production of an electronic device. First, the some board | substrate with which the thermosetting resin layer was formed respectively is arrange | positioned on a hotplate. Thereafter, the semiconductor element is disposed on the thermosetting resin layer.

이 때, 반도체 소자의 단자가 열경화성 수지층을 관통하고, 기판의 단자와 접촉하도록, 열경화성 수지층 상의 반도체 소자에 하중을 가하고, 압접하여 적층체로 한다. 이 조작을 반복하여 복수의 적층체를 얻는다. 그 후, 적층체의 반도체 소자의 단자, 기판의 단자끼리를 접합함과 함께, 수지층을 가압 큐어한다.At this time, a load is applied to the semiconductor element on the thermosetting resin layer so that the terminal of the semiconductor element passes through the thermosetting resin layer and is in contact with the terminal of the substrate to form a laminate. This operation is repeated to obtain a plurality of laminates. Thereafter, the terminals of the semiconductor elements of the laminate and the terminals of the substrate are bonded to each other, and the resin layer is pressurized and cured.

그러나, 이 방법에서는, 열경화성 수지층이 열판에 의해, 가열 상태가 되므로, 서서히 경화가 진행된다. 첫 번째의 적층체의 기판과 반도체 소자를 압접하고 있는 동안에, 상기 기판과는 상이한 다른 기판 상의 열경화성 수지층의 경화가 진행되는 것이다.However, in this method, since the thermosetting resin layer is heated by the hot plate, curing proceeds gradually. While the substrate of the first laminate and the semiconductor element are press-contacted, curing of the thermosetting resin layer on another substrate different from the substrate proceeds.

따라서, 첫 번째 기판과 반도체 소자를 압접하는 힘과, 마지막 기판과 반도체 소자를 압접하는 힘이 크게 상이하다. 이로써, 기판에 형성된 단자와 반도체 소자에 형성된 단자 사이에서 도통 불량이 발생하여, 신뢰성이 저하되는 것이 염려된다.Accordingly, the force for pressing the first substrate and the semiconductor element and the force for pressing the last substrate and the semiconductor element are greatly different. As a result, conduction failure occurs between the terminal formed on the substrate and the terminal formed on the semiconductor element, and there is a concern that the reliability is lowered.

또한, 여기서는, 기판과 반도체 소자의 적층체를 제작하는 경우에 대해 서술했지만, 이것에 한정되지 않고, 기판끼리, 반도체 소자끼리의 적층체를 제작하는 경우에 있어서도, 동일한 과제가 생긴다.In addition, although the case where the laminated body of a board | substrate and a semiconductor element is produced was demonstrated here, it is not limited to this, The same problem arises also when producing the laminated body of board | substrates and semiconductor elements.

본 발명은 상기 서술한 바와 같은 과제를 감안하여 이루어진 것으로서, 신뢰성이 높은 전자 장치를 안정적으로 제조할 수 있는 전자 장치의 제조 방법 및 장치, 그 협압 부재를 제공하는 것이다.This invention is made | formed in view of the subject mentioned above, and provides the manufacturing method and apparatus of the electronic device which can manufacture highly reliable electronic device stably, and its pinching member.

본 발명에 의하면, 표면에 땜납층을 갖는 제 1 단자를 갖는 제 1 전자 부품과, 이 제 1 전자 부품의 제 1 단자에 접합되는 제 2 단자를 갖는 제 2 전자 부품을 구비하는 전자 장치의 제조 방법으로서, 제 1 전자 부품의 제 1 단자와 제 2 전자 부품의 제 2 단자 사이에, 플럭스 활성 화합물과 열경화성 수지를 함유하는 수지층을 배치하여 적층체를 얻는 공정과, 적층체를 제 1 단자의 땜납층의 융점 이상으로 가열하여 제 1 단자와 제 2 단자를 땜납 접합시키는 공정과, 유체에 의해 적층체를 가압하면서 수지층을 경화시키는 공정을 포함하고, 적층체를 얻는 공정에서는, 복수의 제 1 전자 부품의 제 1 단자와 복수의 제 2 전자 부품의 제 2 단자를 각각 대향 배치시키고, 각 제 1 단자와 각 제 2 단자 사이에 수지층을 배치하여 복수의 적층체를 형성하고, 복수의 적층체를 가열하면서 복수의 적층체를 동시에 적층체의 적층 방향으로부터 협압하는 전자 장치의 제조 방법이 제공된다.According to this invention, manufacture of the electronic device provided with the 1st electronic component which has a 1st terminal which has a solder layer on the surface, and the 2nd electronic component which has a 2nd terminal joined to the 1st terminal of this 1st electronic component. As a method, the process of arrange | positioning the resin layer containing a flux active compound and a thermosetting resin between the 1st terminal of a 1st electronic component and the 2nd terminal of a 2nd electronic component, and obtaining a laminated body, The laminated body is a 1st terminal And a step of soldering the first terminal and the second terminal to a solder joint by heating at or above the melting point of the solder layer, and a step of curing the resin layer while pressing the laminate with a fluid. The first terminal of the first electronic component and the second terminal of the plurality of second electronic components are disposed to face each other, and a resin layer is disposed between each of the first terminals and each of the second terminals to form a plurality of laminates. Lamination This method of manufacturing an electronic device that hyeopap a plurality of the laminate at the same time from the lamination direction of the laminated body is provided with heating.

이 발명에 의하면, 복수의 적층체를 가열하면서, 복수의 적층체를 동시에 적층체의 적층 방향으로부터 협압하고 있다. 이로써, 첫 번째 적층체의 제 1 전자 부품과 제 2 전자 부품을 가열하면서 협압하고 있는 동안에, 다른 적층체를 구성하는 열경화성 수지의 경화가 진행되는 것이 억제된다. 따라서, 신뢰성이 높은 전자 장치를 안정적으로 제조할 수 있다.According to this invention, while heating several laminated bodies, the several laminated bodies are pinched simultaneously from the lamination direction of a laminated body. Thereby, hardening of the thermosetting resin which comprises another laminated body progresses, while suppressing the 1st electronic component and 2nd electronic component of a 1st laminated body, heating, and being pressed. Therefore, a highly reliable electronic device can be manufactured stably.

또, 본 발명에 의하면, 상기 서술한 전자 장치의 제조 방법에 사용되는 장치도 제공할 수 있다. 즉, 본 발명에 의하면, 표면에 땜납층을 갖는 제 1 단자를 갖는 제 1 전자 부품의 상기 제 1 단자와, 이 제 1 전자 부품의 상기 제 1 단자에 접합되는 제 2 단자를 갖는 제 2 전자 부품의 상기 제 2 단자 사이에, 플럭스 활성 화합물과 열경화성 수지를 함유하는 수지층을 배치하여, 적층체를 형성한 후, 상기 제 1 단자와 상기 제 2 단자를 접촉시키기 위한 장치로서, 복수의 적층체를 동시에 협압하는 협압 부재를 구비하는 장치도 제공할 수 있다.Moreover, according to this invention, the apparatus used for the manufacturing method of the above-mentioned electronic device can also be provided. That is, according to this invention, the 2nd electron which has the said 1st terminal of the 1st electronic component which has a 1st terminal which has a solder layer on the surface, and the 2nd terminal joined to the said 1st terminal of this 1st electronic component A device for contacting the first terminal and the second terminal after forming a laminate by arranging a resin layer containing a flux active compound and a thermosetting resin between the second terminals of the component, wherein a plurality of laminates are provided. The apparatus provided with the pinching member which pinches a sieve simultaneously can also be provided.

또한, 본 발명에 의하면, 상기 서술한 전자 장치의 제조 장치의 협압 부재도 제공할 수 있다. 즉, 본 발명에 의하면, 1 쌍의 협압 부재의 홈이 형성되어 있고 적어도 일방은 상하 대칭으로 형성되어 있는 협압 부재도 제공할 수 있다.Moreover, according to this invention, the pinching member of the manufacturing apparatus of the electronic device mentioned above can also be provided. That is, according to this invention, the pinching member in which the groove | channel of a pair of pinching members is formed, and at least one is formed in up-down symmetry can also be provided.

본 발명에 의하면, 신뢰성이 높은 전자 장치를 안정적으로 제조할 수 있는 전자 장치의 제조 방법 및 장치가 제공된다.According to this invention, the manufacturing method and apparatus of the electronic device which can manufacture the highly reliable electronic device stably are provided.

도 1 은 본 발명의 일 실시형태에 관련된 전자 장치의 제조 공정을 나타내는 공정 단면도이다.
도 2 는 전자 장치의 제조 공정을 나타내는 공정 단면도이다.
도 3 은 전자 장치의 제조 공정을 나타내는 공정 단면도이다.
도 4 는 전자 장치의 제조 장치를 나타내는 단면도이다.
도 5 는 전자 장치의 제조 장치를 나타내는 단면도이다.
도 6 은 복수의 적층체가 지그 사이에 끼워진 상태를 나타내는 단면도이다.
도 7 은 지그를 구성하는 부재를 나타내는 평면도이다.
도 8 은 전자 장치의 제조 공정을 나타내는 공정 단면도이다.
도 9 는 전자 장치를 나타내는 단면도이다.
도 10 은 일 변형예의 전자 장치의 제조 장치를 나타내는 단면도이다.
도 11 은 다른 변형예의 전자 장치의 제조 장치를 나타내는 단면도이다.1 is a cross-sectional view showing a process for manufacturing an electronic device according to one embodiment of the present invention.
2 is a cross-sectional view illustrating the manufacturing process of the electronic device.
3 is a cross-sectional view illustrating the manufacturing process of the electronic device.
4 is a cross-sectional view illustrating a manufacturing apparatus of an electronic device.
5 is a cross-sectional view illustrating a manufacturing apparatus of an electronic device.
6 is a cross-sectional view showing a state where a plurality of laminates are sandwiched between jigs.
7 is a plan view of a member constituting a jig.
8 is a cross-sectional view illustrating the process of manufacturing the electronic device.
9 is a cross-sectional view illustrating the electronic device.
10 is a cross-sectional view illustrating a manufacturing apparatus of an electronic device of a modification.
11 is a cross-sectional view illustrating a manufacturing apparatus of an electronic device of another modification.

이하, 본 발명의 실시형태를 도면에 기초하여 설명한다. 처음에, 도 1 내지 도 5 를 참조하여, 본 실시형태의 전자 장치의 제조 방법의 개요에 대해 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described based on drawing. First, with reference to FIGS. 1-5, the outline | summary of the manufacturing method of the electronic device of this embodiment is demonstrated.

본 실시형태의 전자 장치의 제조 방법은, 표면에 땜납층 (112) 을 갖는 제 1 단자 (11) 를 갖는 제 1 전자 부품 (1) 과, 이 제 1 전자 부품 (1) 의 제 1 단자 (11) 에 접합되는 제 2 단자 (21) 를 갖는 제 2 전자 부품 (2) 을 구비하는 전자 장치의 제조 방법이다.The manufacturing method of the electronic device of this embodiment has the 1st electronic component 1 which has the 1st terminal 11 which has the solder layer 112 on the surface, and the 1st terminal (1) of this 1st electronic component 1 ( It is a manufacturing method of the electronic device provided with the 2nd electronic component 2 which has the 2nd terminal 21 joined by 11).

이 전자 장치의 제조 방법은, 제 1 전자 부품 (1) 의 제 1 단자 (11) 와 제 2 전자 부품 (2) 의 제 2 단자 (21) 사이에, 플럭스 활성 화합물과 열경화성 수지를 함유하는 수지층 (3) 을 배치하여 적층체 (4) 를 얻는 공정과, 적층체 (4) 를 제 1 단자 (11) 의 땜납층 (112) 의 융점 이상으로 가열하여, 제 1 단자 (11) 와 제 2 단자 (21) 를 땜납 접합시키는 공정과, 유체에 의해 적층체 (4) 를 가압하면서, 수지층 (3) 을 경화시키는 공정을 포함한다.The manufacturing method of this electronic device is a number containing a flux active compound and a thermosetting resin between the 1st terminal 11 of the 1st electronic component 1, and the 2nd terminal 21 of the 2nd electronic component 2. The process of obtaining the laminated body 4 by arrange | positioning the ground layer 3, and heating the laminated body 4 beyond melting | fusing point of the solder layer 112 of the 1st terminal 11, and the 1st terminal 11 and 1st The process of solder-bonding the 2 terminal 21 and the process of hardening the resin layer 3, pressing the laminated body 4 with a fluid are included.

적층체 (4) 를 얻는 상기 공정에서는, 복수의 제 1 전자 부품 (1) 의 제 1 단자 (11) 와 복수의 제 2 전자 부품 (2) 의 제 2 단자 (21) 를, 각각 대향 배치시켜, 각 제 1 단자 (11) 와 각 제 2 단자 (21) 사이에 수지층 (3) 을 배치하여 복수의 적층체 (4) 를 형성하고, 복수의 적층체 (4) 를 가열하면서, 복수의 적층체 (4) 를 동시에 적층체 (4) 의 적층 방향으로부터 협압한다.In the said process of obtaining the laminated body 4, the 1st terminal 11 of the some 1st electronic component 1 and the 2nd terminal 21 of the some 2nd electronic component 2 are opposingly arranged, respectively. The resin layer 3 is arrange | positioned between each 1st terminal 11 and each 2nd terminal 21, the some laminated body 4 is formed, and the some laminated body 4 is heated, The laminated body 4 is pinched simultaneously from the lamination direction of the laminated body 4.

다음으로, 본 실시형태의 전자 장치의 제조 방법에 대해 상세하게 설명한다. 처음에, 도 1 에 나타내는 바와 같이, 제 1 전자 부품 (1) 을 준비한다. 이 제 1 전자 부품 (1) 은, 예를 들어, 기판 (플렉시블 기판, 리지드 기판, 세라믹 기판 등), 반도체 칩, 반도체 소자 탑재 기판 등이다.Next, the manufacturing method of the electronic device of this embodiment is demonstrated in detail. First, as shown in FIG. 1, the 1st electronic component 1 is prepared. This 1st electronic component 1 is a board | substrate (a flexible board | substrate, a rigid board | substrate, a ceramic board | substrate, etc.), a semiconductor chip, a semiconductor element mounting board | substrate, etc., for example.

이 제 1 전자 부품 (1) 은 제 1 단자 (11) 를 갖고, 이 제 1 단자 (11) 는, 제 1 단자 본체 (111) 와, 제 1 단자 본체 (111) 표면에 형성된 땜납층 (112) 을 구비한다. 제 1 단자 본체 (111) 의 형상은, 특별히 한정되지 않고, 볼록상인 것이나, 오목상인 것을 들 수 있다. 또, 제 1 단자 본체 (111) 의 재질은, 특별히 제한되지 않고, 금, 구리, 니켈, 팔라듐, 알루미늄을 들 수 있다.This 1st electronic component 1 has the 1st terminal 11, The 1st terminal 11 has the 1st terminal main body 111 and the solder layer 112 formed in the 1st terminal main body 111 surface. ). The shape of the 1st terminal main body 111 is not specifically limited, A convex thing and a concave shape are mentioned. Moreover, the material of the 1st terminal main body 111 is not specifically limited, Gold, copper, nickel, palladium, aluminum is mentioned.

땜납층 (112) 의 재료는, 특별히 제한되지 않고, 주석, 은, 납, 아연, 비스무트, 인듐 및 구리로 이루어지는 군에서 선택되는 적어도 2 종 이상을 함유하는 합금 등을 들 수 있다. 이들 중, 주석, 은, 납, 아연, 구리로 이루어지는 군에서 선택되는 적어도 2 종 이상을 함유하는 합금이 바람직하다.The material of the solder layer 112 is not specifically limited, An alloy containing at least 2 or more types chosen from the group which consists of tin, silver, lead, zinc, bismuth, indium, and copper etc. is mentioned. Of these, alloys containing at least two or more selected from the group consisting of tin, silver, lead, zinc and copper are preferred.

땜납층 (112) 의 융점은, 110 ∼ 250 ℃, 바람직하게는 170 ∼ 230 ℃ 이다. 땜납층 (112) 은, 제 1 단자 본체 (111) 에 대해 땜납 도금된 것이어도 되고, 또, 제 1 단자 본체 (111) 에 대해 땜납 볼이나 땜납 페이스트를 배치하고, 땜납 범프 등으로 구성되는 것이어도 된다.Melting | fusing point of the solder layer 112 is 110-250 degreeC, Preferably it is 170-230 degreeC. The solder layer 112 may be solder plated with respect to the 1st terminal main body 111, and may arrange | position a solder ball or solder paste with respect to the 1st terminal main body 111, and consist of solder bumps, etc. You can do it.

여기서, 도 6 에 나타내는 바와 같이, 제 1 전자 부품 (1) 은, 복수 개 늘어서 형성되어 있다. 예를 들어, 제 1 전자 부품 (1) 이 기판인 경우에는, 각 기판끼리가 접속되어 1 장의 대형의 기판을 구성하고 있다. 또한, 대형의 기판에는, 도 6 의 점선으로 나타내는 바와 같이, 제 1 전자 부품 (1) 끼리를 분리하기 위한 절단 라인이 형성되어 있다.Here, as shown in FIG. 6, the 1st electronic component 1 is provided in multiple numbers. For example, when the 1st electronic component 1 is a board | substrate, each board | substrate is connected and comprises one large sized board | substrate. In addition, as shown by the dotted line of FIG. 6, the large sized board | substrate is provided with the cutting line for isolate | separating the 1st electronic component 1 comrades.

다음으로, 제 2 전자 부품 (2) 을 준비한다 (도 1 참조). 제 2 전자 부품 (2) 은, 예를 들어, 반도체 칩이나 반도체 소자 탑재 기판이다. 이 제 2 전자 부품 (2) 은 제 2 단자 (21) 를 갖는다.Next, the 2nd electronic component 2 is prepared (refer FIG. 1). The second electronic component 2 is, for example, a semiconductor chip or a semiconductor element mounting substrate. This second electronic component 2 has a second terminal 21.

제 2 단자 (21) 의 형상은, 특별히 제한되지 않고, 제 1 단자 (11) 에 대해 땜납 접합을 실시할 수 있는 형상이면 되고, 예를 들어, 볼록상인 것이나, 오목상인 것을 들 수 있다. 또, 제 2 단자 (21) 의 재질은, 특별히 제한되지 않고, 금, 동, 니켈, 팔라듐, 알루미늄 등을 들 수 있다.The shape of the second terminal 21 is not particularly limited, and may be any shape that can be solder-bonded to the first terminal 11, and examples thereof include a convex shape and a concave shape. Moreover, the material of the 2nd terminal 21 is not specifically limited, Gold, copper, nickel, palladium, aluminum, etc. are mentioned.

다음으로, 도 2 에 나타내는 바와 같이, 제 1 전자 부품 (1) 의 제 1 단자 (11) 와 제 2 전자 부품 (2) 의 제 2 단자 (21) 사이에 플럭스 활성 화합물과, 열경화성 수지를 함유하는 수지층 (3) 을 배치하고, 제 1 단자 (11) 와 제 2 단자 (21) 의 위치 맞춤을 실시한다.Next, as shown in FIG. 2, a flux active compound and a thermosetting resin are contained between the 1st terminal 11 of the 1st electronic component 1 and the 2nd terminal 21 of the 2nd electronic component 2. The resin layer 3 to be arrange | positioned is arrange | positioned, and the 1st terminal 11 and the 2nd terminal 21 are aligned.

여기서는, 복수의 제 1 전자 부품 (1) 과 복수의 제 2 전자 부품 (2) 의 위치 맞춤을 실시한다. 이 공정에서는, 제 1 전자 부품 (1) 과 제 2 전자 부품 (2) 사이에 수지층 (3) 이 배치된 복수의 적층체 (4) 가 얻어진다. 또한, 복수의 적층체 (4) 는, 예를 들어 면내 방향으로 배열된다.Here, positioning of the plurality of first electronic components 1 and the plurality of second electronic components 2 is performed. In this process, the some laminated body 4 in which the resin layer 3 was arrange | positioned between the 1st electronic component 1 and the 2nd electronic component 2 is obtained. In addition, the some laminated body 4 is arranged in an in-plane direction, for example.

여기서는, 제 2 전자 부품 (2) 의 제 2 단자 (21) 는, 수지층 (3) 에 파고들어, 제 1 단자 (11) 와 접촉하는 상태는 되어 있지 않다. 단, 제 1 단자 (11) 와 제 2 단자 (21) 사이에 수지가 개재하고 있는 상태에서, 제 1 단자 (11) 와 제 2 단자 (21) 가 접촉하고 있어도 된다.Here, the second terminal 21 of the second electronic component 2 penetrates into the resin layer 3 and is not in a state of being in contact with the first terminal 11. However, the first terminal 11 and the second terminal 21 may be in contact with each other while the resin is interposed between the first terminal 11 and the second terminal 21.

수지층 (3) 은, 제 1 전자 부품 (1) 과 제 2 전자 부품 (2) 의 간극을 매립할 수 있는 열경화성 수지를 함유하여 구성된다. 수지층 (3) 에 함유되는 열경화성 수지는, 예를 들어, 에폭시 수지, 옥세탄 수지, 페놀 수지, (메트)아크릴레이트 수지, 불포화 폴리에스테르 수지, 디알릴프탈레이트 수지, 말레이미드 수지 등을 사용할 수 있다. 이들은, 단독 또는 2 종 이상을 혼합하여 사용할 수 있다.The resin layer 3 contains the thermosetting resin which can fill the clearance gap between the 1st electronic component 1 and the 2nd electronic component 2, and is comprised. As the thermosetting resin contained in the resin layer 3, for example, an epoxy resin, an oxetane resin, a phenol resin, a (meth) acrylate resin, an unsaturated polyester resin, a diallyl phthalate resin, a maleimide resin, or the like can be used. have. These can be used individually or in mixture of 2 or more types.

그 중에서도, 경화성과 보존성, 경화물의 내열성, 내습성, 내약품성이 우수한 에폭시 수지가 바람직하게 사용된다. 수지층 (3) 의 100 ∼ 200 ℃ 에 있어서의 최저 용융 점도는, 바람직하게는 1 ∼ 1000 Pa·s, 특히 바람직하게는 1 ∼ 500 Pa·s 이다.Especially, the epoxy resin excellent in sclerosis | hardenability, storage property, the heat resistance of a hardened | cured material, moisture resistance, and chemical resistance is used preferably. The minimum melt viscosity in 100-200 degreeC of the resin layer 3 becomes like this. Preferably it is 1-1000 Pa.s, Especially preferably, it is 1-500 Pa.s.

수지층 (3) 의 100 ∼ 200 ℃ 에 있어서의 최저 용융 점도가 상기 범위에 있음으로써, 경화물 중에 공극 (보이드) 이 잘 발생하지 않게 된다. 최저 용융 점도는, 예를 들어, 점탄성 측정 장치인 레오미터를 사용하여, 필름 상태의 샘플에 10 ℃/분의 승온 속도로, 주파수 1 ㎐ 의 미끄럼 전단을 부여하여 측정된다.Since the minimum melt viscosity in 100-200 degreeC of the resin layer 3 exists in the said range, a space | gap (void) will hardly arise in hardened | cured material. The minimum melt viscosity is measured by applying a slip shear with a frequency of 1 Hz to a sample in a film state at a temperature increase rate of 10 ° C / min using a rheometer which is a viscoelasticity measuring device, for example.

수지층 (3) 은, 땜납 접합시에, 땜납층 (112) 의 표면의 산화 피막을 제거하는 작용을 갖는 수지층이다. 수지층 (3) 이, 플럭스 작용을 가짐으로써, 땜납층 (112) 의 표면을 덮고 있는 산화 피막이 제거되므로, 땜납 접합을 실시할 수 있다.The resin layer 3 is a resin layer which has the effect | action which removes the oxide film of the surface of the solder layer 112 at the time of solder bonding. When the resin layer 3 has a flux effect, the oxide film covering the surface of the solder layer 112 is removed, and solder bonding can be performed.

수지층 (3) 이 플럭스 작용을 갖기 위해서는, 수지층 (3) 이, 플럭스 활성 화합물을 함유할 필요가 있다. 수지층 (3) 에 함유되는 플럭스 활성 화합물로는, 땜납 접합에 사용되는 것이면, 특별히 제한되지 않지만, 카르복실기, 페놀 수산기 중 어느 것, 카르복실기, 페놀 수산기의 양방을 구비하는 화합물 등이 바람직하다.In order for the resin layer 3 to have a flux action, it is necessary for the resin layer 3 to contain a flux active compound. The flux-active compound contained in the resin layer 3 is not particularly limited as long as it is used for solder bonding, but is preferably a compound having both a carboxyl group, a phenol hydroxyl group, a carboxyl group, and a phenol hydroxyl group.

수지층 (3) 중의 플럭스 활성 화합물의 배합량은, 1 ∼ 30 중량％ 가 바람직하고, 3 ∼ 20 중량％ 가 특히 바람직하다. 수지층 (3) 중의 플럭스 활성 화합물의 배합량이, 상기 범위임으로써, 수지층 (3) 의 플럭스 활성을 향상시킬 수 있음과 함께, 수지층 (3) 중에, 열경화성 수지와 미반응 플럭스 활성 화합물이 잔존하는 것이 방지된다.1-30 weight% is preferable and, as for the compounding quantity of the flux active compound in the resin layer 3, 3-20 weight% is especially preferable. When the compounding quantity of the flux active compound in the resin layer 3 is the said range, the flux activity of the resin layer 3 can be improved, and in the resin layer 3, a thermosetting resin and an unreacted flux active compound are Remaining is prevented.

또한, 미반응 플럭스 활성 화합물이 잔존하면, 마이그레이션이 발생할 가능성이 있다. 또, 열경화성 수지의 경화제로서 작용하는 화합물 중에는, 플럭스 작용도 갖는 화합물이 있다 (이하, 이와 같은 화합물을, 플럭스 활성 경화제라고도 기재한다).In addition, if an unreacted flux active compound remains, migration may occur. Moreover, among the compounds which act as a hardening | curing agent of a thermosetting resin, there exists a compound which also has a flux action (Hereinafter, such a compound is also described as a flux active hardening | curing agent).

예를 들어, 에폭시 수지의 경화제로서 작용하는 페놀 노볼락 수지, 크레졸 노볼락 수지, 지방족 디카르복실산, 방향족 디카르복실산 등은, 플럭스 작용도 갖고 있다.For example, the phenol novolak resin, cresol novolak resin, aliphatic dicarboxylic acid, aromatic dicarboxylic acid, etc., which act as a curing agent for epoxy resins also have a flux action.

이와 같은, 플럭스 활성 화합물로서도 작용하고, 열경화성 수지의 경화제로서도 작용하는 플럭스 활성 경화제를, 열경화성 수지의 경화제로서 함유하는 수지층 (3) 은, 플럭스 작용을 갖는 수지층 (3) 이 된다.The resin layer 3 which contains a flux active hardening | curing agent which acts as such a flux active compound and also acts as a hardening | curing agent of a thermosetting resin as a hardening | curing agent of a thermosetting resin becomes the resin layer 3 which has a flux effect.

또한, 카르복실기를 구비하는 플럭스 활성 화합물이란, 분자 중에 카르복실기가 1 개 이상 존재하는 것을 말하고, 액상이어도 되고, 고체여도 된다. 또, 페놀성 수산기를 구비하는 플럭스 활성 화합물이란, 분자 중에 페놀성 수산기가 1 개 이상 존재하는 것을 말하고, 액상이어도 되고, 고체여도 된다.In addition, the flux active compound which has a carboxyl group means that one or more carboxyl groups exist in a molecule | numerator, and a liquid may be sufficient and solid may be sufficient as it. Moreover, the flux active compound provided with a phenolic hydroxyl group means that one or more phenolic hydroxyl groups exist in a molecule | numerator, and a liquid may be sufficient as it and a solid may be sufficient as it.

또, 카르복실기 및 페놀성 수산기를 구비하는 플럭스 활성 화합물이란, 분자 중에 카르복실기 및 페놀성 수산기가 각각 하나 이상 존재하는 것을 말하고, 액상이어도 되고, 고체여도 된다.Moreover, the flux active compound which has a carboxyl group and phenolic hydroxyl group means that one or more carboxyl group and phenolic hydroxyl group exist in a molecule | numerator, respectively, and a liquid may be sufficient as it.

이들 중, 카르복실기를 구비하는 플럭스 활성 화합물로는, 지방족 산무수물, 지환식 산무수물, 방향족 산무수물, 지방족 카르복실산, 방향족 카르복실산 등을 들 수 있다.Among these, as a flux active compound which has a carboxyl group, an aliphatic acid anhydride, an alicyclic acid anhydride, an aromatic acid anhydride, an aliphatic carboxylic acid, an aromatic carboxylic acid, etc. are mentioned.

카르복실기를 구비하는 플럭스 활성 화합물에 관련된 지방족 산무수물로는, 무수 숙신산, 폴리아디프산 무수물, 폴리아젤라인산 무수물, 폴리세바스산 무수물 등을 들 수 있다.Examples of the aliphatic acid anhydride related to the flux-active compound having a carboxyl group include succinic anhydride, polyadipic anhydride, polyazelanic anhydride, and poly sebacic anhydride.

카르복실기를 구비하는 플럭스 활성 화합물에 관련된 지환식 산무수물로는, 메틸테트라하이드로 무수 프탈산, 메틸헥사하이드로 무수 프탈산, 무수 메틸하이믹산, 헥사하이드로 무수 프탈산, 테트라하이드로 무수 프탈산, 트리알킬테트라하이드로 무수 프탈산, 메틸시클로헥센디카르복실산 무수물 등을 들 수 있다.Examples of the alicyclic acid anhydride related to the flux-active compound having a carboxyl group include methyltetrahydro phthalic anhydride, methylhexahydrophthalic anhydride, methylhydric anhydride, hexahydro phthalic anhydride, tetrahydro phthalic anhydride, trialkyltetrahydro phthalic anhydride, Methyl cyclohexene dicarboxylic acid anhydride etc. are mentioned.

카르복실기를 구비하는 플럭스 활성 화합물에 관련된 방향족 산무수물로는, 무수 프탈산, 무수 트리멜리트산, 무수 피로멜리트산, 벤조페논테트라카르복실산 무수물, 에틸렌글리콜비스트리멜리테이트, 글리세롤트리스트리멜리테이트 등을 들 수 있다.Examples of the aromatic acid anhydride related to the flux active compound having a carboxyl group include phthalic anhydride, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic anhydride, ethylene glycol bistrimellitate, glycerol tristrimellitate, and the like. Can be mentioned.

카르복실기를 구비하는 플럭스 활성 화합물에 관련된 지방족 카르복실산으로는, 하기 일반식 (1) 로 나타내는 화합물이나, 포름산, 아세트산, 프로피온산, 부티르산, 발레르산, 피발산카프로산, 카프르산, 라우르산, 미리스트산, 팔미트산, 스테아르산, 아크릴산, 메타크릴산, 크로톤산, 올레산, 푸마르산, 말레산, 옥살산, 말론산, 호박산 등을 들 수 있다.Examples of the aliphatic carboxylic acid related to the flux-active compound having a carboxyl group include compounds represented by the following general formula (1), formic acid, acetic acid, propionic acid, butyric acid, valeric acid, pivalic acid caproic acid, capric acid, and lauric acid. , Myristic acid, palmitic acid, stearic acid, acrylic acid, methacrylic acid, crotonic acid, oleic acid, fumaric acid, maleic acid, oxalic acid, malonic acid, succinic acid and the like.

[화학식 1] [Formula 1]

HOOC-(CH2)n-COOH (1)  HOOC- (CH2) n-COOH (1)

식 (1) 중, n 은 20 이하의 자연수를 나타낸다.In formula (1), n represents the natural number of 20 or less.

카르복실기를 구비하는 플럭스 활성 화합물에 관련된 방향족 카르복실산으로는, 벤조산, 프탈산, 이소프탈산, 테레프탈산, 헤미멜리트산, 트리멜리트산, 트리메스산, 멜로판산, 프레니트산, 피로멜리트산, 멜리트산, 트리일산, 자일릴산, 헤멜리트산, 메시틸렌산, 프레이니틸산, 톨루일산, 계피산, 살리실산, 2,3-디하이드록시벤조산, 2,4-디하이드록시벤조산, 겐티신산(2,5-디하이드록시벤조산), 2,6-디하이드록시벤조산, 3,5-디하이드록시벤조산, 침식자산(3,4,5-트리하이드록시벤조산), 1,4-디하이드록시-2-나프토산, 3,5-디하이드록시-2-나프토산 등의 나프토산 유도체, 페놀프탈린, 디페놀산 등을 들 수 있다.Examples of the aromatic carboxylic acid related to the flux active compound having a carboxyl group include benzoic acid, phthalic acid, isophthalic acid, terephthalic acid, hemimetic acid, trimellitic acid, trimesic acid, melanoic acid, prenitic acid, pyromellitic acid and melitric acid. , Triylic acid, xyllic acid, hemelitic acid, mesitylene acid, preinitil acid, toluic acid, cinnamic acid, salicylic acid, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisinic acid (2,5 Dihydroxybenzoic acid), 2,6-dihydroxybenzoic acid, 3,5-dihydroxybenzoic acid, eroded assets (3,4,5-trihydroxybenzoic acid), 1,4-dihydroxy-2- Naphthoic acid derivatives such as naphthoic acid and 3,5-dihydroxy-2-naphthoic acid, phenolphthalin, diphenolic acid, and the like.

이들의 카르복실기를 구비하는 플럭스 활성 화합물 중, 플럭스 활성 화합물이 갖는 활성도, 수지층의 경화시에 있어서의 아웃 가스의 발생량, 및 경화 후의 수지층의 탄성률이나 유리 전이 온도 등의 밸런스가 양호한 점에서, 상기 일반식 (1) 로 나타내는 화합물이 바람직하다.In the flux active compound which has these carboxyl groups, since the balance which the activity which a flux active compound has, the amount of outgassing at the time of hardening of a resin layer, and the elasticity modulus and glass transition temperature of the resin layer after hardening are favorable, The compound represented by the said General formula (1) is preferable.

그리고, 상기 일반식 (1) 로 나타내는 화합물 중, 식 (1) 중의 n 이 3 ∼ 10 인 화합물이, 경화 후의 수지층에 있어서의 탄성률이 증가되는 것을 억제할 수 있음과 함께, 제 1 전자 부품 (1) 과 제 2 전자 부품 (2) 의 접착성을 향상시킬 수 있는 점에서 특히 바람직하다.And in the compound represented by the said General formula (1), the compound whose n in Formula (1) is 3-10 can suppress that the elasticity modulus in the resin layer after hardening increases, and it is a 1st electronic component It is especially preferable at the point which can improve the adhesiveness of (1) and the 2nd electronic component 2.

상기 일반식 (1) 로 나타내는 화합물 중, 식 (1) 중의 n 이 3 ∼ 10 인 화합물로는, 예를 들어, n=3 의 글루타르산 (HOOC-(CH2)3-COOH), n=4 의 아디프산 (HOOC-(CH2)4-COOH), n=5 의 피멜린산 (HOOC-(CH2)5-COOH), n=8 의 세바스산 (HOOC-(CH2)8-COOH) 및 n=10 의 HOOC-(CH2)10-COOH 등을 들 수 있다.In the compound represented by the said General formula (1), as a compound whose n in Formula (1) is 3-10, for example, n = 3 glutaric acid (HOOC- (CH2) 3-COOH), n = 4 adipic acid (HOOC- (CH2) 4-COOH), n = 5 pimelic acid (HOOC- (CH2) 5-COOH), n = 8 sebacic acid (HOOC- (CH2) 8-COOH) And HOOC- (CH2) 10-COOH with n = 10.

페놀성 수산기를 구비하는 플럭스 활성 화합물로는, 페놀류를 들 수 있고, 구체적으로는, 예를 들어, 페놀, o-크레졸, 2,6-자일레놀, p-크레졸, m-크레졸, o-에틸페놀, 2,4-자일레놀, 2,5-자일레놀, m-에틸페놀, 2,3-자일레놀, 메디톨, 3,5-자일레놀, p-터셔리부틸페놀, 카테콜, p-터셔리아밀페놀, 레조르시놀, p-옥틸페놀, p-페닐페놀, 비스페놀 A, 비스페놀 F, 비스페놀 AF, 비페놀, 디알릴비스페놀 F, 디알릴비스페놀 A, 트리스페놀, 테트라키스페놀 등의 페놀성 수산기를 함유하는 모노머류, 페놀 노볼락 수지, o-크레졸 노볼락 수지, 비스페놀 F 노볼락 수지, 비스페놀 A 노볼락 수지 등을 들 수 있다.Examples of the flux active compound having a phenolic hydroxyl group include phenols, and specifically, for example, phenol, o-cresol, 2,6-xylenol, p-cresol, m-cresol, and o- Ethylphenol, 2,4-xylenol, 2,5-xylenol, m-ethylphenol, 2,3-xylenol, methitol, 3,5-xylenol, p-tertiarybutylphenol, Catechol, p-tertylylphenol, resorcinol, p-octylphenol, p-phenylphenol, bisphenol A, bisphenol F, bisphenol AF, biphenol, diallyl bisphenol F, diallyl bisphenol A, trisphenol, tetra Monomers containing phenolic hydroxyl groups, such as kisphenol, a phenol novolak resin, o-cresol novolak resin, bisphenol F novolak resin, bisphenol A novolak resin, etc. are mentioned.

상기 서술한 바와 같은 카르복실기, 또는, 페놀 수산기 중 어느 것, 또는, 카르복실기 및 페놀 수산기의 양방을 구비하는 화합물은, 에폭시 수지와 같은 열경화성 수지와의 반응으로 삼차원적으로 받아들여진다.The compound which has both the carboxyl group mentioned above or the phenol hydroxyl group, or both of a carboxyl group and a phenol hydroxyl group is taken in three-dimensionally by reaction with thermosetting resins, such as an epoxy resin.

그 때문에, 경화 후의 에폭시 수지의 삼차원적인 네트워크의 형성을 향상시킨다는 관점에서는, 플럭스 활성 화합물로는, 플럭스 작용을 갖고, 또한, 에폭시 수지의 경화제로서 작용하는 플럭스 활성 경화제가 바람직하다.Therefore, from the viewpoint of improving the formation of a three-dimensional network of the epoxy resin after curing, as the flux active compound, a flux active curing agent which has a flux action and also acts as a curing agent of the epoxy resin is preferable.

플럭스 활성 경화제로는, 예를 들어, 1 분자 중에, 에폭시 수지에 부가할 수 있는 2 개 이상의 페놀성 수산기와, 플럭스 작용 (환원 작용) 을 나타내는 방향족에 직접 결합한 1 개 이상의 카르복실기를 구비하는 화합물을 들 수 있다.As a flux active hardening | curing agent, the compound which has the 2 or more phenolic hydroxyl group which can be added to an epoxy resin, and the 1 or more carboxyl group which directly couple | bonded with the aromaticity which shows a flux action (reduction action) is contained in 1 molecule, for example. Can be mentioned.

이와 같은 플럭스 활성 경화제로는, 2,3-디하이드록시벤조산, 2,4-디하이드록시벤조산, 겐티신산(2,5-디하이드록시벤조산), 2,6-디하이드록시벤조산, 3,4-디하이드록시벤조산, 갈산(3,4,5-트리하이드록시벤조산) 등의 벤조산 유도체 ; 1,4-디하이드록시-2-나프토산, 3,5-디하이드록시-2-나프토산, 3,7-디하이드록시-2-나프토산 등의 나프토산 유도체 ; 페놀프탈린 ; 및 디페놀산 등을 들 수 있고, 이들은 1 종 단독, 또는 2 종 이상을 조합해도 된다.As such flux active hardening | curing agent, 2, 3- dihydroxy benzoic acid, 2, 4- dihydroxy benzoic acid, gentisine acid (2, 5- dihydroxy benzoic acid), 2, 6- dihydroxy benzoic acid, 3, Benzoic acid derivatives such as 4-dihydroxybenzoic acid and gallic acid (3,4,5-trihydroxybenzoic acid); Naphthoic acid derivatives such as 1,4-dihydroxy-2-naphthoic acid, 3,5-dihydroxy-2-naphthoic acid, and 3,7-dihydroxy-2-naphthoic acid; Phenolphthalin; And diphenolic acid. These may be used alone or in combination of two or more.

그 중에서도, 제 1 단자 (11) 및 제 2 단자 (21) 의 접합을 양호한 것으로 하기 위해서는, 페놀프탈린을 사용하는 것이 특히 바람직하다. 페놀프탈린을 사용함으로써, 땜납층 (112) 의 표면의 산화물을 제거한 후, 에폭시 수지를 경화할 수 있게 되는 것으로 추측된다.Especially, in order to make the joining of the 1st terminal 11 and the 2nd terminal 21 favorable, it is especially preferable to use phenolphthalin. By using phenolphthalin, it is estimated that after removing the oxide of the surface of the solder layer 112, an epoxy resin can be hardened.

따라서, 땜납층 (112) 표면의 산화물이 제거되지 않은 채, 에폭시 수지가 경화되는 것을 억제할 수 있고, 제 1 단자 (11) 및 제 2 단자 (21) 의 땜납 접합을 양호한 것으로 할 수 있다.Therefore, hardening of an epoxy resin can be suppressed, without removing the oxide on the surface of the solder layer 112, and the solder joint of the 1st terminal 11 and the 2nd terminal 21 can be made favorable.

또, 수지층 (3) 중, 플럭스 활성 경화제의 배합량은, 1 ∼ 30 중량％ 가 바람직하고, 3 ∼ 20 중량％ 가 특히 바람직하다. 수지층 (3) 중의 플럭스 활성 경화제의 배합량이, 상기 범위임으로써, 수지층의 플럭스 활성을 향상시킬 수 있음과 함께, 수지층 중에, 열경화성 수지와 미반응 플럭스 활성 경화제가 잔존하는 것이 방지된다.Moreover, 1-30 weight% is preferable and, as for the compounding quantity of a flux active hardening | curing agent in the resin layer 3, 3-20 weight% is especially preferable. When the compounding quantity of the flux active hardening | curing agent in the resin layer 3 is the said range, the flux activity of a resin layer can be improved, and it is prevented that a thermosetting resin and an unreacted flux active hardening | curing agent remain in a resin layer.

또한, 미반응 플럭스 활성 경화제가 잔존하면, 마이그레이션이 발생한다. 또, 수지층 (3) 은, 무기 충전재를 함유하고 있어도 된다. 수지층 (3) 중에 무기 충전재를 함유시킴으로써, 수지층 (3) 의 최저 용융 점도를 높여, 제 1 단자 (11) 및 제 2 단자 (21) 간에 간극이 형성되는 것을 억제할 수 있다.In addition, when an unreacted flux active hardener remains, migration occurs. Moreover, the resin layer 3 may contain the inorganic filler. By containing an inorganic filler in the resin layer 3, the minimum melt viscosity of the resin layer 3 can be raised and it can suppress that a clearance gap is formed between the 1st terminal 11 and the 2nd terminal 21. FIG.

또한, 수지층 (3) 의 최저 용융 점도가 매우 낮은 경우에는, 수지층 (3) 의 유동성이 매우 높아지고, 제 1 단자 (11) 와 제 2 단자 (21) 사이에, 수지층 (3) 이 비집고 들어가, 제 1 단자 (11) 와 제 2 단자 (21) 가 이간되는 경우가 있다.Moreover, when the minimum melt viscosity of the resin layer 3 is very low, the fluidity | liquidity of the resin layer 3 will become very high, and the resin layer 3 will be between the 1st terminal 11 and the 2nd terminal 21. In some cases, the first terminal 11 and the second terminal 21 may be spaced apart from each other.

여기서, 무기 충전재로는, 실리카나, 알루미나 등을 들 수 있다. 또한, 수지층 (3) 은, 경화 촉매를 함유하고 있어도 된다. 경화 촉매는, 수지층 (3) 중의 열경화성 수지의 종류에 따라 적절히 선택할 수 있지만, 예를 들어, 도막 성형성 향상의 관점에서 이미다졸 화합물을 사용할 수 있다.Here, silica, alumina, etc. are mentioned as an inorganic filler. In addition, the resin layer 3 may contain the hardening catalyst. Although a curing catalyst can be suitably selected according to the kind of thermosetting resin in the resin layer 3, For example, an imidazole compound can be used from a viewpoint of coating-film moldability improvement.

이미다졸 화합물로서 2-페닐하이드록시이미다졸, 2-페닐-4-메틸하이드록시이미다졸 등을 들 수 있다.2-phenylhydroxyimidazole, 2-phenyl-4-methylhydroxyimidazole, etc. are mentioned as an imidazole compound.

또, 경화 촉매의 배합비는, 수지층 (3) 의 구성 성분의 합계를 100 으로 했을 때에, 예를 들어 0.01 중량％ 이상 5 중량％ 이하로 한다. 경화 촉매의 배합비를 0.01 중량％ 이상으로 함으로써, 경화 촉매로서의 기능을 더욱 효과적으로 발휘시켜, 수지층 (3) 의 경화성을 향상시킬 수 있다. 또, 경화 촉매의 배합비를 5 중량％ 이하로 함으로써, 수지층 (3) 의 보존성을 더욱 향상시킬 수 있다.In addition, the compounding ratio of a curing catalyst is made into 0.01 weight% or more and 5 weight% or less, for example, when making the sum total of the structural component of the resin layer 3 into 100. By setting the blending ratio of the curing catalyst to 0.01% by weight or more, the function as the curing catalyst can be more effectively exhibited, and the curability of the resin layer 3 can be improved. Moreover, the storage property of the resin layer 3 can further be improved by making the compounding ratio of a curing catalyst into 5 weight% or less.

제 1 전자 부품 (1) 과 제 2 전자 부품 (2) 사이에 수지층 (3) 을 배치하는 방법으로는, 예를 들어, As a method of disposing the resin layer 3 between the first electronic component 1 and the second electronic component 2, for example,

(1) 플럭스 활성 화합물을 함유하는 수지 조성물을 필름상으로 성형한 수지 필름을 준비하고, 이 수지 필름을, 제 1 전자 부품 (1), 또는, 제 2 전자 부품 (2) 에 라미네이트하는 방법,  (1) A method of preparing a resin film obtained by molding a resin composition containing a flux active compound into a film form, and laminating the resin film on the first electronic component 1 or the second electronic component 2,

(2) 플럭스 활성 화합물을 함유하는 액상의 수지 조성물을 준비하고, 이 액상의 수지 조성물을, 제 1 전자 부품 (1), 또는, 제 2 전자 부품 (2) 의 표면에 도포하는 방법,  (2) A method of preparing a liquid resin composition containing a flux active compound and applying the liquid resin composition to the surface of the first electronic component 1 or the second electronic component 2,

(3) 플럭스 활성 화합물을 함유하는 수지 조성물이 용제에 용해, 또는, 분산되어 있는 수지 바니시를 준비하고, 이 수지 바니시를, 제 1 전자 부품 (1), 또는, 제 2 전자 부품 (2) 의 표면에 도포하고, 이어서, 수지 바니시 중의 용제를 휘발시키는 방법을 들 수 있다. 또한, 방법 (2) 에 관련된 액상의 수지 조성물은 용제를 함유하지 않는다. (3) A resin varnish in which a resin composition containing a flux active compound is dissolved or dispersed in a solvent is prepared, and the resin varnish is prepared by the first electronic component 1 or the second electronic component 2. The method of apply | coating to the surface and then volatilizing the solvent in a resin varnish is mentioned. In addition, the liquid resin composition which concerns on the method (2) does not contain a solvent.

여기서, 도 6 에 나타내는 바와 같이, 수지층 (3) 은 복수 늘어서 있고, 복수의 제 1 전자 부품 (1) 상에 걸치는 1 장의 수지 시트를 구성하고 있다. 보다 상세하게 설명하면, 수지 시트는 복수의 수지층 (3) 과 수지층 (3) 끼리를 연결하고 있는 연결 부분으로 구성되고, 수지층 (3) 끼리는 연결 부분을 개재하여 늘어서 있다.Here, as shown in FIG. 6, the resin layer 3 is arranged in multiple numbers, and comprises the resin sheet of 1 sheet on the some 1st electronic component 1. As shown in FIG. In more detail, the resin sheet is comprised from the connection part which connected the some resin layer 3 and the resin layer 3 comrades, and the resin layer 3 comrades is lined through the connection part.

다음으로, 복수의 적층체 (4) 를 가열하면서, 적층체 (4) 의 적층 방향을 따라 협압하고, 도 3 에 나타내는 바와 같이, 제 1 단자 (11) 와 제 2 단자 (21) 가 접촉하도록 제 2 단자 (21) 를 수지층 (3) 에 함몰시킨다.Next, while heating the several laminated body 4, it pinches along the lamination | stacking direction of the laminated body 4, so that the 1st terminal 11 and the 2nd terminal 21 may contact as shown in FIG. The second terminal 21 is recessed in the resin layer 3.

또한, 본 공정도에서는, 제 1 단자 (11) 의 땜납층 (112) 에 의해, 제 1 단자 (11) 와 제 2 단자 (21) 가 땜납 접합되는 경우는 없다. 이 공정에서는, 도 4 ∼ 도 5 에 나타내는 장치 (5) 를 사용한다.In the present process diagram, the first terminal 11 and the second terminal 21 are not solder-joined by the solder layer 112 of the first terminal 11. In this process, the apparatus 5 shown in FIGS. 4-5 is used.

장치 (5) 는, 표면에 땜납층 (112) 을 갖는 제 1 단자 (11) 를 갖는 제 1 전자 부품 (1) 의 제 1 단자 (11) 와, 이 제 1 전자 부품 (1) 의 제 1 단자 (11) 에 접합되는 제 2 단자 (21) 를 갖는 제 2 전자 부품 (2) 의 제 2 단자 (21) 사이에, 플럭스 활성 화합물과, 열경화성 수지를 함유하는 수지층 (3) 을 배치하여, 적층체 (4) 를 형성한 후, 제 1 단자 (11) 와 제 2 단자 (21) 를 접촉시키기 위한 장치이다.The apparatus 5 has the 1st terminal 11 of the 1st electronic component 1 which has the 1st terminal 11 which has the solder layer 112 on the surface, and the 1st of this 1st electronic component 1 Between the 2nd terminal 21 of the 2nd electronic component 2 which has the 2nd terminal 21 joined by the terminal 11, the resin layer 3 containing a flux active compound and a thermosetting resin is arrange | positioned, After the laminated body 4 is formed, it is an apparatus for making the 1st terminal 11 and the 2nd terminal 21 contact.

이 장치 (5) 는, 복수의 적층체 (4) 를 동시에 협압하는 협압 부재인 지그 (53) 를 구비한다. 보다 상세하게 설명하면, 장치 (5) 는, 내부에 복수의 적층체 (4) 가 배치되는 노 (가열로) (51) 와, 노 (51) 내에 배치되는 프레스 부재인 상열판 (521), 하열판 (522) 과 지그 (53) 를 구비한다.This apparatus 5 is provided with the jig 53 which is a pinching member which pinches a some laminated body 4 simultaneously. In more detail, the apparatus 5 is the furnace (heating furnace) 51 in which the several laminated body 4 is arrange | positioned inside, the heat insulation plate 521 which is a press member arrange | positioned in the furnace 51, The lower plate 522 and the jig 53 are provided.

노 (51) 는, 상형(上型) (511) 과 하형(下型) (512) 으로 구성되고, 상형 (511) 과 하형 (512) 으로 구성되는 공간 내에 상열판 (521), 하열판 (522) 이 배치된다. 상열판 (521), 하열판 (522) 은 대향 배치되고, 상열판 (521) 과 하열판 (522) 사이에는, 지그 (53) 및 복수의 적층체 (4) 가 배치된다. 1 쌍의 열판 (521, 522) 은 땜납층 (112) 의 융점 미만의 온도가 되고 있다.The furnace 51 is comprised of the upper mold | type 511 and the lower mold | type 512, and the upper plate 521 and the lower plate (in the space comprised by the upper mold | type 511 and the lower mold | type 512) 522 is disposed. The upper heat plate 521 and the lower heat plate 522 are disposed to face each other, and the jig 53 and the plurality of laminated bodies 4 are disposed between the upper heat plate 521 and the lower heat plate 522. The pair of hot plates 521 and 522 is at a temperature below the melting point of the solder layer 112.

지그 (53) 는, 홈이 형성된 상측 가압 부재 (531) 및 평판상의 하측 가압 부재 (532) 를 구비한다. 상측 가압 부재 (531) 및 하측 가압 부재 (532) 간에 복수의 적층체 (4) 가 배치된다. 상측 가압 부재 (531) 는, 판상이고, 평면 사각 형상이다.The jig 53 is provided with the upper press member 531 in which the groove was formed, and the lower press member 532 of flat form. A plurality of laminates 4 are disposed between the upper pressing member 531 and the lower pressing member 532. The upper press member 531 is plate-shaped and has a flat rectangular shape.

상측 가압 부재 (531) 에는, 도 6, 7 에도 나타내는 바와 같이, 복수의 홈 (531A) 이 형성되어 있고, 일부의 홈 (531A) 끼리가 교차하고 있다. 본 실시형태에서는, 홈 (531A) 이 격자상으로 형성되어 있다.6 and 7, the plurality of grooves 531A are formed in the upper pressing member 531, and some of the grooves 531A intersect with each other. In the present embodiment, the grooves 531A are formed in a lattice shape.

홈 (531A) 으로 구획된 영역 (531B) 이 적층체 (4) 의 제 2 전자 부품 (2) 에 맞닿는다. 1 개의 영역 (531B) 에 대해 1 개의 적층체 (4) 의 제 2 전자 부품 (2) 이 맞닿는다. 하측 가압 부재 (532) 는, 평면 사각 형상이고, 하측 가압 부재 (532) 에는 홈은 형성되지 않고, 표면이 평탄한 판재로 구성되어 있다.The region 531B partitioned by the grooves 531A abuts on the second electronic component 2 of the laminate 4. The second electronic component 2 of one laminate 4 abuts against one region 531B. The lower pressurizing member 532 has a flat rectangular shape, and a groove is not formed in the lower pressurizing member 532, and is made of a plate material having a flat surface.

하측 가압 부재 (532) 와, 상측 가압 부재 (531) 의 홈 (531A) 이 형성된 면은 대향하고 있다. 하측 가압 부재 (532) 에는, 적층체 (4) 의 제 1 전자 부품 (1) 이 맞닿는다. 여기서, 하측 가압 부재 (532), 상측 가압 부재 (531) 의 재료로는 특별히 제한되지 않고, 금속판, 세라믹판 등을 들 수 있다.The lower pressurizing member 532 and the surface in which the groove 531A of the upper pressurizing member 531 is formed oppose. The first electronic component 1 of the laminate 4 abuts against the lower pressing member 532. Here, the material of the lower pressing member 532 and the upper pressing member 531 is not particularly limited, and a metal plate, a ceramic plate, and the like can be given.

금속판으로는, 예를 들어, 스테인리스판, 티탄판, 납판을 들 수 있다. 또, 세라믹판으로는, 유리판, 알루미나판, 질화규소판, 지르코니아판을 들 수 있다. 단, 열전도성이 양호한 것이 바람직하다.As a metal plate, a stainless plate, a titanium plate, and a lead plate are mentioned, for example. Moreover, as a ceramic plate, a glass plate, an alumina plate, a silicon nitride plate, a zirconia plate is mentioned. However, it is preferable that the thermal conductivity is good.

다음으로, 장치 (5) 의 사용 방법에 대해 설명한다. 처음에, 노 (51) 밖에서, 도 6 에 나타내는 바와 같이, 지그 (53) 의 상측 가압 부재 (531) 및 하측 가압 부재 (532) 간에 복수의 적층체 (4) 를 배치하고, 상측 가압 부재 (531) 및 하측 가압 부재 (532) 로 복수의 적층체 (4) 를 사이에 끼운다.Next, the usage method of the apparatus 5 is demonstrated. First, outside the furnace 51, as shown in FIG. 6, the some laminated body 4 is arrange | positioned between the upper pressurizing member 531 and the lower pressurizing member 532 of the jig 53, and the upper pressurizing member ( 531 and the lower press member 532 sandwich the plurality of laminates 4 therebetween.

이 때, 도 6 에 나타내는 바와 같이, 홈 (531A) 의 폭 (W1) (홈 (531A) 의 연장 방향과 직교하는 방향의 길이) 은, 인접하는 적층체 (4) 간의 간극 (W2) 보다 크다. 바꾸어 말하면, 홈 (531A) 으로 구획된 상기 영역 (531B) 에 맞닿는 제 2 전자 부품 (2) 의 단면 (端面) (측면) 이, 홈 (531A) 의 측면 (531C) 보다 홈 (531A) 내측으로 돌출되어 있다. 상기 서술한 바와 같이 상측 가압 부재 (531) 의 폭 (W1) 의 홈 (531A) 으로 구획된 영역 (531B) 은, 제 2 전자 부품 (2) 의 제 2 단자 (21) 보다 외측에 위치하는 형상으로 형성되어 있다.At this time, as shown in FIG. 6, the width W1 of the groove 531A (the length in the direction orthogonal to the extending direction of the groove 531A) is larger than the gap W2 between the adjacent laminates 4. . In other words, the end face (side surface) of the second electronic component 2 which abuts on the region 531B partitioned by the groove 531A is located inside the groove 531A than the side surface 531C of the groove 531A. It protrudes. As described above, the region 531B partitioned by the groove 531A of the width W1 of the upper pressing member 531 is located outside the second terminal 21 of the second electronic component 2. It is formed.

또, 인접하는 적층체 (4) 중, 수지층 (3) 끼리는 늘어서 형성되어 있지만, 인접하는 제 2 전자 부품 (2) 간에는 공극이 형성되어 있기 때문에, 상기 공극으로부터 수지층 (3) 이 늘어섬으로써 구성되는 수지 시트의 일부가 노출되게 된다. 수지 시트의 노출 부분은 홈 (531A) 과 대향한다.Moreover, although the resin layers 3 are formed side by side among the adjacent laminated bodies 4, since the space | gap is formed between the adjacent 2nd electronic components 2, the resin layer 3 stretches from the said space | gap. A part of the resin sheet comprised by this is exposed. The exposed portion of the resin sheet opposes the groove 531A.

도 6 은, 상측 가압 부재 (531) 및 하측 가압 부재 (532) 로 복수의 적층체 (4) 를 사이에 끼운 상태를 나타내는 도면이다. 다음으로, 노 (51) 내에 지그 (53) 및 복수의 적층체 (4) 를 반송한다. 노 (51) 내에 지그 (53) 및 복수의 적층체 (4) 를 반송할 때에는, 반송 필름 등을 사용해도 된다.FIG. 6: is a figure which shows the state which pinched | interposed the some laminated body 4 with the upper press member 531 and the lower press member 532. FIG. Next, the jig 53 and the plurality of laminated bodies 4 are conveyed in the furnace 51. When conveying the jig 53 and the some laminated body 4 in the furnace 51, you may use a conveyance film.

여기서, 미리 상열판 (521), 하열판 (522) 은 가열된 상태로 되어 있다. 그 후, 상형 (511) 을 하형 (512) 측으로 이동시켜, 상형 (511) 및 하형 (512) 간의 간극을 닫는다. 지그 (53) 의 하측 가압 부재 (532) 는, 하열판 (522) 이 맞닿게 된다 (도 4 참조).Here, the upper heat plate 521 and the lower heat plate 522 are in a heated state in advance. Thereafter, the upper mold 511 is moved to the lower mold 512 side to close the gap between the upper mold 511 and the lower mold 512. The lower press member 532 of the jig 53 comes into contact with the lower plate 522 (see FIG. 4).

그 후, 도 5 에 나타내는 바와 같이, 상열판 (521) 을 하방으로 이동시키고, 상열판 (521) 이 지그 (53) 의 상측 가압 부재 (531) 에 맞닿는다. 지그 (53) 의 상측 가압 부재 (531) 는 상열판 (521) 에 의해 하방으로 눌리고, 지그 (53) 는, 하열판 (522) 과 상열판 (521) 으로 협압되고, 지그 (53) 의 상측 가압 부재 (531, 532) 에 의해 복수의 적층체 (4) 가 협압되게 된다.Thereafter, as shown in FIG. 5, the upper heat plate 521 is moved downward, and the upper heat plate 521 abuts against the upper pressing member 531 of the jig 53. The upper pressurizing member 531 of the jig 53 is pressed downward by the upper heat plate 521, and the jig 53 is pinched by the lower heat plate 522 and the upper heat plate 521, and the upper side of the jig 53. The plurality of laminates 4 are pressed by the pressing members 531, 532.

즉, 복수의 적층체 (4) 를 땜납층 (112) 의 융점 미만, 또한, 수지층 (3) 의 경화 온도 미만, 즉 수지층 (3) 의 열경화성 수지의 경화 온도 미만 (수지층 (3) 에 함유되는 열경화성 수지가, JIS K 6900 에 준하는 C-스테이지가 되는 온도 미만) 에서 가열하면서, 적층체 (4) 의 적층 방향을 따라 협압하고, 제 1 단자 (11) 와 제 2 단자 (21) 가 접촉하도록 제 2 단자 (21) 가 수지층 (3) 에 함몰하게 된다.That is, the plurality of laminates 4 are less than the melting point of the solder layer 112, and less than the curing temperature of the resin layer 3, that is, less than the curing temperature of the thermosetting resin of the resin layer 3 (resin layer 3) The thermosetting resin contained in the pressure-reduced pressure is reduced along the lamination direction of the laminate 4 while heating at a temperature below the temperature at which the C-stage conforms to JIS K 6900), and thus, the first terminal 11 and the second terminal 21. The second terminal 21 is recessed in the resin layer 3 so as to contact each other.

다음으로, 상형 (511), 하형 (512) 을 이간하여, 노 (51) 내로부터 복수의 적층체 (4) 를 반출한다. 또한, 복수의 적층체 (4) 를 협압할 때에 진공 하에서 협압해도 된다. 이로써, 수지층 (3) 에서의 보이드의 발생을 억제할 수 있다. 그 후, 도 8 에 나타내는 장치 (6) 를 사용하여, 복수의 적층체 (4) 를 제 1 단자 (11) 의 땜납층 (112) 의 융점 이상으로 가열하여, 제 1 단자 (11) 와 제 2 단자 (21) 를 땜납 접합시킨다.Next, the upper mold | type 511 and the lower mold | type 512 are separated, and the some laminated body 4 is carried out from inside the furnace 51. FIG. In addition, when pinching the some laminated body 4, you may pinch under vacuum. Thereby, generation | occurrence | production of the void in the resin layer 3 can be suppressed. Then, using the apparatus 6 shown in FIG. 8, the some laminated body 4 is heated beyond melting | fusing point of the solder layer 112 of the 1st terminal 11, and the 1st terminal 11 and the 1st agent are made. The two terminals 21 are soldered together.

장치 (6) 는, 적층체 (4) 를 가압 분위기 하에서 가열할 수 있는 것으로, 구조로는, 예를 들어, 적층체 (4) 를 내부에 수용하는 용기 (61) 와, 이 용기 (61) 내에 유체를 도입하기 위한 배관 (62) 을 갖는다.The apparatus 6 can heat the laminated body 4 in a pressurized atmosphere, As a structure, it is the container 61 which accommodates the laminated body 4 inside, and this container 61, for example. It has a piping 62 for introducing a fluid into it.

용기 (61) 는 압력 용기인 것이 특징이고, 용기 (61) 내에 적층체 (4) 를 설치한 후, 배관 (62) 으로부터 가열하고, 추가로 가압한 유체를 용기 (61) 내에 유입시킴으로써, 적층체 (4) 를 가열 가압하게 된다.The container 61 is characterized by being a pressure container, and after the laminated body 4 is installed in the container 61, the container 61 is heated from the pipe 62, and the fluid further pressurized is introduced into the container 61, thereby laminating it. The sieve 4 is heated and pressurized.

또, 배관 (62) 으로부터 유체를 용기 (61) 내에 유입시켜, 가압 분위기 하로 하면서, 용기 (61) 를 가열함으로써, 적층체 (4) 를 가열할 수도 있다. 용기 (61) 의 재료로는, 금속을 들 수 있고, 예를 들어, 스테인리스, 티탄, 구리, 이들의 합금 등이다.Moreover, the laminated body 4 can also be heated by flowing the fluid from the piping 62 in the container 61, and heating the container 61, under pressure atmosphere. As a material of the container 61, a metal is mentioned, For example, stainless steel, titanium, copper, these alloys, etc. are mentioned.

유체에 의해, 적층체 (4) 를 가압할 때의 가압력은, 0.1 ∼ 10 ㎫, 바람직하게는 0.5 ∼ 5 ㎫ 이다. 이와 같이 함으로써, 경화한 수지층 (3) 중에 공극 (보이드) 이 잘 발생하지 않게 된다.The pressing force at the time of pressurizing the laminated body 4 with a fluid is 0.1-10 Mpa, Preferably it is 0.5-5 Mpa. By doing in this way, the space | gap (void) hardly arises in the hardened resin layer 3.

또한, 본 발명에 있어서, 유체로 가압한다란, 적층체 (4) 의 분위기의 압력을, 대기압보다 가압력 만큼 높게 하는 것을 가리킨다. 즉, 가압력 10 ㎫ 이란, 대기압보다 적층체에 작용하는 압력이 10 ㎫ 큰 것을 나타낸다.In addition, in this invention, pressurizing with a fluid refers to making the pressure of the atmosphere of the laminated body 4 higher by the pressurization pressure than atmospheric pressure. That is, a pressure of 10 MPa means that the pressure acting on the laminate is 10 MPa larger than the atmospheric pressure.

용기 (61) 내에 적층체 (4) 를 설치한 후, 적층체 (4) 가 가열됨과 함께, 적층체 (4) 가 가압된다. 적층체 (4) 를 가압하는 유체는, 배관 (62) 으로부터 용기 (61) 내에 도입되어, 적층체 (4) 를 가압하게 된다. 적층체 (4) 를 가압하는 유체로는 질소 가스, 아르곤 가스 등의 비산화성 가스, 공기 등의 가스가 바람직하다.After installing the laminated body 4 in the container 61, while the laminated body 4 is heated, the laminated body 4 is pressurized. The fluid pressurizing the laminate 4 is introduced into the container 61 from the pipe 62 to pressurize the laminate 4. As a fluid which pressurizes the laminated body 4, non-oxidizing gas, such as nitrogen gas and argon gas, gas, such as air, is preferable.

그 중에서도, 비산화성 가스를 사용하는 것이 바람직하다. 비산화성 가스를 사용함으로써, 제 1 단자 (11) 및 제 2 단자 (21) 의 접합을 보다 양호한 것으로 할 수 있다. 또한, 비산화성 가스란 불활성 가스, 질소 가스를 의미한다.Especially, it is preferable to use a non-oxidizing gas. By using a non-oxidizing gas, joining of the 1st terminal 11 and the 2nd terminal 21 can be made more favorable. In addition, a non-oxidizing gas means an inert gas and nitrogen gas.

적층체 (4) 의 온도가 땜납층 (112) 의 융점에 이른 후, 용기 (61) 내의 온도 및 압력을 유지하면서, 소정 시간, 적층체 (4) 를 가열 및 가압한다. 이로써, 적층체 (4) 중의 수지층 (3) 이 경화되게 된다.After the temperature of the laminated body 4 reaches melting | fusing point of the solder layer 112, while maintaining the temperature and pressure in the container 61, the laminated body 4 is heated and pressurized for a predetermined time. Thereby, the resin layer 3 in the laminated body 4 will harden | cure.

그 후, 장치 (6) 로부터 적층체 (4) 를 꺼내고, 필요에 따라 적층체 (4) 를 다시 경화시킨다. 이상에 의해, 전자 장치를 얻을 수 있다 (도 9 참조). 도 9 에서는, 제 1 단자 (11) 와 제 2 단자 (21) 가 땜납층 (112) 에 의해 접합되고, 제 2 단자 (21) 의 선단이, 땜납층 (112) 에 파고든 상태로 되어 있다. 또한, 도 6 에서 나타낸 점선의 절단 라인에 따라, 제 1 전자 부품 (1) 간, 수지층 (3) 간을 절단함으로써 분리한 복수의 전자 장치를 얻을 수 있다.Then, the laminated body 4 is taken out from the apparatus 6, and the laminated body 4 is hardened again as needed. The electronic device can be obtained by the above (refer FIG. 9). In FIG. 9, the 1st terminal 11 and the 2nd terminal 21 are joined by the solder layer 112, and the front-end | tip of the 2nd terminal 21 is in the state which dug in the solder layer 112. In FIG. Moreover, along the cutting line of the dotted line shown in FIG. 6, the some electronic device isolate | separated by cutting between the 1st electronic components 1 and the resin layer 3 can be obtained.

다음으로, 본 실시형태의 작용 효과에 대해 설명한다. 본 실시형태에서는, 복수의 적층체 (4) 를 가열하면서, 복수의 적층체 (4) 를 동시에 적층체 (4) 의 적층 방향으로부터 협압하고 있다. 이로써, 첫 번째 적층체 (4) 의 제 1 전자 부품 (1) 과 제 2 전자 부품 (2) 을 협압하고 있는 동안에, 다른 적층체 (4) 의 수지층 (3) 의 경화가 진행되는 것이 억제된다. 따라서, 신뢰성이 높은 전자 장치를 안정적으로 제조할 수 있다.Next, the effect of this embodiment is demonstrated. In this embodiment, the some laminated body 4 is pinched from the lamination direction of the laminated body 4 simultaneously, heating the some laminated body 4. Thereby, while adhering the 1st electronic component 1 and the 2nd electronic component 2 of the 1st laminated body 4, it is suppressed that hardening of the resin layer 3 of the other laminated body 4 advances. do. Therefore, a highly reliable electronic device can be manufactured stably.

또, 본 실시형태에서는, 적층체 (4) 를 가압 유체에 의해 가압하여 수지층 (3) 을 경화시키고 있기 때문에, 수지층 (3) 의 경화물 중의 기포 등의 공극의 발생을 억제할 수 있다. 또한, 제 1 단자 (11) 및 제 2 단자 (21) 를 땜납 접합할 때에, 유체에 의해 적층체 (4) 를 가압하면, 수지층 (3) 의 밀도를 높여, 체적을 저감시킴으로써, 제 1 단자 (11) 와 제 2 단자 (21) 가 압착하는 방향으로 힘을 작용시키는 것이 가능해진다.Moreover, in this embodiment, since the laminated body 4 is pressurized with a pressurized fluid and the resin layer 3 is hardened | cured, generation | occurrence | production of the space | gaps, such as a bubble in the hardened | cured material of the resin layer 3, can be suppressed. . In addition, when soldering the 1st terminal 11 and the 2nd terminal 21, when the laminated body 4 is pressurized with a fluid, the density of the resin layer 3 will be raised and a volume will be reduced, The force can be exerted in the direction in which the terminal 11 and the second terminal 21 are crimped.

또한, 제 1 단자 (11) 및 제 2 단자 (21) 를 접합할 때에, 유체에 의해 적층체 (4) 를 가압하면, 수지층 (3) 의 발포에 의한 수지 유동을 억제할 수 있고, 제 1 단자 (11) 및 제 2 단자 (21) 간의 차이를 확실하게 저감시킬 수 있다.In addition, when joining the 1st terminal 11 and the 2nd terminal 21, when the laminated body 4 is pressurized with a fluid, resin flow by foaming of the resin layer 3 can be suppressed, The difference between the first terminal 11 and the second terminal 21 can be reliably reduced.

또, 본 실시형태에서는, 적층체 (4) 를 협압하는 상측 가압 부재 (531) 에 홈 (531A) 을 형성하고 있다. 적층체 (4) 를 협압할 때에, 적층체 (4) 의 수지층 (3) 이 적층체 (4) 로부터 비어져 나오는 경우가 있는데, 비어져 나온 수지층 (3) 을 홈 (531A) 내로 놓아줄 수 있다. 이로써, 제 2 전자 부품 (2) 과 상측 가압 부재 (531) 사이에 수지가 비집고 들어가는 것을 방지할 수 있다.Moreover, in this embodiment, the groove 531A is formed in the upper press member 531 which pinches the laminated body 4. At the time of pinching the laminated body 4, the resin layer 3 of the laminated body 4 may protrude from the laminated body 4, but the protruding resin layer 3 is placed in the groove 531A. Can give Thereby, resin can be prevented from slipping in between the 2nd electronic component 2 and the upper side press member 531.

또한, 본 실시형태에서는, 홈 (531A) 으로 구획된 상기 영역 (531B) 에 맞닿는 제 2 전자 부품 (2) 의 단면이, 홈 (531A) 의 측면 (531C) 보다 홈 (531A) 내측으로 돌출되어 있다.In addition, in this embodiment, the cross section of the 2nd electronic component 2 which abuts on the said area | region 531B divided by the groove 531A protrudes inside groove 531A rather than the side surface 531C of groove 531A. have.

적층체 (4) 를 협압할 때에, 적층체 (4) 로부터 비어져 나온 수지가, 적층체 (4) 의 제 2 전자 부품 (2) 의 단면을 따라 기어오르는 경우가 있다. 홈 (531A) 의 측면 (531C) 이, 제 2 전자 부품 (2) 의 단면보다, 홈 (531A) 내측으로 돌출되어 있지 않기 때문에, 제 2 전자 부품 (2) 의 단면을 기어오르는 수지가 상측 가압 부재 (531) 에 부착되는 것을 억제할 수 있다. 그 때문에, 상측 가압 부재 (531) 의 수지에 의한 오염을 방지할 수 있다.When pinching the laminated body 4, the resin which protruded from the laminated body 4 may climb along the cross section of the 2nd electronic component 2 of the laminated body 4. Since the side surface 531C of the groove 531A does not protrude into the groove 531A inside the cross section of the second electronic component 2, the resin that climbs up the cross section of the second electronic component 2 is pressurized upward. Attachment to the member 531 can be suppressed. Therefore, contamination by resin of the upper press member 531 can be prevented.

또, 상측 가압 부재 (531) 에 홈 (531A) 을 형성하지 않는 경우에는, 적층체 (4) 로부터 비어져 나온 수지가 상기 부재에 부착되어 상기 부재의 적층체 (4) 측의 면이 평탄하지 않게 될 가능성이 있다. 그 때문에, 적층체 (4) 에 작용하는 하중에 편차가 발생하는 경우가 있다. 이에 반하여, 본 실시형태에서는, 상기 서술한 바와 같이 상측 가압 부재 (531) 에 대한 수지의 부착을 방지할 수 있으므로, 적층체 (4) 에 작용하는 하중의 편차의 발생을 억제할 수 있다.In addition, when the groove 531A is not formed in the upper pressurizing member 531, the resin protruding from the laminated body 4 adheres to the member, and the surface of the laminated body 4 side of the member is not flat. There is a possibility of not. Therefore, a deviation may arise in the load which acts on the laminated body 4. On the other hand, in this embodiment, since sticking of resin to the upper press member 531 can be prevented as mentioned above, generation | occurrence | production of the deviation of the load which acts on the laminated body 4 can be suppressed.

또한, 본 발명은 상기 서술한 실시형태에 한정되는 것이 아니고, 본 발명의 목적을 달성할 수 있는 범위에서의 변형, 개량 등은 본 발명에 포함되는 것이다. 예를 들어, 상기 형태에서는, 장치 (5) 에 있어서 지그 (53) 를 사용하고 있었지만, 이것에 한정되지 않고, 지그 (53) 를 사용하지 않아도 되다.In addition, this invention is not limited to embodiment mentioned above, The deformation | transformation, improvement, etc. in the range which can achieve the objective of this invention are included in this invention. For example, in the said aspect, although the jig 53 was used in the apparatus 5, it is not limited to this, It is not necessary to use the jig 53. As shown in FIG.

또, 상기 형태에서는, 제 1 전자 부품 (1) 끼리, 수지층 (3) 끼리가 늘어서 있었지만, 이것에 한정되는 것은 아니다. 예를 들어, 미리 제 1 전자 부품 (1) 끼리, 수지층 (3) 끼리가 분리되어 있고, 제 1 전자 부품 (1) 간, 수지층 (3) 간에 간극 (공극) 이 있어도 된다.Moreover, in the said aspect, although the 1st electronic component 1 comrades and the resin layer 3 comrades lined up, it is not limited to this. For example, the 1st electronic components 1 and the resin layer 3 may isolate | separate previously, and the clearance gap (gap) may exist between the 1st electronic components 1 and the resin layer 3.

또한, 상기 형태에서는, 제 2 전자 부품 (2) 에 상측 가압 부재 (531) 를 맞닿게 하고 있었지만, 이것에 한정되는 것이 아니며, 제 1 전자 부품 (1) 에 상측 가압 부재 (531) 를 맞닿게 해도 된다.In addition, in the said aspect, although the upper press member 531 was made to contact the 2nd electronic component 2, it is not limited to this, The upper press member 531 makes the 1st electronic component 1 abut. You may also

또, 일방의 적층체 (4) 에 있어서는, 제 1 전자 부품 (1) 에 상측 가압 부재 (531) 가 맞닿도록 하고, 타방의 적층체 (4) 에 있어서는, 제 2 전자 부품 (2) 에 상측 가압 부재 (531) 가 맞닿도록 해도 된다. 단, 단자끼리의 접합 안정성의 관점에서는, 상기 형태와 같이, 상측 가압 부재 (531) 에 접촉하는 부품은 동일한 부품인 것이 바람직하다.Moreover, in one laminated body 4, the upper press member 531 abuts on the 1st electronic component 1, and in the other laminated body 4, it is upper side to the 2nd electronic component 2 The pressing member 531 may abut. However, from the viewpoint of the bonding stability of the terminals, it is preferable that the parts in contact with the upper pressing member 531 are the same parts as in the above-described embodiment.

또한, 상기 형태에서는 적층체 (4) 의 제 2 전자 부품 (2) 에 맞닿는 영역 (531B) 을 구획하는 홈 (531A) 이 하면에만 형성되어 있고, 상면은 평탄한 상측 가압 부재 (531) 를 예시하였다.Moreover, in the said form, the groove 531A which partitions the area | region 531B which abuts on the 2nd electronic component 2 of the laminated body 4 is formed only in the lower surface, and the upper surface illustrated the flat upper press member 531. .

그러나, 도 10 에 협압 부재로서 예시하는 상측 가압 부재 (533) 와 같이, 하면의 홈 (531A) 과 동일한 홈 (533A) 이 상면에도 형성되어 영역 (533B) 이 구획되어 있고, 상하 대칭의 상측 가압 부재 (533) 등도 실시 가능하다. 여기서 말하는 상하 방향은, 도 10 의 상하 방향에 대응하고 있다. 즉, 적층체 (4) 의 적층 방향과 일치한다.However, like the upper pressing member 533 illustrated as the pinching member in FIG. 10, the same groove 533A as the lower surface groove 531A is also formed on the upper surface so that the region 533B is partitioned, and the upper and lower symmetric upper pressing is performed. The member 533 can also be implemented. The vertical direction referred to here corresponds to the vertical direction in FIG. 10. That is, it matches with the lamination direction of the laminated body 4.

이와 같은 상측 가압 부재 (533) 는, 상하 대칭이므로 가압에 의한 만곡을 양호하게 방지할 수 있고, 보다 균등하게 복수의 제 2 전자 부품 (2) 을 제 1 전자 부품 (1) 에 가압할 수 있다. 게다가, 상기 서술한 바와 같은 상측 가압 부재 (533) 는 상하 대칭이므로, 제조시의 압력 등에 의해 상하 방향으로 만곡하는 것 등도 방지할 수 있다.Since the upper pressing member 533 is vertically symmetrical, it is possible to satisfactorily prevent the bending due to the pressing, and can evenly press the plurality of second electronic components 2 to the first electronic components 1. . In addition, since the upper pressing member 533 as described above is vertically symmetrical, it is possible to prevent the bending in the vertical direction due to the pressure at the time of manufacture or the like.

또, 상기 형태에서는 전자 장치의 제조 방법에 있어서, 적층체 (4) 를 얻는 공정에서는, 수지층 (3) 의 경화 온도 미만의 온도에서 적층체 (4) 를 가열하면서, 프레스 부재인 열판 (521, 522) 에 의해 적층체 (4) 의 적층 방향을 따라 적층체 (4) 를 기계적으로 가압하는 것만 예시하였다.Moreover, in the said aspect, in the manufacturing method of an electronic device, in the process of obtaining the laminated body 4, the hotplate 521 which is a press member, heating the laminated body 4 at the temperature below the hardening temperature of the resin layer 3. , 522 only illustrates mechanically pressing the laminate 4 along the lamination direction of the laminate 4.

그러나, 이와 같이 적층체 (4) 를 기계적으로 가압할 때, 추가로 공기 등의 유체에 의해 적층체 (4) 를 가압해도 된다 (도시 생략). 이 경우, 적층체 (4) 를 균일하게 가압할 수 있을 뿐만 아니라, 수지층 (3) 에 발생하는 기포의 팽창도 방지할 수 있다.However, when mechanically pressurizing the laminated body 4 in this way, you may further pressurize the laminated body 4 with fluids, such as air (not shown). In this case, not only the laminated body 4 can be pressurized uniformly, but also the expansion of the bubble which arises in the resin layer 3 can be prevented.

또한, 상기 서술한 적층체 (4) 를 얻는 공정에서는, 수지층 (3) 의 경화 온도 미만이고, 수지층 (3) 의 점도가 1 Pa·s 이상, 10000 Pa·s 이하가 되는 온도에서 적층체 (4) 를 가열해도 된다. 또, 상기 서술한 적층체 (4) 를 얻는 공정에 있어서, 용기인 용기 (61) 내에 적층체 (4) 를 배치하고, 용기 (61) 내에 유체를 도입하여, 유체에 의해, 적층체 (4) 를 가압해도 된다. 이와 같은 유체는 공기나 질소를 이용할 수 있다.In addition, in the process of obtaining the laminated body 4 mentioned above, it laminates at the temperature which is less than the hardening temperature of the resin layer 3, and the viscosity of the resin layer 3 becomes 1 Pa * s or more and 10000 Pa * s or less. The sieve 4 may be heated. Moreover, in the process of obtaining the laminated body 4 mentioned above, the laminated body 4 is arrange | positioned in the container 61 which is a container, the fluid is introduce | transduced into the container 61, and the laminated body 4 is carried out by the fluid. ) May be pressurized. Such a fluid may use air or nitrogen.

또한, 상기 서술한 바와 같이 적층체 (4) 를 가압하는 유체의 압력은, 노 (51) 의 상형 (511) 과 하형 (512) 을 개방하는 내압이 된다. 그래서, 도 11 에 나타내는 바와 같이, 노 (51) 의 상형 (511) 과 하형 (512) 을 폐지(閉止)하는 압력과, 적층체 (4) 를 직접 가압하는 열판 (521, 522) 의 압력과, 적층체 (4) 를 가압하는 노 (51) 내의 기압을, 각각 별개로 제어할 수 있는 것이 바람직하다.In addition, as mentioned above, the pressure of the fluid which pressurizes the laminated body 4 becomes the internal pressure which opens the upper mold | type 511 and the lower mold | type 512 of the furnace 51. As shown in FIG. Therefore, as shown in FIG. 11, the pressure which closes the upper mold | type 511 and the lower mold | type 512 of the furnace 51, the pressure of the hot plates 521 and 522 which pressurize the laminated body 4 directly, It is preferable that the air pressure in the furnace 51 which presses the laminated body 4 can be controlled separately, respectively.

이 출원은, 2010년 4월 23일에 출원된 일본 특허출원 2010-099553호, 2010년 7월 1일에 출원된 일본 특허출원 2010-150827호, 2010년 8월 24일에 출원된 일본 특허출원 2010-186870호를 기초로 하는 우선권을 주장하고, 그 개시의 모두를 여기에 받아들인다.This application is filed in Japanese Patent Application No. 2010-099553, filed April 23, 2010, Japanese Patent Application No. 2010-150827, filed July 1, 2010, and Japanese Patent Application, filed August 24, 2010. We claim priority based on 2010-186870 and accept all of its disclosures here.

Claims (20)

표면에 땜납층을 갖는 제 1 단자를 갖는 제 1 전자 부품과, 이 제 1 전자 부품의 상기 제 1 단자에 접합되는 제 2 단자를 갖는 제 2 전자 부품을 구비하는 전자 장치의 제조 방법으로서,
상기 제 1 전자 부품의 제 1 단자와 상기 제 2 전자 부품의 제 2 단자 사이에 플럭스 활성 화합물과 열경화성 수지를 함유하는 수지층을 배치하여 적층체를 얻는 공정과,
상기 적층체를 상기 제 1 단자의 상기 땜납층의 융점 이상으로 가열하여, 상기 제 1 단자와 상기 제 2 단자를 땜납 접합시키는 공정과,
유체에 의해 상기 적층체를 가압하면서, 상기 수지층을 경화시키는 공정을 포함하고,
상기 적층체를 얻는 상기 공정에서는,
복수의 제 1 전자 부품의 제 1 단자와 복수의 제 2 전자 부품의 제 2 단자를 각각 대향 배치시키고, 각 제 1 단자와 각 제 2 단자 사이에 상기 수지층을 배치하여 복수의 적층체를 형성하고, 복수의 적층체를 가열하면서, 상기 복수의 적층체를 동시에 상기 적층체의 적층 방향으로부터 협압하는, 전자 장치의 제조 방법.A method of manufacturing an electronic device, comprising: a first electronic component having a first terminal having a solder layer on its surface; and a second electronic component having a second terminal joined to the first terminal of the first electronic component;
Arranging a resin layer containing a flux active compound and a thermosetting resin between a first terminal of said first electronic component and a second terminal of said second electronic component to obtain a laminate;
Heating the laminate above the melting point of the solder layer of the first terminal to solder-bond the first terminal and the second terminal,
Curing the resin layer while pressing the laminate with a fluid,
In the said process of obtaining the said laminated body,
First terminals of the plurality of first electronic components and second terminals of the plurality of second electronic components are disposed to face each other, and the resin layer is disposed between each of the first terminals and each of the second terminals to form a plurality of laminates. And pressurizing the plurality of laminates simultaneously from the stacking direction of the laminate while heating the plurality of laminates. 제 1 항에 있어서,
상기 복수의 적층체는 면내 방향으로 배열되어 있는, 전자 장치의 제조 방법.The method of claim 1,
The plurality of laminates are arranged in an in-plane direction. 제 1 항 또는 제 2 항에 있어서,
적층체를 얻는 상기 공정에서는,
상기 복수의 적층체를 1 쌍의 협압 부재로 협압하고,
상기 1 쌍의 협압 부재 중, 일방의 협압 부재는, 홈이 형성된 부재이고,
홈이 형성된 상기 부재를 상기 적층체에 맞닿게 했을 때에,
일방의 협압 부재의 상기 홈으로 구획된 각 영역이 각각 상기 적층체의 제 1 전자 부품 또는 제 2 전자 부품에 맞닿고, 또한, 상기 홈으로 구획된 상기 영역에 맞닿는 제 1 전자 부품 또는 제 2 전자 부품의 단면이, 상기 홈의 측면보다 홈 내측으로 돌출되는, 전자 장치의 제조 방법.3. The method according to claim 1 or 2,
In the said process of obtaining a laminated body,
The plurality of laminates are pinched with a pair of pinching members,
Of the pair of pinching members, one of the pinching members is a member in which a groove is formed,
When the said member in which the groove was formed was made to contact the said laminated body,
Each of the regions partitioned by the grooves in one of the pinching members contacts the first electronic component or the second electronic component of the laminate, and the first electronic component or the second electrons abuts on the region partitioned by the grooves. The cross section of a component protrudes inside a groove rather than the side surface of the said groove. 제 3 항에 있어서,
홈이 형성된 상기 부재를 상기 적층체에 맞닿게 했을 때에,
상기 홈으로 구획된 상기 영역에는, 각 적층체의 제 1 전자 부품 및 제 2 전자 부품 중 일방의 부품이 맞닿고,
복수의 적층체의 각 수지층은 늘어서, 수지 시트를 구성하고,
상기 적층체의 적층 방향에서 보아, 인접하는 적층체의 상기 일방의 부품간으로부터 상기 수지 시트의 일부가 노출되고,
홈이 형성된 상기 부재를 상기 적층체에 맞닿게 했을 때에, 노출된 상기 수지 시트의 일부가 상기 홈과 대향하는, 전자 장치의 제조 방법.The method of claim 3, wherein
When the said member in which the groove was formed was made to contact the said laminated body,
In the region divided by the groove, one of the first electronic component and the second electronic component of each laminate abuts,
Each resin layer of a some laminated body lines up, and comprises a resin sheet,
From the lamination direction of the said laminated body, a part of said resin sheet is exposed from between the said one parts of adjacent laminated bodies,
The part of the said resin sheet exposed when the said member in which the groove | channel was formed contacted the said laminated body opposes the said groove | channel, The manufacturing method of the electronic device. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,
적층체를 얻는 상기 공정에서는,
상기 수지층의 경화 온도 미만의 온도에서 상기 적층체를 가열하면서, 프레스 부재에 의해 상기 적층체의 적층 방향을 따라 상기 적층체를 가압함과 함께, 유체에 의해 상기 적층체를 가압하는, 전자 장치의 제조 방법.The method according to any one of claims 1 to 4,
In the said process of obtaining a laminated body,
The electronic device which presses the said laminated body by a fluid while pressing the said laminated body along the lamination direction of the said laminated body by a press member, heating the said laminated body at the temperature below the hardening temperature of the said resin layer. Method of preparation. 제 5 항에 있어서,
상기 적층체를 얻는 상기 공정에 있어서,
상기 프레스 부재는, 열판이고, 상기 열판을 적층체에 맞닿게 함으로써, 상기 적층체가 가열되는, 전자 장치의 제조 방법.The method of claim 5, wherein
In the step of obtaining the laminate,
The press member is a hot plate, and the laminate is heated by bringing the hot plate into contact with the laminate. 제 5 항 또는 제 6 항에 있어서,
상기 적층체를 얻는 상기 공정에 있어서, 용기 내에 상기 적층체를 배치하고, 상기 용기 내에 상기 유체를 도입하여, 상기 유체에 의해 상기 적층체를 가압하는, 전자 장치의 제조 방법.The method according to claim 5 or 6,
In the step of obtaining the laminate, the laminate is disposed in a container, the fluid is introduced into the container, and the laminate is pressurized by the fluid. 제 1 항 또는 제 2 항에 있어서,
적층체를 얻는 상기 공정은,
상기 복수의 적층체를 1 쌍의 협압 부재로 협압하는 공정과,
상기 수지층의 경화 온도 미만의 온도에서 상기 적층체를 가열하면서, 상기 1 쌍의 협압 부재를 프레스 부재에 의해 상기 적층체의 적층 방향으로부터 협압함으로써, 상기 적층체의 적층 방향을 따라 상기 적층체를 가압함과 함께, 유체에 의해 상기 적층체를 가압하는 공정을 포함하고,
상기 1 쌍의 협압 부재 중, 일방의 협압 부재는, 홈이 형성된 부재이고,
홈이 형성된 상기 부재를 상기 적층체에 맞닿게 했을 때에,
일방의 협압 부재의 상기 홈으로 구획된 각 영역이 각각 상기 적층체의 제 1 전자 부품 또는 제 2 전자 부품에 맞닿고, 또한, 상기 홈으로 구획된 상기 영역에 맞닿는 제 1 전자 부품 또는 제 2 전자 부품의 단면이, 상기 홈의 측면보다 홈 내측으로 돌출되는, 전자 장치의 제조 방법.3. The method according to claim 1 or 2,
The process of obtaining a laminate,
A step of pinching the plurality of laminates with a pair of pinching members,
While pressing the said pair of pinching members from the lamination direction of the said laminated body with a press member, heating the said laminated body at the temperature below the hardening temperature of the said resin layer, the said laminated body is made along the lamination direction of the said laminated body. Pressurizing and pressurizing the laminate by a fluid;
Of the pair of pinching members, one of the pinching members is a member in which a groove is formed,
When the said member in which the groove was formed was made to contact the said laminated body,
Each of the regions partitioned by the grooves in one of the pinching members contacts the first electronic component or the second electronic component of the laminate, and the first electronic component or the second electrons abuts on the region partitioned by the grooves. The cross section of a component protrudes inside a groove rather than the side surface of the said groove. 제 1 항 내지 제 8 항 중 어느 한 항에 있어서,
상기 적층체를 얻는 상기 공정에서는,
상기 수지층의 점도가 1 Pa·s 이상, 10000 Pa·s 이하가 되는 온도에서 상기 적층체를 가열하는, 전자 장치의 제조 방법.The method according to any one of claims 1 to 8,
In the said process of obtaining the said laminated body,
The manufacturing method of the electronic device which heats the said laminated body at the temperature which the viscosity of the said resin layer becomes 1 Pa * s or more and 10000 Pa * s or less. 표면에 땜납층을 갖는 제 1 단자를 갖는 제 1 전자 부품의 상기 제 1 단자와, 이 제 1 전자 부품의 상기 제 1 단자에 접합되는 제 2 단자를 갖는 제 2 전자 부품의 상기 제 2 단자 사이에, 플럭스 활성 화합물과 열경화성 수지를 함유하는 수지층을 배치하여, 적층체를 형성한 후, 상기 제 1 단자와 상기 제 2 단자를 접촉시키기 위한 장치로서,
복수의 적층체를 동시에 협압하는 협압 부재를 구비하는, 장치.Between the first terminal of a first electronic component having a first terminal having a solder layer on its surface, and the second terminal of a second electronic component having a second terminal joined to the first terminal of the first electronic component An apparatus for contacting the first terminal and the second terminal after arranging a resin layer containing a flux active compound and a thermosetting resin in a to form a laminate.
An apparatus provided with the pinching member which pinches a some laminated body simultaneously. 제 10 항에 있어서,
상기 협압 부재는, 면내 방향으로 배열된 상기 복수의 적층체를 동시에 협압하는, 장치.11. The method of claim 10,
The pinching member is configured to pinch the plurality of laminates arranged in the in-plane direction simultaneously. 제 10 항 또는 제 11 항에 있어서,
상기 협압 부재는, 상기 복수의 적층체를 협압하는 1 쌍의 협압 부재를 갖고,
상기 1 쌍의 협압 부재 중, 적어도 일방의 협압 부재는, 홈이 형성된 부재이고,
홈이 형성된 상기 부재를 상기 적층체에 맞닿게 했을 때에,
일방의 협압 부재의 상기 홈으로 구획된 각 영역을 각각 상기 적층체의 제 1 전자 부품 또는 제 2 전자 부품에 맞닿고, 또한, 상기 홈으로 구획된 상기 영역에 맞닿는 제 1 전자 부품 또는 제 2 전자 부품의 단면이, 상기 홈의 측면보다 홈 내측으로 돌출되도록 구성되어 있는, 장치.The method of claim 10 or 11,
The pinching member has a pair of pinching members for pinching the plurality of laminates,
At least one pinching member is a member in which the groove | channel was formed among the said pair of pinching members,
When the said member in which the groove was formed was made to contact the said laminated body,
The first electronic component or the second electron which abuts each area | region partitioned by the said groove | channel of one pinching member with the 1st electronic component or the 2nd electronic component of the said laminated body, and touches the said area | region partitioned by the said groove | channel respectively, respectively. The device, wherein the cross section of the component is configured to project into the groove rather than the side of the groove. 제 10 항 내지 제 12 항 중 어느 한 항에 있어서,
상기 수지층의 경화 온도 미만의 온도에서 상기 적층체를 가열하면서, 프레스 부재에 의해 상기 적층체의 적층 방향을 따라 상기 적층체를 가압함과 함께, 유체에 의해 상기 적층체를 가압하도록 구성되어 있는, 장치.13. The method according to any one of claims 10 to 12,
While pressing the said laminated body along the lamination | stacking direction of the said laminated body by a press member, heating the said laminated body at the temperature below the hardening temperature of the said resin layer, It is comprised so that it may pressurize the said laminated body by a fluid. , Device. 제 13 항에 있어서,
상기 프레스 부재는, 열판이고, 상기 열판을 적층체에 맞닿게 함으로써, 상기 적층체를 가열하도록 구성되어 있는, 장치.The method of claim 13,
The press member is a hot plate, and is configured to heat the laminate by bringing the hot plate into contact with the laminate. 제 13 항 또는 제 14 항에 있어서,
용기 내에 상기 적층체를 배치하고, 상기 용기 내에 상기 유체를 도입하여, 상기 유체에 의해 상기 적층체를 가압하도록 구성되어 있는, 장치.The method according to claim 13 or 14,
The apparatus is configured to place the stack in a container, introduce the fluid into the container, and pressurize the stack with the fluid. 제 10 항 내지 제 15 항 중 어느 한 항에 있어서,
상기 적층체의 상기 수지층의 점도가 1 Pa·s 이상, 10000 Pa·s 이하가 되는 온도에서 상기 적층체를 가열하도록 구성되어 있는, 장치.16. The method according to any one of claims 10 to 15,
The apparatus is comprised so that the said laminated body may be heated at the temperature whose viscosity of the said resin layer of the said laminated body becomes 1 Pa * s or more and 10000 Pa * s or less. 제 12 항에 있어서,
1 쌍의 상기 협압 부재 중 상기 홈이 형성되어 있는 적어도 일방의 상기 협압 부재는, 상하 대칭으로 형성되어 있는, 장치.13. The method of claim 12,
At least one said pinching member in which the said groove | channel is formed among a pair of said pinching members is formed in up-down symmetry. 제 17 항에 있어서,
상기 1 쌍의 협압 부재 중 적어도 일방의 협압 부재는, 상기 제 2 전자 부품에 맞닿는 하면에 형성되어 있는 상기 홈과 상하 대칭으로 상면에도 홈이 형성되어 있는, 장치.The method of claim 17,
The at least one pinching member of the said pair of pinching members is a groove | channel formed in the upper surface in up-down symmetry with the said groove formed in the lower surface which contact | connects the said 2nd electronic component. 제 17 항 또는 제 18 항에 기재된 장치의 1 쌍의 협압 부재로서,
상기 홈이 형성되어 있는 적어도 일방의 협압 부재는, 상하 대칭으로 형성되어 있는, 1 쌍의 협압 부재.As a pair of pinching members of the apparatus of Claim 17 or 18,
The at least one pinching member in which the said groove is formed is a pair of pinching members formed in up-down symmetry. 제 19 항에 있어서,
적어도 일방의 협압 부재는, 상기 제 2 전자 부품에 맞닿는 하면에 형성되어 있는 상기 홈과 상하 대칭으로 상면에도 홈이 형성되어 있는, 1 쌍의 협압 부재.The method of claim 19,
At least one pinching member is a pair of pinching members in which the groove is formed also in the upper surface in the up-down symmetry with the said groove formed in the lower surface which contact | connects the said 2nd electronic component.
KR1020127030656A 2010-04-23 2011-04-13 Device and method for producing electronic device, and pair of compressed members thereof KR20130054283A (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP2010099553 2010-04-23
JPJP-P-2010-099553 2010-04-23
JP2010150827 2010-07-01
JPJP-P-2010-150827 2010-07-01
JPJP-P-2010-186870 2010-08-24
JP2010186870 2010-08-24
PCT/JP2011/002184 WO2011132384A1 (en) 2010-04-23 2011-04-13 Device and method for producing electronic device, and pair of compressed members thereof

Publications (1)

Publication Number Publication Date
KR20130054283A true KR20130054283A (en) 2013-05-24

Family

ID=44833928

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127030656A KR20130054283A (en) 2010-04-23 2011-04-13 Device and method for producing electronic device, and pair of compressed members thereof

Country Status (5)

Country Link
JP (1) JPWO2011132384A1 (en)
KR (1) KR20130054283A (en)
CN (1) CN102859674A (en)
TW (1) TW201222689A (en)
WO (1) WO2011132384A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230001904A (en) * 2021-06-29 2023-01-05 (주)나노테크 Jig for brazing welding with adjustable pressure distribution

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5867259B2 (en) * 2012-04-17 2016-02-24 住友ベークライト株式会社 Manufacturing method of laminate
JP5853944B2 (en) * 2012-12-25 2016-02-09 住友ベークライト株式会社 Manufacturing method of semiconductor device
CN107043847B (en) * 2016-02-09 2021-06-18 株式会社东北磁材研究所 Heat treatment device for laminated body of amorphous alloy thin strip and soft magnetic core

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2903697B2 (en) * 1990-11-06 1999-06-07 セイコーエプソン株式会社 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
JPH06349892A (en) * 1993-06-10 1994-12-22 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JP3301075B2 (en) * 1999-04-20 2002-07-15 ソニーケミカル株式会社 Method for manufacturing semiconductor device
JP3537400B2 (en) * 2000-03-17 2004-06-14 松下電器産業株式会社 Semiconductor built-in module and method of manufacturing the same
JP2002110744A (en) * 2000-09-26 2002-04-12 Matsushita Electric Ind Co Ltd Apparatus and method for mounting semiconductor
JP2004311709A (en) * 2003-04-07 2004-11-04 Renesas Technology Corp Manufacturing method of semiconductor device and semiconductor manufacturing device
JP3921459B2 (en) * 2003-07-11 2007-05-30 ソニーケミカル＆インフォメーションデバイス株式会社 Mounting method and mounting apparatus for electrical parts
JP4841431B2 (en) * 2005-02-02 2011-12-21 ソニーケミカル＆インフォメーションデバイス株式会社 Electrical component mounting equipment
JP4692101B2 (en) * 2005-06-27 2011-06-01 ソニー株式会社 Part joining method
JP2008147601A (en) * 2006-12-13 2008-06-26 Yoshihiro Shimada Flip chip bonding method, and method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230001904A (en) * 2021-06-29 2023-01-05 (주)나노테크 Jig for brazing welding with adjustable pressure distribution
KR20230002113A (en) * 2021-06-29 2023-01-05 (주)나노테크 Jig for brazing welding with adjustable pressure distribution

Also Published As

Publication number Publication date
CN102859674A (en) 2013-01-02
TW201222689A (en) 2012-06-01
JPWO2011132384A1 (en) 2013-07-18
WO2011132384A1 (en) 2011-10-27

Similar Documents

Publication Publication Date Title
JP5780228B2 (en) Manufacturing method of semiconductor device
JP5533663B2 (en) Manufacturing method of electronic device
WO2013027832A1 (en) Method for manufacturing semiconductor device, block stacked body, and sequential stacked body
WO2011048774A1 (en) Process for production of electronic device, electronic device, and device for production of electronic device
JP2012104782A (en) Method and apparatus for manufacturing semiconductor device
WO2009107357A1 (en) Solder connecting method, electronic device and method for manufacturing same
EP2375879A1 (en) Flexible substrate and electronic device
KR20130054283A (en) Device and method for producing electronic device, and pair of compressed members thereof
JP2013033952A (en) Manufacturing method of semiconductor device
WO2012026091A1 (en) Method for manufacturing electronic device
JP5948723B2 (en) Manufacturing method of electronic device
JP5853754B2 (en) Manufacturing method of semiconductor device
JP2014056954A (en) Semiconductor device manufacturing method and semiconductor device
JP2012160668A (en) Method for manufacturing electric component
JP2011228620A (en) Method of manufacturing electronic device and manufacturing apparatus of the same
JP2013045945A (en) Manufacturing method of semiconductor device
JP2016036041A (en) Method of manufacturing semiconductor device
JP2017028067A (en) Connection method of circuit member

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid