JP5867259B2 - Manufacturing method of laminate - Google Patents

Description

  The present invention relates to a method for manufacturing a laminate.

  A semiconductor device (stacked body) configured by stacking a plurality of semiconductor elements is used. For example, Patent Document 1 discloses a semiconductor device in which a plurality of semiconductor elements (or semiconductor substrates) having TSV (Through Silicon Via) are stacked, specifically, a plurality of semiconductor chips are stacked on an interposer via a resin layer. A semiconductor device (laminated body) is disclosed. Such a semiconductor device is considered to be manufactured as follows.

  First, bumps for connection are formed on the interposer in advance. Thereafter, a film adhesive (resin layer) is provided on the interposer, and then semiconductor chips are stacked and soldered. By repeating such operations, a semiconductor device (stacked body) in which semiconductor chips are stacked in a plurality of stages on the interposer is obtained.

JP 2011-29392 A

  However, in the method of manufacturing a semiconductor device disclosed in Patent Document 1, since solder bonding is repeatedly performed each time a semiconductor chip is stacked, productivity is deteriorated by multiple times of solder bonding. Further, since the solder bonding is repeatedly performed every time the semiconductor chips are stacked, there is a concern about the influence of heat at the time of solder bonding to the lower semiconductor chip.

  Therefore, the present inventors heated and applied the laminated body after laminating a plurality of substrates having terminals on the front surface or having terminals on both the front and back surfaces in a plurality of stages without performing solder bonding. A new technology has been invented to collectively perform solder bonding between the plurality of base materials (between terminals) by pressing.

  Specifically, first, the first base material and the second base material are laminated so that the terminals face each other with the resin layer interposed therebetween. In addition, it is assumed that at least one of the terminals of the first base material and the second base material facing each other includes a solder layer. At this stage, not only the solder layer but also the resin layer is interposed between the terminals of both base materials.

  Thereafter, the laminate is sandwiched between a pair of pressing members while being heated at a temperature at which the resin layer is melted and the solder layer is not melted. By this treatment, the resin interposed between the terminals is removed from the region, and a laminate in which the terminals of the first base material and the second base material are connected via the solder layer is obtained.

  Thereafter, the laminate is released from the pinching member, and the third base material is laminated on the laminate. Specifically, the terminals located on the back surface of the second base material and the terminals included in the third base material are laminated so as to face each other with the resin layer interposed therebetween. Note that at least one of the terminals of the second base material and the third base material facing each other is provided with a solder layer. At this stage, not only the solder layer but also the resin layer is interposed between the terminals of the second base material and the third base material.

  Thereafter, the laminate is sandwiched between a pair of pressing members while being heated at a temperature at which the resin layer is melted and the solder layer is not melted. By the treatment, the resin that was interposed between the terminals of the second base material and the third base material is removed from the region, and the terminals of the second base material and the third base material have solder layers. The laminated body connected through this is obtained.

  Thereafter, the same treatment is repeated to form a laminate in which a predetermined number of base materials are stacked in a predetermined stage.

  Thereafter, the laminated body is sandwiched between a plurality of base materials (between terminals) by being sandwiched between a pair of sandwiching members while being heated at a temperature at which the solder layer is melted. Thereafter, the laminate is heated to advance the curing of the resin layer.

  Hereinafter, the heating and pressurizing treatment performed to collectively perform the solder bonding between a plurality of base materials (between terminals) described above is referred to as “main press bonding”, and in order to stack a plurality of base materials in the previous stage. The heating / pressurizing process to be performed is called “temporary pressure bonding”.

  The inventors have newly invented the above-described technique. And the present inventors discovered the following new problems in the said invention.

  In the case of the said invention, a predetermined number of base materials are laminated | stacked, repeating temporary crimping | compression-release of a load. Note that when the load is released, the solder bonding between the terminals and the resin layer are not cured.

  In such a case, the resin of the resin layer enters between the terminals of each base material connected via the solder layer when applying a load (temporary pressure bonding) (resin bite) as the load is released, and the terminal-solder layer- The terminal connection state may be canceled.

  The resin between the terminals cannot be sufficiently discharged even in the subsequent press-bonding performed as a result, and as a result, the resin bite remains between the terminals and the connection between the terminals cannot be ensured. There is a fear.

  Therefore, the present invention provides a plurality of base materials having terminals on the front surface or having terminals on both the front and back surfaces in a plurality of layers without soldering, and then connecting the plurality of base materials (between the terminals). It is an object of the present invention to solve the problem of poor connection between terminals caused by resin biting between terminals that can occur in the technique of performing solder joints together.

According to the present invention,
A first base material having a first terminal, a first resin layer, and a second base material having a 2a terminal on the back surface thereof and a second base material having a second b terminal on the back surface thereof, the first terminal and the first 2a terminals are stacked so as to face each other with the first resin layer interposed therebetween, the first resin layer is melted, and at least one of the first terminal and the second a terminal is melted A first laminating step of forming a first laminate by applying a first load with a pair of clamping members while heating at a temperature that does not
After the first stacking step, an opening step of releasing a load on the first stack by the pinching member;
After the opening step, the second substrate having the first laminated body, the second resin layer, and the third terminal faces the second b terminal and the third terminal with the second resin layer interposed therebetween. And a pair of pressing members while heating at a temperature at which the second resin layer is melted and at least one of the second b terminal and the third terminal is not melted. A second stacking step of forming a second stack by applying a second load;
After the second lamination step, while heating the second laminated body at a temperature at which the first resin layer and the second resin layer melt and the first solder layer and the second solder layer do not melt. In addition, by applying a third load with a pair of clamping members, the resin layer interposed between the terminals is eliminated, and the first terminal, the first solder layer, and the second a terminal are directly connected, and The second b terminal, the second solder layer, and the third terminal are directly connected, and then the second stacked body is heated at a temperature at which the first solder layer and the second solder layer are melted. A first joining step of solder joining between the first terminal and the second a terminal and between the second b terminal and the third terminal by applying a load of
Have
In the first bonding step, the first resin layer and the second resin layer are melted and the second laminated body is heated at a temperature at which the first solder layer and the second solder layer are not melted. When the third load is applied by a pair of pressing members, the resin existing between the terminals is discharged from between the terminals while the first solder layer and the second solder layer are deformed .
As the third load, a method of manufacturing a laminate that is larger than both the first load and the second load can be obtained.

  According to the present invention, a plurality of base materials having terminals on the front surface or having terminals on both the front surface and the back surface are laminated in a plurality of stages without soldering, and then the plurality of base materials (between the terminals) ), It is possible to suppress the occurrence of poor connection between the terminals due to the resin biting between the terminals, which can occur in the technique of performing the solder joint collectively.

It is an example of the flowchart which shows the flow of a process of the manufacturing method of the laminated body of this embodiment. It is sectional drawing which shows the manufacturing process of the laminated body of this embodiment. It is sectional drawing which shows the manufacturing process of the laminated body of this embodiment. It is sectional drawing which shows the manufacturing process of the laminated body of this embodiment. It is sectional drawing which shows the manufacturing process of the laminated body of this embodiment. It is an example of the flowchart which shows the flow of a process of the manufacturing method of the laminated body of this embodiment. It is sectional drawing which shows the manufacturing process of the laminated body of this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same component and description is abbreviate | omitted suitably.

(First embodiment)
As a means for solving the problem of the present invention (resin biting between terminals), the present inventors apply the resin interposed between the terminals in the region in the main pressing (heating / pressing) after a plurality of temporary pressings. We investigated the means to connect the terminals together through the solder layer.

  As explained in the above section of the problem, when temporary press-fitting (heating / pressing) is performed on a laminate obtained by laminating the first base material and the second base material, it is interposed between the terminals of these base materials. The resin that has been removed can be removed from the region, and the terminals can be connected to each other through the solder layer. However, after that, when the load on the laminated body is released to further laminate another base material, the resin of the resin layer enters between the terminals (resin biting), and the terminal-solder layer-terminal connection state can be canceled. And then, even if the final pressure bonding (heating / pressurization) is performed on the laminate in which the base material is laminated in multiple stages by repeating the temporary pressure bonding a predetermined number of times, the resin that has entered between the terminals when the load is released cannot be sufficiently discharged. There is a case.

  As a result of examining the reason why the resin interposed between the terminals cannot be sufficiently removed by the main crimping, the present inventors have crushed the solder layer too much by the temporary crimping, that is, the height of the solder layer before the main crimping. Was found to be caused by being too low. If the solder layer is controlled so as not to be crushed by temporary crimping, that is, the solder layer height is sufficiently secured before the final crimping, and the solder layer is temporarily crushed so as to be sufficiently crushed during the final crimping. It has been found that when the crimping and the final crimping are controlled, the resin interposed between the terminals can be removed from the region by the final crimping performed after a plurality of temporary crimps. Hereinafter, the configuration of the first embodiment of the present invention based on such new knowledge will be described in detail with reference to FIGS. 1 to 5.

  FIG. 1 shows a flowchart showing an example of the processing flow of the laminate manufacturing method of the present embodiment. FIG. 2 to FIG. 5 show examples of process schematic diagrams of the laminated body of the present embodiment.

  As shown in FIG. 1, the manufacturing method of the laminated body formed in this embodiment includes a first lamination step S10, an opening step S20, a second lamination step S30, a first joining step S40, an installation step S50, 2 joining process S60.

<First lamination step S10>
In the first stacking step S10, a first base material having a first terminal, a first resin layer, and a second base material having a 2a terminal on the back surface thereof and a second base material having a 2b terminal on the back surface thereof, The first terminal and the second a terminal are stacked so as to face each other with the first resin layer interposed therebetween, the first resin layer is melted, and the first solder layer provided in at least one of the first terminal and the second a terminal is provided. A first laminate is formed by applying a first load with a pair of clamping members while heating at a temperature that does not melt. Hereinafter, the process will be described in detail using specific examples.

  First, for example, as shown in FIG. 2A, a semiconductor chip (semiconductor component) 10 is prepared as a first base material, and a semiconductor chip 12 is prepared as a second base material.

  The semiconductor chip 10 is provided with a terminal 101 (first terminal) connected to the semiconductor chip 12 on the substrate surface. Note that no terminal is provided on the other substrate surface (back surface) side of the semiconductor chip 10. Further, the semiconductor chip 10 is not provided with a via penetrating the substrate.

  For example, the terminal 101 has a structure in which a copper layer, a nickel layer, and a gold layer are laminated in this order from the substrate side. However, the structure of the terminal 101 is not limited to this.

  The thickness of the semiconductor chip 10 is, for example, 10 μm or more and 150 μm or less. More preferably, it is 20 μm or more and 100 μm or less.

  The semiconductor chip 12 is a semiconductor element having a TSV structure including a substrate (silicon substrate) 120 and a via 123 penetrating the substrate 120. A terminal 121 (second terminal a) is provided on one surface of the substrate 120, and a terminal 122 (second terminal b) is provided on the other surface. The terminals 121 and 122 are connected by vias 123 embedded in the substrate 120. The terminal 121 is a terminal connected to the semiconductor chip 10, and the terminal 122 is a terminal connected to another semiconductor chip.

  The via 123 is made of, for example, a metal such as copper or conductive polysilicon doped with impurities.

  The terminal 122 has a layer configuration similar to that of the terminal 101, for example.

  The terminal 121 has a solder layer 121A (first solder layer) on the surface. The terminal 121 has a structure in which, for example, a nickel layer is stacked on a copper layer, and a solder layer 121A is provided so as to cover the nickel layer. The material of the solder layer 121A is not particularly limited, and examples thereof include an alloy containing at least one selected from the group consisting of tin, silver, lead, zinc, bismuth, indium, and copper. Among these, an alloy containing at least one selected from the group consisting of tin, silver, lead, zinc and copper is preferable. The melting point of the solder layer 121A is preferably 110 ° C. or higher and 250 ° C. or lower, more preferably 170 ° C. or higher and 230 ° C. or lower.

  Note that it is only necessary that at least one of the terminals connected to each other has the solder layer 121A (the same applies to all the following embodiments). In the illustrated example, the terminal 121 includes the solder layer 121A, but the present invention is not limited to this. The terminal 101 may include the solder layer 121A instead of the terminal 121, or the terminal 101 and the terminal 121 Both may have a solder layer 121A.

  A resin layer 11 (first resin layer) is provided on the surface of the semiconductor chip 12 on the side where the terminals 121 of the substrate 120 are provided. The resin layer 11 covers the terminals 121 and the solder layer 121A. Such a resin layer 11 is for filling the gap between the semiconductor chips 10 and 12 after the semiconductor chips 10 and 12 are stacked.

  In addition, at least one of the base materials connected to each other only needs to have the resin layer 11 (the same applies to all the following embodiments). In the illustrated example, the semiconductor chip 12 has the resin layer 11, but the present invention is not limited to this. The semiconductor chip 10 may have the resin layer 11 instead of the semiconductor chip 12, or the semiconductor chip 10 Both the semiconductor chip 12 and the semiconductor chip 12 may have the resin layer 11.

  The resin layer 11 may be a layer containing a thermosetting resin, for example. Moreover, the resin layer 11 may contain a flux active compound. By including a flux compound, the connection reliability at the time of soldering can be improved.

  As the thermosetting resin, for example, epoxy resin, oxetane resin, phenol resin, (meth) acrylate resin, unsaturated polyester resin, diallyl phthalate resin, maleimide resin and the like can be used. These can be used individually or in mixture of 2 or more types. Among them, an epoxy resin excellent in curability and storage stability, heat resistance, moisture resistance, and chemical resistance of a cured product is preferably used. The content of the thermosetting resin in the resin layer 11 is preferably 30% by weight or more and 70% by weight or less.

  The flux active compound contained in the resin layer 11 is not particularly limited as long as it is used for solder joining, but either a carboxyl group or a phenol hydroxyl group, or a compound having both a carboxyl group and a phenol hydroxyl group is preferable. . The amount of the flux active compound in the resin layer 11 is preferably 1% by weight to 30% by weight, and particularly preferably 3% by weight to 20% by weight.

  When such a resin layer 11 is used, the oxide film on the surface of the solder layer or the terminal can be removed by the flux action at the time of solder joining.

  The resin layer 11 may contain an inorganic filler. By including an inorganic filler in the resin layer, it is possible to increase the minimum melt viscosity of the resin layer and to prevent a gap from being formed between the terminals. Here, examples of the inorganic filler include silica and alumina.

  Here, examples of the method of providing the resin layer 11 on the semiconductor chip 12 include the following methods. Note that a similar method can be adopted when the resin layer 11 is provided on the semiconductor chip 10.

(1) A film-like resin layer 11 is affixed to the semiconductor chip 12 after singulation.

(2) The film-like resin layer 11 is attached to the wafer before the plurality of semiconductor chips 12 are separated. Thereafter, the semiconductor chip 12 with the resin layer 11 is obtained by dicing the wafer.

(3) The resin layer 11 is formed by spin coating on the wafer before the semiconductor chips 12 are separated into individual pieces. Thereafter, the semiconductor chip 12 with the resin layer 11 is obtained by dicing the wafer.

  The thickness of the substrate 120 of the semiconductor chip 12 is 10 μm or more and 150 μm or less, more preferably 20 μm or more and 100 μm or less, and further 20 μm or more and 50 μm or less.

  The semiconductor chips 10 and 12 may have the same size or different sizes in plan view (plan view when viewed from the substrate surface side). In the illustrated example, the semiconductor chips 10 and 12 have the same size in plan view.

  After preparing the semiconductor chips 10 and 12 as described above, the semiconductor chip 10, the terminal 101 provided on the semiconductor chip 10 and the terminal 121 provided on the semiconductor chip 12 face each other through the resin layer 11, A laminated body in which the resin layer 11 and the semiconductor chip 12 are laminated is formed.

  At this time, alignment may be performed by confirming the alignment mark formed on the semiconductor chip 10 and the alignment mark formed on the semiconductor chip 12.

  Thereafter, a first load is applied to the laminated body with a pair of clamping members while heating the resin layer 11 at a temperature at which the resin layer 11 is melted and the solder layer 121A is not melted (temporary pressure bonding). As shown in FIG. 2B, a stacked body (first stacked body) in which the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12 are pressure-bonded in this order is formed.

  For example, the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12 are sandwiched (clamped) while being heated by a pair of the clamping members 52 and 55 with a built-in heater, and a load is applied. The layer 11 and the semiconductor chip 12 are pressure-bonded. You may perform the said heating and load in air | atmosphere under atmospheric pressure using a flip chip bonder. The curing of the resin layer 11 is performed so as not to proceed. That is, the heating temperature is such that the thermosetting resin of the resin layer 11 is not completely cured.

  If the load amount at this time is too large, the solder layer 121A is sandwiched between the terminal 101 and the terminal 121 and is strongly crushed, and as a result, it is greatly crushed. If the solder layer 121A is greatly crushed in this way, as described above, the height of the solder layer 121A becomes too low, and the resin between the terminals cannot be sufficiently discharged by subsequent main pressing.

  Therefore, in the present embodiment, this load amount is controlled so that the solder layer 121A is not crushed too much. The amount of load at this time can be arbitrarily determined as long as the solder layer 121A is not crushed by temporary crimping and the resin interposed between the terminals can be removed from the region by being crushed by permanent crimping.

  Note that, in the temporary press-bonded state (under heating and pressurization), as shown in FIG. 2B, the terminal 101, the solder layer 121A, and the terminal 121 may be directly connected. At this time, the solder layer 121 </ b> A may be sandwiched between the terminal 101 and the terminal 121 and may be slightly deformed, may be hardly deformed, or may not be deformed at all. It may be. In addition, the terminal 101, the solder layer 121 </ b> A, and the terminal 121 are not directly connected in the temporarily press-bonded state (under heating and pressure), and the resin layer 11 is slightly present between the terminal 101 and the solder layer 121 </ b> A. (Not shown).

<Opening step S20>
The opening step S20 is performed after the first stacking step S10. In release process S20, the load to the 1st laminated body by a pinching member is open | released.

  For example, as shown in FIG. 2B, the load is released from the stacked body of the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12 that are sandwiched between the pair of pressing members 52 and 55 and applied with a predetermined load.

  The present inventors have confirmed that the resin layer 11 can enter between the terminal 101 and the solder layer 121A by releasing the load (see FIG. 2C).

  After the step, it may be confirmed whether or not the position of the semiconductor chip 12 with respect to the semiconductor chip 10 after the temporary pressure bonding is accurate. The confirmation can be performed using, for example, an X-ray microscope or an infrared microscope.

<Second Laminating Step S30>
The second stacking step S30 is performed after the opening step S20. In the second lamination step S30, the first base material, the second resin layer, and the third base material having the third terminal are laminated so that the second b terminal and the third terminal face each other through the second resin layer. The second resin layer is melted and the second solder layer provided in at least one of the second b terminal and the third terminal is heated at a temperature at which the second solder layer is not melted. By applying the above load (temporary pressure bonding), the first laminated body, the second resin layer, and the second laminated body obtained by pressure bonding the third base material are formed.

  For example, a semiconductor chip 14 having the same configuration as the semiconductor chip 12 described above is prepared as the third base material. The semiconductor chip 14 includes a resin layer 13 (second resin layer) having the same configuration as the resin layer 11 included in the semiconductor chip 12. And in 2nd lamination process S30, a 3rd base material can be laminated on the 1st laminated body like 1st lamination process S10.

  That is, the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12 so that the terminal 122 (second b terminal) provided on the semiconductor chip 12 and the terminal 141 provided on the semiconductor chip 14 face each other through the resin layer 13. Then, a laminated body in which the resin layer 13 and the semiconductor chip 14 are laminated is formed.

  At this time, alignment may be performed by confirming the alignment mark formed on the semiconductor chip 12 and the alignment mark formed on the semiconductor chip 14.

  Thereafter, as shown in FIG. 2D, a load is applied to the laminated body with a pair of pressing members while heating the resin layer 13 at a temperature at which the resin layer 13 is melted and the solder layer 141A is not melted. (Temporary crimping), the resin layer 13 existing between the terminals 122 and 141 is removed from the region, and for example, a state as shown in FIG. 2D is obtained.

  For example, the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, and the semiconductor chip 14 are sandwiched (clamped) and heated while being heated by the pair of clamping members 52 and 55 with built-in heaters. Thereby, the semiconductor chip 12, the resin layer 13, and the semiconductor chip 14 are pressure-bonded. You may perform the said heating and load in air | atmosphere under atmospheric pressure using a flip chip bonder. It should be noted that the resin layers 11 and 13 are heated to such an extent that they do not proceed. That is, the heating temperature is such that the thermosetting resin of the resin layers 11 and 13 is not completely cured.

  If the amount of load at this time is too large, the solder layer 141A is sandwiched between the terminal 122 and the terminal 141 and strongly pressed, and as a result, it is greatly crushed. Similarly, the solder layer 121 </ b> A is sandwiched between the terminals 101 and 121 and strongly pressed, and as a result, is greatly crushed. If the solder layers 121A and 141A are greatly crushed as described above, the height of the solder layers 121A and 141A becomes too low as described above. become unable.

  Therefore, as in the first stacking step S10, this load amount is also controlled in this step so that the solder layers 121A and 141A are not crushed too much. The load amount at this time can be arbitrarily determined within a range in which the resin interposed between the terminals can be discharged from the region when the solder layers 121A and 141A are not crushed by temporary crimping and are crushed by the final crimping.

  Note that, in the temporarily press-bonded state (under heating and pressurization), the terminal 122, the solder layer 141A, and the terminal 141 may be directly connected as shown in FIG. Further, the terminal 101, the solder layer 121A, and the terminal 121 may be directly connected. At this time, the solder layer 121 </ b> A may be sandwiched between the terminal 101 and the terminal 121 and may be slightly deformed, may be hardly deformed, or may not be deformed at all. It may be. Similarly, the solder layer 141A may be sandwiched between the terminal 122 and the terminal 141 and may be slightly deformed, may be hardly deformed, or may not be deformed at all. It may be. In addition, the terminal 122, the solder layer 141A, and the terminal 141 are not directly connected in the pre-bonded state (under heating and pressurization), and the resin layer 13 is slightly present between the terminal 122 and the solder layer 141A. (Not shown). Similarly, the terminal 101, the solder layer 121A, and the terminal 121 may not be directly connected, and the resin layer 11 may be slightly present between the terminal 101 and the solder layer 121A (not shown).

  In the present embodiment, after the second lamination step S30, the second laminated body is released from the pinching member, and then a first joining step S40 described below is performed. When the present inventors release the second laminated body from the pinching member (release the load), the resin layers 11 and 13 are interposed between the terminal 101 and the solder layer 121A and between the terminal 122 and the solder layer 141A. It is confirmed that the vehicle can enter (see FIG. 2E).

  In addition, after the second stacking step S30 and before the first bonding step S40, the opening step S20 and the second stacking step S30 are set as one set, and a predetermined set is repeated, so that more substrates can be formed in a plurality of stages (designed You may form the laminated body laminated | stacked on matter. Here, after the second laminated body shown in FIG. 2 (E) is obtained, the second laminated body in which the four substrates are laminated is obtained by performing one set of the opening step S20 and the second laminated step S30. It is assumed that it was obtained (see FIG. 2F). In such a case, after the second second lamination step S30, the second laminated body is released from the pinching member, and then a first joining step S40 described below is performed. In such a case, the present inventors also release the second laminated body from the pinching member (release the load), between the terminal 101 and the solder layer 121A, between the terminal 122 and the solder layer 141A, and between the terminal 142 and It has been confirmed that the resin layers 11, 13, and 15 can enter between the solder layers 161A (see FIG. 2F).

  In the steps so far, the solder layers (solder layers 121A, 141A, 161A) located between the terminals are not melted, and the terminals 101, 121, the terminals 122, 141, and the terminals 142, 161 are Not soldered.

  Further, in the second stacked body, the side surfaces of the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, the semiconductor chip 14, the resin layer 15, and the semiconductor chip 16 may be smooth when viewed from above. Alternatively, the resin layers 11, 13, and 15 may protrude from the side surfaces of the semiconductor chips 10, 12, 14, and 16. Furthermore, for example, the semiconductor chip 16 or the semiconductor chip 10 may be smaller than other semiconductor chips.

  Moreover, the thickness of the resin layers 11, 13, and 15 is 5 micrometers or more and 100 micrometers or less, for example, More preferably, they are 10 micrometers or more and 50 micrometers or less. By setting the thickness to 5 μm or more, the resin layer can reliably cover the solder layer, and the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 can be easily connected by the flux activity of the resin layer. Moreover, by setting it as 100 micrometers or less, the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 can be easily connected. Furthermore, the curvature of the semiconductor chips 12, 14, and 16 due to curing shrinkage of the resin layer can be suppressed by setting the thickness to 100 μm or less.

<First joining step S40 (main pressure bonding)>
The first joining step S40 includes a pressing step and a holding step. The holding process is performed after the pressing process. By the pushing process, the resin layer interposed between the terminals is removed, and the terminals are connected via the solder layer. Then, in the holding step, the solder layer is melted and solder bonding between the terminals is performed.

  In the pressing step, the resin layers (resin layers 11, 13, 15) interposed between the base materials (semiconductor chips 10, 12, 14, 16) are melted and the solder layers (solder layers 121A, 121A, 141A, 161A) while applying heat to the laminated body 2 (second laminated body) at a temperature at which the laminated body 2 (second laminated body) is not melted, the resin layer interposed between the terminals is removed from the region by applying a third load with a pair of pressing members. Then, the terminal 101, the solder layer 121A, and the terminal 121 are directly connected, the terminal 122, the solder layer 141A, and the terminal 141 are directly connected, and the terminal 142, the solder layer 161A, and the terminal 161 are directly connected.

  As described above, the first stacking step S10 and the second stacking step S30 are controlled so that the deformation amount (crushing amount) of the solder layer (solder layers 121A, 141A, 161A) located between the terminals is small. Yes. Specifically, the solder layers (solder layers 121A, 141A, 161A) located between the terminals are sufficiently crushed by heating and pressurization under predetermined conditions in the first joining step S40, and the resin interposed between the terminals is removed. The deformation amount (the amount to be crushed) of the solder layers (solder layers 121A, 141A, 161A) in the first lamination step S10 and the second lamination step S30 is controlled so as to eliminate the region.

  For this reason, when the pressing step of the first joining step S40 is performed (immediately before performing), the solder layers (solder layers 121A, 141A, 161A) located between the terminals are sufficiently crushed by heating and pressurization in the pressing step. The height between the terminals is such that the resin interposed between the terminals can be removed from the region. As a result, the resin interposed between the terminals is discharged from between the terminals while the solder layers (first solder layer, second solder layer, etc.) located between the terminals are deformed by heating and pressurizing in the pressing process. Thus, the terminals are connected via the solder layer.

  In addition, the 3rd load of an indentation process is larger than both the 1st load in 1st lamination process S10, and the 2nd load in 2nd lamination process S30.

  The holding process is performed subsequent to the pushing process. Specifically, the holding step is continuously performed while maintaining the terminal-solder layer-terminal connection state formed by the pressing step. That is, the load applied to the second laminate between the pressurization to the second laminate in the pushing step and the pressurization to the second laminate in the holding step eliminates the terminal-solder layer-terminal connection state. It will not go down until it is done. In the holding step, the laminate 2 (second laminate) is heated and pressurized (fourth load) at a temperature at which the solder layers (solder layers 121A, 141A, 161A) located between the terminals are melted. Solder the terminals together.

  Here, in the first bonding step S40, the terminals are soldered together means the following. The second stacked body is heated to a melting point or higher of the solder layers 121A, 141A, 161A, and each solder layer 121A used for bonding between the semiconductor chips 10, 12, between the semiconductor chips 12, 14, and between the semiconductor chips 14, 16; 141A and 161A are melted, and the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are in physical contact with each other, and at least a part forms an alloy.

  This process can be realized by using, for example, the apparatus 5 shown in FIG. The device 5 includes a container 51 into which a fluid is introduced, and a pair of pinching members (hot plates 56 and 58) disposed in the container 51.

  The container 51 is a pressure container, and examples of the material of the container 51 include metals, and examples thereof include stainless steel, titanium, and copper.

  The hot plates 56 and 58 are press plates having a heater inside, and sandwich the laminate 2 placed above the hot plate 58 with the hot plates 56 and 58. A pin 54 is formed in the hot plate 58, and this pin 54 passes through a plate material (installation portion for installing the laminate 2) 57. The plate material 57 slides on the pins 54 and contacts the hot plate 58 when the laminated body 2 is clamped.

  The temperature of the hot plate 56 is set higher than the temperature of the hot plate 58. For example, the temperature of the hot plate 56 is 20 ° C. or more higher than the hot plate 58, the hot plate 56 has a temperature equal to or higher than the melting point of the solder layers 121A, 141A, 161A, and the hot plate 58 has the solder layers 121A, 141A, 161A. Less than the melting point.

  First, the hot plates 56 and 58 are heated to a predetermined temperature in advance. The plate member 57 is separated from the hot plate 58 and the laminate 2 is installed on the plate member 57. Next, a fluid is introduced into the container 51 through the pipe 511. As the fluid, gas is preferable, and examples thereof include air and inert gas (nitrogen gas, rare gas).

  Thereafter, the hot plate 56 is brought into contact with the laminate 2 while maintaining the state where the laminate 2 is pressurized with a fluid. Further, the plate material 57 is slid on the pins 54, and the laminated body 2 is clamped along the laminating direction by the hot plates 56 and 58. The laminated body 2 is heated to a temperature equal to or higher than the melting point of the solder layers 121A, 141A, and 161A, and solder bonding is performed between the terminals 101 and 121, between the terminals 122 and 141, and between the terminals 142 and 161.

  The amount of load when the laminate 2 is pressurized with a fluid is, for example, 15N or more and 45N or less, preferably 20N or more and 40N or less. In addition, pressurizing with a fluid refers to making the pressure of the atmosphere of the laminated body 2 higher than the atmospheric pressure by the applied pressure.

  The heating temperature for the laminated body 2 can be designed in a range equal to or higher than the melting point of the solder layers 121A, 141A, and 161A. When the melting points of the solder layers 121A, 141A, and 161A are different, the laminate 2 may be heated to a temperature higher than the melting point of the solder layer having the highest melting point.

  Thereafter, the hot plates 56 and 58 are separated from each other, and the fluid is further discharged from the container 51. The pressurization to the laminated body 2 by the fluid is stopped, and then the laminated body 2 is taken out from the container 51.

  Here, when the resin layers 11, 13, and 15 are not completely cured in the above processing using the apparatus shown in FIG. 3, the resin layers 11, 13 are then used using the apparatus 6 shown in FIG. 4. , 15 may be cured. When the resin layers 11, 13, and 15 are completely cured in the above process using the apparatus shown in FIG. 3, this process is unnecessary. The apparatus 6 has the same container 51 as the apparatus 5 and heats the laminated body 2 while pressurizing it with a fluid to cure the resin layers 11, 13, and 15. The same fluid as that used in the apparatus 6 can be used.

  As a method of heating the laminated body 2, there is a method of heating and pressurizing the laminated body 2 by putting a heated fluid into the container 51 from the pipe 511. Moreover, the laminated body 2 can also be heated by flowing the fluid from the pipe 511 into the container 51 and heating the container 51 in a pressurized atmosphere.

  The laminated body 2 is disposed in the container 51, a fluid is introduced, and the laminated body 2 is heated to a temperature equal to or higher than the curing temperature of the thermosetting resin of the resin layers 11, 13, 15 to cure the resin layers 11, 13, 15. To do. For example, heating is performed at 180 ° C. for 1 hour. Here, the curing temperature is the curing temperature of the resin layer, and refers to the temperature at which the thermosetting resin contained in the resin layer becomes a C-stage according to JISK6900.

  Note that the resin layers 11, 13, and 15 may be cured by putting a plurality of laminates 2 in the container 51 of the apparatus 6. In this way, productivity can be improved.

  In addition, 1st joining process S40 can also be performed using the same apparatus (example: clamping member 52, 55) as the apparatus used by 1st lamination process S10 and 2nd lamination process S30. In such a case, after the second lamination step S30 for laminating the last substrate, the heating and pressurization settings of the apparatus are changed while maintaining the state where a load is applied to the laminated body, One joining step S40 may be performed. For example, when three base materials are stacked, after the last third base material is stacked as shown in FIG. 2D, the state in which the stacked body is pressed by the pressing members 52 and 55 is maintained. The first joining step S40 may be performed continuously by changing the settings of the heating and pressurization of the apparatus as they are.

  As described above, the stacked body 2 is obtained in which the semiconductor chips 10 and 12, the semiconductor chips 12 and 14, and the semiconductor chips 14 and 16 are joined by soldering.

<Installation process S50>
The installation step S50 is performed after the first joining step S40. In the installation step S50, the plurality of second stacked bodies after the first bonding step S40 are installed on the fourth base material.

  First, as shown in FIG. 5A, as the fourth base material 18, for example, a resin substrate, a silicon substrate, a glass substrate, a ceramic substrate, or the like is prepared. Terminals (laminated body connection terminals) 181 are formed on the surface of the fourth base material 18. The terminal 181 is made of the same structure and material as the terminal 101, and has a solder layer 181A on the surface. The terminal 181 is connected to the semiconductor chip 16.

  Next, the resin layer 17 is provided on the surface of the prepared fourth base material 18 (not shown). The resin layer 17 is provided so as to cover the terminal 181. The resin layer 17 may be the same as the resin layers 11, 13, and 15, but may be different. For example, a paste-like no-flow type underfill material (NUF) may be used. In order to provide the resin layer 17 on a part of the surface of the substrate 18, it is preferable to apply a paste-like underfill material by dispensing or ink jet. Examples of such a no-flow type underfill material include those disclosed in Japanese Patent Application Laid-Open No. 2008-13710.

  After providing the resin layer 17 on the fourth base material 18, the laminate 2 (see FIG. 5B) is disposed on the resin layer 17. At this time, it arrange | positions so that the terminal 162 of the laminated body 2 may oppose the terminal 181 of the 4th base material 18 on both sides of the resin layer 17.

<Second joining step S60>
The second joining step S60 is performed after the installation step S50. In 2nd joining process S60, a 2nd laminated body and a 4th base material are joined.

  For example, as illustrated in FIG. 5C, the laminate 2, the resin layer, and the laminate 2, the resin layer 17, and the fourth base material 18 are clamped along the lamination direction with a pair of clamping members 41 and 42. 17. The fourth substrate 18 is heated to the melting point or higher of the solder layer 181A. At this time, the laminate 2, the resin layer 17, and the fourth base material 18 are sandwiched between the pair of sandwiching members 41 and 42, and the pair of sandwiching members 41 and 42 are heated, whereby the laminate 2 and the resin are heated. The layer 17 and the base material 18 are heated to the melting point or higher of the solder layer 181A. Thereby, the terminal 181 and the terminal 162 are soldered together. This joining step is performed using, for example, a flip chip bonder.

  Thereafter, the installation step S50 and the second bonding step S60 are repeated a plurality of times, and as shown in FIG. 5D, the structure 3 in which the plurality of laminated bodies 2 are laminated on the fourth base material 18 is obtained.

  Thereafter, the resin layer 17 of the structure 3 is cured as necessary. For example, the resin layer 17 can be cured using the apparatus 6 shown in FIG. The curing method is the same as the method described above, and the structure 3 is heated to a temperature equal to or higher than the curing temperature of the thermosetting resin of the resin layer 17 while pressing the structure 3 with a fluid to cure the resin layer 17. Do.

  By doing in this way, generation | occurrence | production of the void in the resin layer 17 can be prevented, and the generated void can be eliminated.

<Sealing process>
Next, the structure 3 is sealed. The sealing method may be potting, transfer molding, or compression molding.

  After that, for each stacked body 2, a plurality of semiconductor devices 1 shown in FIG. 5E can be obtained by cutting. In FIG. 5E, reference numeral 19 denotes a sealing material, and reference numeral 18A denotes a diced fourth base material 18. Further, when the semiconductor device 1 has a plurality of stacked bodies 2, the semiconductor device 1 may be cut for each unit of the semiconductor device 1. A dicing blade, a laser, a router, or the like can be used for cutting.

  In the method for manufacturing a laminate of the present embodiment described above, a plurality of base materials having terminals on the front surface or having terminals on both the front and back surfaces are laminated in a plurality of stages without performing solder bonding, It is possible to solve the problem of poor connection between terminals due to resin biting between terminals, which can occur in a technique in which solder bonding between a plurality of base materials (between terminals) is performed collectively.

  That is, in the present embodiment, the solder layer is controlled so as not to be crushed by temporary pressing, so that the height of the solder layer can be sufficiently ensured before the main pressing. For this reason, the solder layer is sufficiently crushed by the final press-bonding performed after a plurality of temporary press-bonds, the resin interposed between the terminals can be removed from the region, and the terminals can be connected via the solder layer. Then, by performing solder bonding while maintaining this state, the terminals can be solder-bonded with no resin interposed between the terminals, and a good connection between the terminals can be obtained.

(Second Embodiment)
In the present embodiment, the pressurizing / heating treatment (second laminating step S30) when laminating the last base material in the step of laminating a predetermined number of base materials and solder bonding between a plurality of base materials (between terminals) The pressurizing / heating treatment (first joining step S40) is performed continuously. That is, after the second lamination step S30, the first joining step S40 is continuously performed by changing the setting of the pinching member without releasing the load on the second stacked body by the pinching member. In addition, when doing in this way, the pressurization / heat processing in the pressing process of 1st joining process S40 can serve as the pressurization / heat processing of 2nd lamination process S30 which laminate | stacks the last base material. That is, the pressing step of the first joining step S40 can be performed without performing the pressurizing / heating treatment (second laminating step S30) when laminating the last substrate. If it does in this way, the pressing and heating process (2nd lamination process S30) at the time of laminating the last substrate and the pushing process of the 1st joining process S40 can be collectively performed by one processing.

  Since other configurations are the same as those of the first embodiment, description thereof is omitted here.

  The present embodiment can realize the same operational effects as the first embodiment, and can also simplify the process.

(Third embodiment)
In this embodiment, a plurality of stacked bodies are formed by stacking a predetermined number of base materials on a semiconductor wafer on which a plurality of semiconductor elements are formed, and then solder bonding is performed. Other configurations are the same as those in the first and second embodiments.

  FIG. 6 shows a flowchart showing an example of the processing flow of the laminate manufacturing method of the present embodiment. As shown in FIG. 6, the manufacturing method of the laminated body of this embodiment includes a first lamination step S10, an opening step S20, a second lamination step S30, a first joining step S40, and an individualization step S45. The installation step S50 and the second joining step S60.

  In the present embodiment, after the semiconductor chip (second base material) is stacked via the resin layer in the first region on the semiconductor wafer (first base material) in the same manner as in the first embodiment (first stacking) Step S10), the opening step S20 and the second stacking step S30 are performed in the same manner as in the first embodiment. Next, as in the first embodiment, a set including the opening step S20 and the second stacking step S30 is repeated a predetermined set, thereby obtaining a child stacked body in which semiconductor chips are stacked in a predetermined stage. And after performing the last 2nd lamination | stacking process S30 with respect to the said child laminated body (child laminated body formed in 1st area | region) (after laminating the last semiconductor chip), the said child laminated body is clamped member Release from. Thereafter, a semiconductor chip (second base material) is stacked on a second region different from the first region on the semiconductor wafer via a resin layer (first stacking step S10). Then, similar to the processing in the first region, a set including the opening step S20 and the second stacking step S30 is repeated a predetermined set, thereby obtaining a child stacked body having semiconductor chips stacked in a predetermined stage. The pinching member is configured to be able to pinch the child laminated body located in the first region and the child laminated body located in the second region individually, and when forming the child laminated body in the second region, The child laminated body located in one region is not pinched.

  After forming the child laminated body in the second region, the child laminated body located in the second region is released from the pinching member, and a process similar to the process for forming the child laminated body in the second region described above is performed a predetermined number of times (design Note) By repeating, a plurality of child laminated bodies are formed in a plurality of regions on the semiconductor wafer. And after forming the last child laminated body on the said semiconductor wafer, the state shown in Drawing 7 is obtained by releasing the last child laminated body from a pinching member. Then, 1st joining process S40 is performed. In the first joining step S40, for example, a plurality of child laminates 4 may be clamped together using a pair of clamping members having a large plane area. In addition, you may pinch with respect to the some laminated body 4 individually or for every predetermined number of laminated child bodies 4. FIG.

  After the first joining step S40, an individualization step S45 is performed. In the singulation step S45, the semiconductor wafer 10A (first base material) is singulated in units of 4 child stacks. Separation can be realized according to the prior art.

  Since other configurations are the same as those in the first and second embodiments, description thereof is omitted here.

  This embodiment can realize the same operational effects as those of the first and second embodiments. Further, productivity is increased as compared with the case of stacking in units of individual semiconductor chips. Moreover, when pinching is carried out collectively, since 1st joining process S40 needs only once, productivity becomes high.

  In addition, the process of stacking the semiconductor chips on the semiconductor wafer 10A includes the flow of forming another child stacked body 4 in another region after forming one child stacked body 4 as described above, A plurality of child stacked bodies 4 may be formed in parallel, such that a first-stage semiconductor chip is stacked in a plurality of regions and then a second-stage semiconductor chip is stacked in the plurality of regions. In such a case, after passing through the last second stacking step S30, the child stacked body on which the last semiconductor chip is stacked is released from the pinching member, whereby the state shown in FIG. 7 is obtained. Then, 1st joining process S40 is performed.

  In addition, the first stacking step S10, the opening step S20, the second stacking step S30, and the first bonding step S40 are performed in this order to form one or a plurality of child stacked bodies that have been subjected to solder bonding on one semiconductor wafer 10A. After that, the first stacking step S10, the opening step S20, the second stacking step S30, and the first bonding step S40 are performed in this order, and one or a plurality of the solder bonding is performed on other regions on the semiconductor wafer 10A. A child laminate may be newly formed. In addition, after 2nd lamination | stacking process S30, as a process after releasing a child laminated body from a pinching member, you may perform 1st joining process S40, or similarly to 2nd Embodiment, After the second stacking step S30, the first joining step S40 may be performed continuously by changing the setting of the pinching member without releasing the load on the child stacked body by the pinching member.

(Modification)
Also in the following modified examples, the same operational effects as those of the first to third embodiments can be realized.

  In each said embodiment, after forming the resin layer 17 on the base material 18, the laminated body 2 was installed on the base material 18, However, It is not restricted to this. For example, without providing the resin layer 17, the base material 18 and the laminated body 2 may be soldered and then sealed, and at the same time, an underfill may be filled between the base material 18 and the laminated body 2. In this case, what is called a mold underfill material is used, for example, a material disclosed in Japanese Patent Application Laid-Open Nos. 2003-12773 and 2003-277585 may be used.

  Furthermore, in each said embodiment, after comprising the laminated body 2 and hardening resin layer 11,13,15, the solder joining of the base material 18 and the laminated body 2 was implemented, but resin layer 11, Solder joining between the base material 18 and the laminated body 2 may be performed in a state where 13 and 15 are not completely cured. For example, the resin layers 11, 13, and 15 may be completely cured when sealing.

  Further, in each of the above embodiments, the laminated body 2 is solder-bonded to the base material 18 one by one and the plurality of laminated bodies 2 are provided on the base material 18. However, the present invention is not limited to this. For example, a plurality of laminates 2 may be placed on the base material 18 and then the plurality of laminates 2 may be soldered to the base material 18 simultaneously using the apparatus shown in FIG. More specifically, a resin layer 17 similar to the resin layers 11, 13, 15 is formed on the substrate 18. At this time, the resin layer 17 is provided so as to cover the terminal 181 of the substrate 18. Then, the laminated body 2 is mounted on the resin layer 17, and the base material 18 and the laminated body 2 are temporarily pressure-bonded through the molten resin layer 17. For example, using a flip chip bonder or the like, the substrate 18 and the laminate 2 are temporarily pressure-bonded by heating. This operation is repeated to temporarily press-bond the plurality of laminated bodies 2 to the base material 18. Thereafter, using the apparatus shown in FIG. 3, the plurality of laminates 2 are simultaneously solder-bonded to the base material 18. By doing in this way, manufacturing efficiency can be improved.

  Moreover, in each said embodiment, although the semiconductor chip 10, 12, 14, 16 was laminated | stacked and the laminated body 2 was comprised, it is not restricted to this. For example, as a semiconductor component, a wafer or a block body in which a plurality of semiconductor chips are formed is prepared, and a stacked body in which the semiconductor components are not solder-bonded by stacking them is prepared. Then, this laminated body is cut | disconnected, 1st joining process S40 may be performed similarly to each said embodiment, and it may laminate | stack on a base material after that and 2nd joining process S60 may be implemented.

  In addition, a wafer or block body in which a plurality of semiconductor chips are formed is prepared as a semiconductor component, and a stacked body in which the semiconductor components are not solder-bonded by stacking these is prepared. Thereafter, similarly to each of the embodiments described above, the first bonding step S40 of this laminated body is performed, and then cut. And the laminated body separated into pieces may be laminated | stacked on a base material, and 2nd joining process S60 may be implemented.

  Furthermore, in each said embodiment, although the semiconductor chip 10 shall not have a TSV structure, it is not restricted to this, It is good also as a semiconductor chip of a TSV structure.

Moreover, although each said embodiment demonstrated the example which laminates | stacks four base materials, it is not restricted to this. The number of substrates to be laminated can be selected within a range of 3 or more.
Hereinafter, examples of the reference form will be added.
1. A first base material having a first terminal, a first resin layer, and a second base material having a 2a terminal on the back surface thereof and a second base material having a second b terminal on the back surface thereof, the first terminal and the first 2a terminals are stacked so as to face each other with the first resin layer interposed therebetween, the first resin layer is melted, and at least one of the first terminal and the second a terminal is melted A first laminating step of forming a first laminate by applying a first load with a pair of clamping members while heating at a temperature that does not
After the first stacking step, an opening step of releasing a load on the first stack by the pinching member;
After the opening step, the second substrate having the first laminated body, the second resin layer, and the third terminal faces the second b terminal and the third terminal with the second resin layer interposed therebetween. And a pair of pressing members while heating at a temperature at which the second resin layer is melted and at least one of the second b terminal and the third terminal is not melted. A second stacking step of forming a second stack by applying a second load;
After the second lamination step, while heating the second laminated body at a temperature at which the first resin layer and the second resin layer melt and the first solder layer and the second solder layer do not melt. In addition, by applying a third load with a pair of clamping members, the resin layer interposed between the terminals is eliminated, and the first terminal, the first solder layer, and the second a terminal are directly connected, and The second b terminal, the second solder layer, and the third terminal are directly connected, and then the second stacked body is heated at a temperature at which the first solder layer and the second solder layer are melted. A first joining step of solder joining between the first terminal and the second a terminal and between the second b terminal and the third terminal by applying a load of
Have
In the first bonding step, the first resin layer and the second resin layer are melted and the second laminated body is heated at a temperature at which the first solder layer and the second solder layer are not melted. Manufacture of a laminate in which when the third load is applied by a pair of clamping members, the resin existing between the terminals is discharged from between the terminals while the first solder layer and the second solder layer are deformed. Method.
2. In the manufacturing method of the laminated body of Claim 1,
The third load is a method for manufacturing a laminated body, which is larger than both the first load and the second load.
3. In the method for producing a laminate according to 1 or 2,
The first to third base materials are all semiconductor components,
After the first joining step, an installation step of installing a plurality of the second laminated bodies on the fourth substrate;
A second joining step for joining the second laminate and the fourth substrate;
The manufacturing method of the laminated body which has further.
4). In the method for producing a laminate according to 1 or 2,
The first substrate is a wafer on which a plurality of semiconductor elements are formed, and the second and third substrates are both semiconductor components,
In the first stacking step, a plurality of the second substrates are stacked on the first substrate,
In the second stacking step, the third base material is stacked on each of the plurality of second base materials positioned on the first base material, so that the first base material Forming a plurality of child laminates including the second substrate and the third substrate;
In the first joining step, a method of manufacturing a laminated body in which solder joining is collectively performed on the plurality of child laminated bodies.
5. In the method for producing a laminate according to 1 or 2,
The first substrate is a wafer on which a plurality of semiconductor elements are formed, and the second and third substrates are both semiconductor components,
In the first stacking step, a plurality of the second substrates are stacked on the first substrate,
In the second stacking step, the third base material is stacked on each of the plurality of second base materials positioned on the first base material, so that the first base material Forming a plurality of child laminates including the second substrate and the third substrate;
In the first joining step, a method of manufacturing a laminated body in which solder joining is individually performed on the plurality of child laminated bodies.
6). In the method for producing a laminate according to 1 or 2,
The first substrate is a wafer on which a plurality of semiconductor elements are formed, and the second and third substrates are both semiconductor components,
A child obtained by laminating the second base material and the third base material on the first base material by performing the first stacking step, the opening step, the second stacking step, and the first joining step in this order. After forming the laminated body, the first base material step, the opening step, the second base material step, and the first joining step are performed in this order, and the second base material is formed in another region of the first base material. And the manufacturing method of the laminated body which forms the other child laminated body which laminated | stacked the said 3rd base material.
7). In the manufacturing method of the laminated body in any one of 4 to 6,
The manufacturing method of the laminated body which further has the singulation process which divides the said 1st base material provided with the said several child laminated body by which the said solder joint was made | formed into the said child laminated body unit.
8). In the manufacturing method of the laminated body in any one of 3 to 7,
The semiconductor component is a manufacturing method of a laminate which is a semiconductor chip having a TSV (Through Silicon Via) structure.
9. In the manufacturing method of the laminated body in any one of 1 to 8,
The said resin layer is a manufacturing method of the laminated body containing a flux active compound.
10. In the manufacturing method of the laminated body in any one of 1 to 9,
The first resin layer and the second resin layer are cured by heating in the first bonding step or by heating the second laminated body after the solder bonding after the first bonding step. A manufacturing method of a layered product.
11. In the manufacturing method of the laminated body in any one of 1 to 10,
Heating / pressurizing in which a second load is applied by a pair of clamping members while heating at a temperature at which the second solder layer included in at least one of the second b terminal and the third terminal does not melt in the second lamination step Processing
In the first bonding step performed after the second lamination step, the first resin layer and the second resin layer are melted, and the first solder layer and the second solder layer are not melted. A method for producing a laminate, which also serves as a heating and pressurizing treatment that eliminates a resin layer interposed between terminals by applying a third load with a pair of clamping members while heating the second laminate.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Laminated body 3 Structure 4 Child laminated body 5 Device 6 Device 10 Semiconductor chip 10A Semiconductor wafer 11 Resin layer 12 Semiconductor chip 13 Resin layer 14 Semiconductor chip 15 Resin layer 16 Semiconductor chip 17 Resin layer 18 Base material 18A Base material 19 Sealing material 41, 42 Clamping member 51 Container 52 Clamping member 54 Pin 55 Clamping member 56 Hot plate 57 Plate material 58 Hot plate 101 Terminal 120 Substrate 121 Terminal 121A Solder layer 122 Terminal 123 Via 141 Terminal 141A Solder layer 142 Terminal 161 Terminal 161A Solder layer 162 Terminal 181 Terminal 181A Solder layer 511 Piping

Claims (1)

A first base material having a first terminal, a first resin layer, and a second base material having a 2a terminal on the back surface thereof and a second base material having a second b terminal on the back surface thereof, the first terminal and the first 2a terminals are stacked so as to face each other with the first resin layer interposed therebetween, the first resin layer is melted, and at least one of the first terminal and the second a terminal is melted A first laminating step of forming a first laminate by applying a first load with a pair of clamping members while heating at a temperature that does not
After the first stacking step, an opening step of releasing a load on the first stack by the pinching member;
After the opening step, the second substrate having the first laminated body, the second resin layer, and the third terminal faces the second b terminal and the third terminal with the second resin layer interposed therebetween. And a pair of pressing members while heating at a temperature at which the second resin layer is melted and at least one of the second b terminal and the third terminal is not melted. A second stacking step of forming a second stack by applying a second load;
After the second lamination step, while heating the second laminated body at a temperature at which the first resin layer and the second resin layer melt and the first solder layer and the second solder layer do not melt. In addition, by applying a third load with a pair of clamping members, the resin layer interposed between the terminals is eliminated, and the first terminal, the first solder layer, and the second a terminal are directly connected, and The second b terminal, the second solder layer, and the third terminal are directly connected, and then the second stacked body is heated at a temperature at which the first solder layer and the second solder layer are melted. A first joining step of solder joining between the first terminal and the second a terminal and between the second b terminal and the third terminal by applying a load of
Have
In the first bonding step, the first resin layer and the second resin layer are melted and the second laminated body is heated at a temperature at which the first solder layer and the second solder layer are not melted. When the third load is applied by a pair of pressing members, the resin existing between the terminals is discharged from between the terminals while the first solder layer and the second solder layer are deformed .
The third load is a method for manufacturing a laminated body, which is larger than both the first load and the second load .

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