JP2014056954A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can improve productivity, and provide a semiconductor device having a structure capable of improving productivity.SOLUTION: A semiconductor device 1 comprises: a semiconductor element 16 having connection terminals 161; a semiconductor element 14 having connection terminals 142 which are opposite to the connection terminals 161 of the semiconductor element 16 and connected to the connection terminals 161 of the semiconductor element 16; and a resin layer 15 arranged between a semiconductor substrate 140 of the semiconductor element 14 and a semiconductor substrate 160 of the semiconductor element 16. In the semiconductor device 1, an outline of a region where a surface of the semiconductor element 14 on the semiconductor element 16 side and a surface of the semiconductor element 16 on the semiconductor element 14 side overlap each other lies within an outline of the semiconductor substrate 160 of the semiconductor element 16 in planar view from a lamination direction.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Conventionally, a semiconductor device in which a plurality of semiconductor elements are stacked is known (for example, see Patent Document 1). Patent Document 1 discloses a memory module in which a plurality of memory core chips are stacked.

JP 2006-301863 A

When stacking semiconductor elements, the present inventors arrange a resin layer between a pair of semiconductor elements, and then pressurize a stacked body including the pair of semiconductor elements and the resin layer along the stacking direction. Thought about how to connect.
And in such a manufacturing method, it turned out that the following subjects generate | occur | produce.
When the stacked body is pressed along the stacking direction, a part of the resin layer protrudes from between the semiconductor elements. The protruding resin layer adheres to the side surface of the semiconductor element, and further to the surface of the semiconductor element opposite to the other semiconductor element side. Thereby, a resin layer may adhere to the member which pinches | interposes a laminated body.

According to the present invention,
A first semiconductor element having a semiconductor substrate and a connection terminal provided on the semiconductor substrate;
A semiconductor substrate having connection terminals on the front and back surfaces and a second semiconductor element having a through via that connects between the connection terminals and penetrates the semiconductor substrate;
A laminate comprising a resin layer disposed between the semiconductor substrate of the first semiconductor element and the semiconductor substrate of the second semiconductor element;
In plan view from the stacking direction,
Inside the outer surface of the first semiconductor element, a surface of the first semiconductor element on the second semiconductor element side of the semiconductor substrate and a surface of the second semiconductor element on the first semiconductor element side of the semiconductor substrate. Preparing a laminate in which the outline of the overlapped region is located;
The stacked body is sandwiched from a stacking direction by a pair of pressing members, and the stacked body is pressed along the stacking direction to connect the connection terminal of the first semiconductor element and the first of the second semiconductor element. There is provided a method of manufacturing a semiconductor device including a step of joining one of the connection terminals located on the semiconductor element side.

According to this invention, the surface on the second semiconductor element side of the substrate of the first semiconductor element and the surface on the first semiconductor element side of the substrate of the second semiconductor element are arranged inside the outline of the first semiconductor element. A laminated body in which the outline of the overlapped region is located is prepared, and this laminated body is pressurized along the lamination direction.
In this pressing step, a part of the resin layer is extruded from a region where the surface of the substrate of the first semiconductor element on the second semiconductor element side and the surface of the substrate of the second semiconductor element on the first semiconductor element side overlap. Even if the outer surface of the first semiconductor element is located outside the outer region of the overlapped region, the extruded resin layer is formed on the side surface of the first semiconductor element, It can suppress adhering to the surface on the opposite side to the 2nd semiconductor element of a semiconductor element.
Thereby, it can prevent that the pinching member which pinches | interposes a laminated body will be contaminated, and can improve productivity of a semiconductor device.

Furthermore, according to the present invention, a semiconductor device manufactured by the above-described manufacturing method can also be provided.
That is, according to the present invention,
A first semiconductor element having a semiconductor substrate and connection terminals;
A semiconductor substrate having connection terminals formed on the front and back surfaces, and a through via that connects between the terminals and penetrates the semiconductor substrate, and one of the connection terminals is bonded to the connection terminal of the first semiconductor element A second semiconductor element,
A resin layer disposed between the semiconductor substrate of the first semiconductor element and the semiconductor substrate of the second semiconductor element;
In plan view from the stacking direction,
Inside the outer surface of the first semiconductor element, a surface of the first semiconductor element on the second semiconductor element side of the semiconductor substrate, and a surface of the second semiconductor element on the first semiconductor element side of the semiconductor substrate, It is also possible to provide a semiconductor device in which the outline of the overlapping region is located.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can improve productivity, and the semiconductor device of a structure which can improve productivity are provided.

(A) is sectional drawing along the lamination direction of the semiconductor device concerning 1st embodiment of this invention. FIG. 4B is a plan view from the stacking direction of the semiconductor devices. It is a figure which shows the manufacturing process of a semiconductor device. (A) is a top view which shows a part of wafer with which several semiconductor elements were integrated, (B) is sectional drawing which shows the state by which the resin layer was apply | coated to the wafer. (A), (B) is a figure which shows a mode that a wafer is diced. (A) is a figure which shows the manufacturing apparatus of a semiconductor device, (B) is a figure which shows the laminated body after being pinched with the manufacturing apparatus shown by (A). It is a figure which shows the manufacturing apparatus of a semiconductor device. (A)-(C) are figures which show the manufacturing process of a semiconductor device. (A), (B) is a figure which shows the manufacturing process of the semiconductor device concerning 2nd embodiment of this invention. It is a figure which shows a mode that a wafer is diced. (A), (B) is a figure which shows the manufacturing process of the semiconductor device concerning 3rd embodiment of this invention. (A), (B) is a figure which shows the manufacturing process of the semiconductor device concerning 4th embodiment of this invention. It is a figure which shows a mode that a wafer is diced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and detailed description thereof is appropriately omitted so as not to overlap.
(First embodiment)
First, an outline of the semiconductor device 1 of the present embodiment will be described with reference to FIG.
As shown in FIG. 1A, the semiconductor device 1 is opposed to the semiconductor element 16 having the connection terminal 161 and the connection terminal 161 of the semiconductor element 16 and is connected to the connection terminal 161 of the semiconductor element 16. And a resin layer 15 disposed between the substrate 140 of the semiconductor element 14 and the substrate 160 of the semiconductor element 16.
As shown in FIG. 1B, the semiconductor device 1 includes a semiconductor substrate 140 of the semiconductor element 140 on the outer side of the semiconductor element 16, that is, on the inner side of the outer side L <b> 4 of the substrate 160 in a plan view from the stacking direction. An outline L1 of a region where the surface on the element 16 side and the surface on the semiconductor element 14 side of the semiconductor substrate 160 of the semiconductor element 16 overlap is located.
Here, the surface of the semiconductor substrate 140 on the semiconductor element 16 side means a surface on which the connection terminal 142 connected to the terminal 161 of the semiconductor element 16 is provided.
The surface on the semiconductor element 14 side of the semiconductor substrate 160 means a surface on which a connection terminal 161 connected to the terminal 142 of the semiconductor element 14 is provided.

Next, the semiconductor device 1 of the present embodiment will be described in detail with reference to FIG.
The semiconductor device 1 includes a base 18A, a plurality of semiconductor elements 16, 14, 12, and 10 stacked on the base 18A, and resin layers 17, 15, 13, and 11. The resin layer 15 protrudes from between the substrate 160 of the semiconductor element 16 and the substrate 140 of the semiconductor element 14 and is accommodated in a space immediately above the outer peripheral portion of the substrate 160.
The resin layer 13 protrudes from between the substrate 140 of the semiconductor element 14 and the substrate 120 of the semiconductor element 12. And it is accommodated in the space immediately above the outer periphery of the substrate 160. Similarly, the resin layer 11 protrudes from between the substrate 120 of the semiconductor element 12 and the substrate 100 of the semiconductor element 10. And it is accommodated in the space immediately under the outer periphery of the substrate 100.

The base material 18A may be a resin substrate, or may be a silicon substrate or a ceramic substrate. Although not shown on the back surface of the base material 18A, for example, a terminal or the like is formed and is electrically connected to a terminal 181 provided on the front surface (surface on the semiconductor element 16 side) side.
The terminal 181 has a solder layer 181A on the surface. The connection terminal 181 has a structure in which, for example, a nickel layer is stacked on a copper layer, and a solder layer 181A is provided so as to cover the nickel layer.
The material of the solder layer 181A is not particularly limited, and examples thereof include an alloy containing at least one selected from the group consisting of tin, silver, lead, zinc, bismuth, indium, and copper. Among these, an alloy containing at least one selected from the group consisting of tin, silver, lead, zinc and copper is preferable. The melting point of the solder layer 181A is 110 to 250 ° C, preferably 170 to 230 ° C.

The semiconductor element 16 is disposed on the base material 18A. In the top view of the semiconductor device 1, the outline of the base material 18 </ b> A is outside the outline of the semiconductor element 16, and the planar shape viewed from the substrate surface side of the base material 18 </ b> A is larger than the planar shape of the semiconductor element 16. .
The semiconductor element 16 is a TSV structure semiconductor element having a substrate (semiconductor substrate, for example, a silicon substrate) 160 and a via 163 penetrating the substrate 160. An internal circuit or the like is built in the substrate 160. A terminal 161 is provided on one surface of the substrate 160, and a terminal 162 is provided on the other surface. The terminal 161 and the terminal 162 are connected by a via 163. The terminal 161 is a connection terminal connected to the semiconductor element 14, and the terminal 162 is a connection terminal connected to the terminal 181 of the base 18A.
The via 163 is made of, for example, a metal such as copper or conductive polysilicon doped with impurities.
For example, the terminal 162 has a structure in which a copper layer, a nickel layer, and a gold layer are laminated in this order from the substrate side. However, the structure of the terminal 162 is not limited to this.
The terminal 161 has a solder layer 161A on the surface. The structure of the terminal 161 is the same as that of the terminal 181. For example, a nickel layer is laminated on a copper layer, and a solder layer 161A similar to the solder layer 181A is provided so as to cover the nickel layer.

The terminal 181 of the base 18A and the terminal 162 of the semiconductor element 16 face each other and are soldered.
A resin layer 17 is disposed between the base material 18 </ b> A and the substrate 160 of the semiconductor element 16. The resin layer 17 surrounds the periphery of the terminal 181 and the terminal 162.

A semiconductor element 14 is disposed on the semiconductor element 16. The semiconductor element 14 is a semiconductor element having a TSV structure having a substrate (semiconductor substrate, for example, a silicon substrate) 140 and a via 143 penetrating the substrate 140. An internal circuit or the like is built in the substrate 140, and a terminal 141 is provided on one surface of the substrate 140, and a terminal 142 is provided on the other surface. The terminal 141 and the terminal 142 are connected by a via 143. The terminal 141 is a connection terminal connected to the semiconductor element 12, and the terminal 142 is a connection terminal connected to the terminal 161 of the semiconductor element 16.
The via 143 has the same structure and material as the via 163, and the terminal 142 has the same structure and material as the terminal 162. The terminal 141 has the same structure and material as the terminal 161. For example, a structure in which a nickel layer is stacked on a copper layer and a solder layer 141A similar to the solder layer 161A is provided so as to cover the nickel layer. It is.

  The terminal 142 of the semiconductor element 14 and the terminal 161 of the semiconductor element 16 face each other and are soldered. A resin layer 15 is disposed between the substrate 140 of the semiconductor element 14 and the substrate 160 of the semiconductor element 16. The resin layer 15 surrounds the periphery of the terminal 161 and the terminal 142.

The semiconductor element 12 is disposed on the semiconductor element 14. The semiconductor element 12 is a semiconductor element having a TSV structure having a substrate (semiconductor substrate, for example, a silicon substrate) 120 and a via 123 penetrating the substrate 120. An internal circuit or the like is built in the substrate 120. A terminal 121 is provided on one surface of the substrate 120, and a terminal 122 is provided on the other surface. The terminals 121 and 122 are connected by vias 123. The terminal 121 is a connection terminal connected to the semiconductor element 10, and the terminal 122 is a connection terminal connected to the terminal 141 of the semiconductor element 14.
The via 123 has the same structure and material as the via 163, and the terminal 122 has the same structure and material as the terminal 162. The terminal 121 has the same structure and material as the terminal 161. For example, the terminal 121 has a structure in which a nickel layer is laminated on a copper layer and a solder layer 121A similar to the solder layer 161A is provided so as to cover the nickel layer. is there.

  The terminal 122 of the semiconductor element 12 and the terminal 141 of the semiconductor element 14 face each other and are soldered. The resin layer 13 is disposed between the substrate 120 of the semiconductor element 12 and the substrate 140 of the semiconductor element 14. The resin layer 13 surrounds the periphery of the terminal 141 and the terminal 122.

A semiconductor element 10 is arranged on the semiconductor element 12. The semiconductor element 10 is provided with a terminal (terminal for connection to the semiconductor element 12) 101 on the surface of a semiconductor substrate 100 such as a silicon substrate. In the present embodiment, no via penetrating the substrate 100 is provided. An internal circuit or the like is built in the substrate 100. For example, the connection terminal 101 has a structure in which a copper layer, a nickel layer, and a gold layer are laminated in this order from the substrate side. However, the structure of the connection terminal 101 is not limited to this.
Further, no terminal is provided on the other substrate surface side of the semiconductor element 10.

  The terminal 121 of the semiconductor element 12 and the terminal 101 of the semiconductor element 10 face each other and are soldered. A resin layer 11 is disposed between the substrate 120 of the semiconductor element 12 and the substrate 100 of the semiconductor element 10. This resin layer 11 surrounds the periphery of the terminal 121 and the terminal 101.

The thickness of the substrate 120, 140, 160 of the semiconductor elements 12, 14, 16 as described above is 10 μm or more and 150 μm or less, more preferably 20 μm or more and 100 μm or less, and further 50 μm or less, and the substrate becomes very thin. Yes.
Further, the thickness of the substrate 100 of the semiconductor element 10 is not less than 10 μm and not more than 150 μm. More preferably, it is 20 μm or more and 100 μm or less.
Furthermore, in this embodiment, the semiconductor elements 10, 12, 14, and 16 are memory chips such as DRAM and SRAM, for example.
Here, although not shown, dicing lines surrounding the internal circuit region remain in a frame shape at the peripheral portions of the substrates 120, 140, and 160 of the semiconductor elements 12, 14, and 16. A semiconductor element is obtained by cutting a wafer in which a plurality of semiconductor elements are integrated along a dicing line. However, a dicing line remains on the substrate of each semiconductor element. In the present embodiment, the size and shape of the regions surrounded by the dicing lines of the respective substrates 120, 140, 160 are equal.
Further, the semiconductor elements 12, 14, and 16 may be semiconductor elements having the same function, or may be semiconductor elements having different functions. For example, the internal circuit of the semiconductor elements 12, 14, 16 may have the same layout.

  In the present embodiment, all of the substrates 100, 120, 140, and 160 of the semiconductor device 1 have a planar rectangular shape in plan view (top view) from the stacking direction, and a cross section along the stacking direction has a rectangular shape. is there. The substrate 160 of the semiconductor element 16 and the substrate 100 of the semiconductor element 10 have a larger planar size in plan view from the stacking direction than the substrates 120 and 140 of the other semiconductor elements 12 and 14.

The substrate 160 of the semiconductor element 16 and the substrate 100 of the semiconductor element 10 have the same planar size in plan view from the stacking direction, and the side surfaces of the substrates 160 and 100 are flush with each other.
In the present embodiment, the substrates 120 and 140 of the semiconductor elements 12 and 14 have the same planar size in a plan view from the stacking direction, and the side surfaces of the substrates 120 and 140 are flush.
In other words, the side surfaces of the substrates 100 and 160 are located outward from the side surfaces of the substrates 120 and 140, respectively, and the semiconductor element 10 in plan view along the stacking direction of the semiconductor elements 10, 12, 14, and 16 , 16, that is, inside the outlines of the substrates 100 and 160, the outlines of the semiconductor elements 12 and 14, that is, the outlines of the substrates 120 and 140 are located.
In the present embodiment, the entire outer peripheral edges of the substrates 100 and 160 are located outward from the outer peripheral edges of the substrates 120 and 140.

And in this embodiment, as shown in FIG.1 (B), in planar view from the lamination direction (planar view from the arrow direction of FIG. 1 (A)),
An outline L1 of a region where the surface of the substrate 160 of the semiconductor element 16 on the semiconductor element 14 side and the surface of the substrate 140 of the semiconductor element 14 on the semiconductor element 16 side overlap,
A contour L2 of a region where a surface of the substrate 140 of the semiconductor element 14 on the side of the semiconductor element 12 and a surface of the substrate 120 of the semiconductor element 12 on the side of the semiconductor element 14 overlap,
An outline L3 of a region where the surface of the semiconductor element 12 on the semiconductor element 10 side of the substrate 120 and the surface of the semiconductor element 10 on the semiconductor element 12 side of the substrate 100 overlap each other;
Are located inside the outline L4 without contacting the outline L4 of the substrate 100 and the substrate 160.
However, for example, one side surface of the substrate 160 may be a surface position with the side surface of the substrate 140, and the other side surface of the substrate 160 may be positioned outward from the other side surface of the substrate 140.
Here, the distance l between the outer contour L4 of the substrate 100 and the substrate 160 and the outer contours L1 to L3 in a plan view from the semiconductor element stacking direction depends on the composition of the resin layers 11, 13, 15 and the manufacturing conditions. For example, it is 2.5 μm to 2.5 mm.
By setting the distance l in this way, for example, it is possible to reliably prevent the resin layer 11 from adhering to the side surface of the substrate 100 or the resin layer 15 from adhering to the side surface of the substrate 160.

  Further, in the semiconductor device 1, as illustrated in FIG. 1A, the outer peripheral portion of the substrate 100 and the outer peripheral portion of the substrate 160 are opposed to each other, and between the outer peripheral portion of the substrate 100 and the outer peripheral portion of the substrate 160. In this space, a part of the resin layer 17, a part of the resin layer 15, a part of the resin layer 13, and a part of the resin layer 11 are located.

Next, the resin layers 11, 13, 15, and 17 will be described.
The resin layers 11, 13, 15, and 17 each include a thermosetting resin and a flux active compound.
As the thermosetting resin, for example, epoxy resin, oxetane resin, phenol resin, (meth) acrylate resin, unsaturated polyester resin, diallyl phthalate resin, maleimide resin and the like can be used. These can be used individually or in mixture of 2 or more types.
Among them, an epoxy resin excellent in curability and storage stability, heat resistance, moisture resistance, and chemical resistance of a cured product is preferably used. The content of the thermosetting resin in the resin layers 11, 13, 15 and 17 is preferably 30% by weight or more and 70% by weight or less.

  The resin layers 11, 13, 15, and 17 are resin layers that have an action of removing an oxide film on the surface of the solder layer and the terminal during solder joining. Since the resin layers 11, 13, 15, and 17 have a flux action, the oxide film covering the surface of the solder and the terminals is removed, so that solder bonding can be performed. In order for the resin layers 11, 13, 15, and 17 to have a flux action, the resin layers 11, 13, 15, and 17 need to contain a flux active compound. The flux active compound contained in the resin layers 11, 13, 15, and 17 is not particularly limited as long as it is used for solder bonding, but is either a carboxyl group or a phenol hydroxyl group, or a carboxyl group and a phenol hydroxyl group. A compound comprising both of these is preferred.

  The amount of the flux active compound in the resin layers 11, 13, 15 and 17 is preferably 1 to 30% by weight, particularly preferably 3 to 20% by weight.

  Examples of the flux active compound having a carboxyl group include aliphatic acid anhydrides, alicyclic acid anhydrides, aromatic acid anhydrides, aliphatic carboxylic acids, and aromatic carboxylic acids.

  Examples of the aliphatic acid anhydride related to the flux active compound having a carboxyl group include succinic anhydride, polyadipic acid anhydride, polyazeline acid anhydride, polysebacic acid anhydride, and the like.

  Examples of alicyclic acid anhydrides related to flux active compounds having a carboxyl group include methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylhymic anhydride, hexahydrophthalic anhydride, tetrahydrophthalic anhydride, trialkyltetrahydro Any of phthalic anhydride, methylcyclohexene dicarboxylic acid anhydride and the like can be mentioned.

  Aromatic acid anhydrides related to flux active compounds having a carboxyl group include phthalic anhydride, trimellitic anhydride, pyromellitic anhydride, benzophenone tetracarboxylic anhydride, ethylene glycol bistrimellitate, glycerol tris trimellitate, etc. Any of these may be mentioned.

Examples of the aliphatic carboxylic acid related to the flux active compound having a carboxyl group include compounds represented by the following general formula (I), formic acid, acetic acid, propionic acid, butyric acid, valeric acid, pivalic acid caproic acid, caprylic acid, lauric acid , Myristic acid, palmitic acid, stearic acid, acrylic acid, methacrylic acid, crotonic acid, oleic acid, fumaric acid, maleic acid, oxalic acid, malonic acid, oxalic acid and the like.
_{HOOC- (CH 2) n -COOH (} I)
(In the formula (I), n represents an integer of 0 or more and 20 or less.)

  Aromatic carboxylic acids related to flux active compounds with carboxyl groups include benzoic acid, phthalic acid, isophthalic acid, terephthalic acid, hemimellitic acid, trimellitic acid, trimesic acid, merophanic acid, planitic acid, pyromellitic acid, merit Acid, triyl acid, xylyl acid, hemelic acid, mesitylene acid, prenylic acid, toluic acid, cinnamic acid, salicylic acid, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2,5-dihydroxy) Benzoic acid), 2,6-dihydroxybenzoic acid, 3,5-dihydroxybenzoic acid, gallic acid (3,4,5-trihydroxybenzoic acid), 1,4-dihydroxy-2-naphthoic acid, 3,5 -Naphthoic acid derivatives such as dihydroxy-2-naphthoic acid, phenolphthaline, diphenol Like any of the etc. is.

  Among these flux active compounds having a carboxyl group, there is a good balance between the activity of the flux active compound, the amount of outgas generated when the resin layer is cured, and the elastic modulus and glass transition temperature of the cured resin layer. The compound represented by the general formula (I) is preferable. And among the compounds shown by said general formula (I), while the compound whose n in Formula (I) is 3-10 can suppress that the elasticity modulus in the resin layer after hardening increases. In particular, it is preferable in that the adhesiveness can be improved.

Among the compounds represented by the general formula (I), examples of the compound in which n in the formula (I) is 3 to 10 include, for example, n = 3 glutaric acid (HOOC— (CH ₂ ) ₃ —COOH), n = 4 adipic acid (HOOC— (CH ₂ ) ₄ —COOH), n = 5 pimelic acid (HOOC— (CH ₂ ) ₅ —COOH), n = 8 sebacic acid (HOOC— (CH ₂ ) ₈ -COOH) and n = 10 for HOOC- _{(CH 2)} any such 10 -COOH and the like.

  Examples of the flux active compound having a phenolic hydroxyl group include phenols. Specifically, for example, phenol, o-cresol, 2,6-xylenol, p-cresol, m-cresol, o-ethylphenol, 2 , 4-xylenol, 2,5 xylenol, m-ethylphenol, 2,3-xylenol, meditol, 3,5-xylenol, p-tertiarybutylphenol, catechol, p-tertiaryamylphenol, resorcinol, p-octylphenol, Monomers containing phenolic hydroxyl groups such as p-phenylphenol, bisphenol A, bisphenol F, bisphenol AF, biphenol, diallyl bisphenol F, diallyl bisphenol A, trisphenol, tetrakisphenol Phenol novolak resins, o- cresol novolak resin, bisphenol F novolak resins, or such as bisphenol A novolac resins.

  A compound having either a carboxyl group or a phenol hydroxyl group as described above or a compound having both a carboxyl group and a phenol hydroxyl group is taken in three-dimensionally by reaction with a thermosetting resin such as an epoxy resin.

Therefore, from the viewpoint of improving the formation of a three-dimensional network of the epoxy resin after curing, the flux active compound is preferably a flux active curing agent having a flux action and acting as a curing agent for the epoxy resin. Examples of the flux active curing agent include, in one molecule, two or more phenolic hydroxyl groups that can be added to an epoxy resin, and one or more carboxyls directly bonded to an aromatic group that exhibits a flux action (reduction action). And a compound having a group. Such flux active curing agents include 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2,5-dihydroxybenzoic acid), 2,6-dihydroxybenzoic acid, 3,4- Benzoic acid derivatives such as dihydroxybenzoic acid and gallic acid (3,4,5-trihydroxybenzoic acid); 1,4-dihydroxy-2-naphthoic acid, 3,5-dihydroxy-2-naphthoic acid, 3,7- Examples thereof include naphthoic acid derivatives such as dihydroxy-2-naphthoic acid; phenolphthaline; and diphenolic acid. These may be used alone or in combination of two or more.
Especially, in order to make the joining between terminals favorable, it is particularly preferable to use phenolphthaline.

Moreover, 1-30 weight% is preferable and, as for the compounding quantity of a flux active hardening | curing agent in a resin layer, 3-20 weight% is especially preferable. When the blending amount of the flux active curing agent in the resin layer is within the above range, the flux activity of the resin layer can be improved, and the thermosetting resin and the unreacted flux active curing agent are contained in the resin layer. Is prevented from remaining.
Moreover, the resin layer may contain the inorganic filler. By including an inorganic filler in the resin layer, it is possible to increase the minimum melt viscosity of the resin layer and to prevent a gap from being formed between the terminals. Here, examples of the inorganic filler include silica and alumina.

  Further, the semiconductor device 1 has a sealing material 19 as shown in FIG. The sealing material 19 covers the outer periphery of the laminate 2 composed of the semiconductor elements 16, 14, 12, 10 and the resin layers 17, 15, 13, 11.

Next, a method for manufacturing the semiconductor device 1 as described above will be described. This will be described with reference to FIGS.
First, an outline of a method for manufacturing the semiconductor device 1 of the present embodiment will be described.
The manufacturing method of the semiconductor device 1 of this embodiment is as follows.
A semiconductor element 16;
A resin layer 15;
The substrate 140 on which the connection terminals 141 and 142 are formed on the front and back surfaces and the through vias 143 that connect between the connection terminals 141 and 142 and penetrate the substrate 140 are sandwiched between the semiconductor element 16 and the resin layer 15. And a laminated body 2 including the semiconductor elements 14 arranged opposite to each other,
In plan view from the stacking direction,
A surface of the substrate 160 of the semiconductor element 16 on the side of the semiconductor element 14 (that is, a surface provided with the terminal 161) inside the outline L4 (see FIG. 1B) of the substrate 160 of the semiconductor element 16, and the semiconductor element 14 A step of preparing a stacked body 2 in which an outline L1 (see FIG. 1B) of a region where the surface of the substrate 140 on the side of the semiconductor element 16 (that is, the surface provided with the terminals 142) overlaps is positioned;
A step of sandwiching the stacked body 2 from the stacking direction by the pair of pressing members 52 and 55, pressurizing the stacked body 2 along the stacking direction, and bonding the semiconductor elements 16 and 14.

Next, a method for manufacturing the semiconductor device 1 will be described in detail.
(Process for preparing a laminate)
As shown in FIG. 2A, a semiconductor element 10, a semiconductor element 12 with a resin layer 11, a semiconductor element 14 with a resin layer 13, and a semiconductor element 16 with a resin layer 15 are prepared.
Here, the semiconductor element 12 with the resin layer 11, the semiconductor element 14 with the resin layer 13, and the semiconductor element 16 with the resin layer 15 are prepared as follows.
First, as shown in FIG. 3A, a plurality of semiconductor elements 12 are formed, and an integrated wafer W1 is prepared.
Similarly, a plurality of semiconductor elements 14 are formed and an integrated wafer W2 is prepared.
Further, a plurality of semiconductor elements 16 are similarly formed, and an integrated wafer W3 is prepared.
A dicing line D is formed on each of the wafers W1 to W3, and the patterns of the dicing lines D (the width, the number and the interval of the dicing lines D) are the same for all the wafers W1 to W3.
Then, as shown in FIG. 3B, a resin layer 11A to be the resin layer 11 is provided on the surface of the wafer W1. The resin layer 11A covers the entire surface of the wafer W1, and is provided so as to cover the terminals 121 of the semiconductor elements 12 of the wafer W1.
Similarly, a resin layer 13A to be the resin layer 13 is provided on the wafer W2. The resin layer 13A covers the entire surface of the wafer W2, and is provided so as to cover the terminals 141 of the semiconductor elements 14 of the wafer W2.
Further, a resin layer 15A to be the resin layer 15 is provided on the wafer W3. The resin layer 15A covers the entire surface of the wafer W3, and is provided so as to cover the terminals 161 of the semiconductor elements 16 of the wafer W3.
In addition, as a method of providing the resin layer 11A on the wafer W1, the film-like resin layer 11A may be attached to the wafer W1, and a varnish-like resin composition that becomes the resin layer 11A is spin-coated on the wafer W1. The resin layer 11A may be provided on the wafer W1 by applying and drying.
For the resin layers 13A and 15A, the resin layers can be provided on the wafers W2 and W3 in the same manner.

Thereafter, as shown in FIG. 4, the wafers W <b> 1 to W <b> 3 are cut along the dicing line D, respectively.
Here, as shown in FIG. 4A, when dicing the wafers W1 and W2, a blade B1 having a wide blade edge is used. By using the blade B1 having a wide blade edge in this way, the semiconductor elements 12 and 14 having a small planar size can be obtained.
The blade B1 has a ring shape, and the outer peripheral edge is a cutting edge. Although the width of the blade edge of the blade B1 depends on the width of the dicing line D, it can be, for example, 0.015 mm to 5 mm.
On the other hand, as shown in FIG. 4B, when dicing the wafer W3, a blade B2 having a narrower blade edge than the blade B1 is used. This blade B2 is also ring-shaped, and the outer peripheral edge is the cutting edge. By using the blade B2 having a narrow blade edge in this way, the semiconductor element 16 having a large planar size can be obtained.
In the case where the semiconductor element 12 and the semiconductor element 14 are elements having the same function, and the elements having the same internal circuit layout and the like, among the plurality of semiconductor elements obtained by dicing the wafer W1, Any one may be used as the semiconductor element 12 and any other may be used as the semiconductor element 14.

In the semiconductor element 12 with the resin layer 11 manufactured as described above, the resin layer is coated so as to cover the entire surface of one surface of the substrate 120 of the semiconductor element 12 (the surface on the semiconductor element 10 side of the stacked body 2). 11 is provided, and the side surface of the resin layer 11 and the side surface of the substrate 120 of the semiconductor element 12 are flush with each other.
The same applies to the semiconductor element 14 with the resin layer 13 and the semiconductor element 16 with the resin layer 15. That is, the resin layer 13 is provided so as to cover the entire surface of one surface of the substrate 140 of the semiconductor element 14 (the surface on the semiconductor element 12 side of the stacked body 2). The side surface of the substrate 140 is flush with the side surface.
Furthermore, the resin layer 15 is provided so as to cover the entire surface of one surface of the substrate 160 of the semiconductor element 16 (the surface on the semiconductor element 14 side of the stacked body 2). The side surface of the substrate 160 is flush.
Further, as described above, the resin layer 11 provided on the semiconductor element 12, the resin layer 13 provided on the semiconductor element 14, and the resin layer 15 provided on the semiconductor element 16 are all in a B-stage state. The minimum melt viscosity at 60 to 150 ° C. of each of the resin layers 11, 13 and 15 is preferably 0.1 to 10,000 Pa · s.
By doing in this way, it can prevent that each resin layer 11, 13, 15 protrudes from between semiconductor elements excessively in the process of solder-joining terminals of a back | latter stage.
In addition, the minimum melt viscosity of each resin layer 11, 13, 15 can be measured as follows.
Each resin layer having a thickness of 100 μm is measured with a viscoelasticity measuring device (Rheo Stress RS-10, manufactured by HAAKE Co., Ltd.) at a heating rate of 10 ° C./min, a frequency of 0.1 Hz, and constant strain-stress detection. And the minimum melt viscosity in 60-150 degreeC is detected.

Next, as illustrated in FIG. 2B, the stacked body 2 including the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, the semiconductor element 14, the resin layer 15, and the semiconductor element 16 is prepared. .
First, the surface of the semiconductor element 10 on which the terminal 101 is formed and the resin layer 11 provided on the semiconductor element 12 face each other, and the semiconductor element 12 is stacked on the semiconductor element 10 with the resin layer 11 interposed therebetween.
At this time, alignment is performed by confirming the alignment mark formed on the semiconductor element 10 and the alignment mark formed on the semiconductor element 12.
Thereafter, the semiconductor element 10, the resin layer 11, and the semiconductor element 12 are heated to bond the semiconductor element 10 and the semiconductor element 12 through the resin layer 11 in a semi-cured state (B stage). At this time, by sandwiching the semiconductor element 10, the resin layer 11, and the semiconductor element 12 by a pair of clamping members (not shown) with a built-in heater, the semiconductor element 10, the resin layer 11, and the semiconductor element 12 are heated, The semiconductor element 10 and the semiconductor element 12 can be bonded together by pressing between the pair of pressing members and applying a load. For example, using a flip chip bonder, the semiconductor element 10 and the semiconductor element 12 are bonded via the resin layer 11 in the atmosphere under atmospheric pressure. The heating temperature at this time is not particularly limited as long as the thermosetting resin of the resin layer 11 is not completely cured, but is preferably lower than the curing temperature of the thermosetting resin. For example, the heating temperature can be 80 to 220 ° C. Further, the clamping time may be 1 to 5 seconds.
Whether or not the position of the semiconductor element 12 relative to the semiconductor element 10 after bonding can be accurately confirmed using, for example, an X-ray microscope or an infrared microscope.

Next, the surface of the semiconductor element 12 on which the terminal 122 is provided and the resin layer 13 are opposed to each other, and the semiconductor element 14 is stacked on the semiconductor element 12 with the resin layer 13 interposed therebetween.
At this time, alignment is performed by confirming the alignment mark formed on the semiconductor element 12 and the alignment mark formed on the semiconductor element 14.
Thereafter, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, and the semiconductor element 14 are heated, and the semiconductor element 12 and the semiconductor element 14 are moved through the semi-cured (B stage) resin layer 13. Glue. At this time, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, and the semiconductor element 14 are sandwiched and heated by a pair of sandwiching members with a built-in heater, and sandwiched by the pair of sandwiching members, The semiconductor element 12 and the semiconductor element 14 can be bonded by applying a load. For example, the semiconductor element 12 and the semiconductor element 14 are bonded in the atmosphere under atmospheric pressure using a flip chip bonder. The heating temperature at this time is not particularly limited as long as the thermosetting resin of the resin layer 13 is not completely cured, but is preferably lower than the curing temperature of the thermosetting resin. For example, the heating temperature can be 80 to 220 ° C. Further, the clamping time may be 1 to 5 seconds.
Whether or not the position of the semiconductor element 14 with respect to the semiconductor element 12 after bonding can be accurately confirmed using, for example, an X-ray microscope or an infrared microscope.

Next, as shown in FIG. 2B, the surface of the semiconductor element 14 provided with the terminals 142 is opposed to the resin layer 15, and the semiconductor element 16 is placed on the semiconductor element 14 via the resin layer 15. Laminate.
At this time, alignment is performed by confirming the alignment mark formed on the semiconductor element 14 and the alignment mark formed on the semiconductor element 16.
Thereafter, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, the semiconductor element 14, the resin layer 15, and the semiconductor element 16 are heated, and the semi-cured state (B stage) through the resin layer 15, The semiconductor element 14 and the semiconductor element 16 are bonded. At this time, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, the semiconductor element 14, the resin layer 15, and the semiconductor element 16 are sandwiched and heated by a pair of pressing members having a built-in heater. The semiconductor element 14 and the semiconductor element 16 can be bonded together by applying a load with a pinching member. For example, the semiconductor element 14 and the semiconductor element 16 are bonded in the atmosphere under atmospheric pressure using a flip chip bonder. The heating temperature at this time is not particularly limited as long as the thermosetting resin of the resin layer 15 is not completely cured, but is preferably lower than the curing temperature of the thermosetting resin. For example, the heating temperature can be 80 to 220 ° C. Further, the clamping time may be 1 to 5 seconds.
Whether or not the position of the semiconductor element 16 with respect to the semiconductor element 14 after bonding can be accurately confirmed using, for example, an X-ray microscope or an infrared microscope.
The laminated body 2 is obtained by the above. In the laminate 2 thus obtained, the resin layers 11, 13, and 15 are in a semi-cured state and are not completely cured.

In this step, the solder layers 121A, 141A, 161A are not melted, and the terminals 101, 121, the terminals 122, 141, and the terminals 142, 161 are not soldered. The terminals 101 and 121 may be in physical contact with each other, and the resin of the resin layer 11 may be interposed between the terminals 101 and 121. The same applies to the terminals 122 and 141 and the terminals 142 and 161.
Moreover, in this process, the clamping pressure at the time of bonding semiconductor elements is 0.01 to 0.2 MPa, for example.

In the stacked body 2 obtained by the process as described above, the side surfaces of the semiconductor elements 10 and 16 are positioned outside the side surfaces of the semiconductor elements 12 and 14.
Further, in the plan view from the stacking direction of the stacked body 2, the outlines of the resin layers 11 and 13 are located inside the outline of the substrate 100 of the semiconductor element 10 and the outline of the substrate 160 of the semiconductor element 16.

(First joining process)
Next, as shown in FIG. 2C, the laminate 2 obtained through the above steps is heated to perform solder bonding between the terminals 101 and 121, between the terminals 122 and 141, and between the terminals 142 and 161. .
Here, in the first bonding step, the terminals are soldered together means the following. The laminated body 2 is heated to the melting point or higher of the solder layers 121A, 141A, 161A, and the solder layers 121A, 141A used for bonding between the semiconductor elements 10, 12, between the semiconductor elements 12, 14, and between the semiconductor elements 14, 16 are used. 161A is melted, the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are in physical contact, and at least a part forms an alloy.

Here, for example, the apparatus 5 shown in FIG. 5 is used. The device 5 includes a container 51 into which a fluid is introduced, and a pair of hot plates 52 and 53 disposed in the container 51.
The container 51 is a pressure container, and examples of the material of the container 51 include metals, and examples thereof include stainless steel, titanium, and copper.
The hot plates 52 and 53 are press plates having a heater inside, and sandwich the laminated body 2 installed above the hot plate 53 with the hot plates 52 and 53. A pin 54 is formed in the hot plate 53, and the pin 54 passes through a plate material (installation portion for installing the laminate 2) 55. The plate material 55 slides on the pins 54 and contacts the hot plate 53 when the laminated body 2 is clamped.
The temperature of the hot plate 52 is set higher than the temperature of the hot plate 53. For example, the temperature of the hot plate 52 is 20 ° C. or more higher than that of the hot plate 53, the hot plate 52 has a temperature equal to or higher than the melting point of the solder layers 121A, 141A, and 161A. Less than the melting point.
By setting the temperature of the hot plate 53 to be lower than that of the hot plate 52 in this way, after the laminated body 2 is installed in the apparatus 5, until the laminated body 2 is pressurized with a predetermined pressure with a fluid. In addition, the resin layers 11, 13, 15 of the laminate 2 are softened, and the voids in the resin layers 11, 13, 15 are prevented from becoming large. On the other hand, by keeping the temperature of the hot plate 52 higher than that of the hot plate 53, after the laminated body 2 is clamped, the laminated body 2 can be raised to a predetermined temperature in a relatively short time. .
When the plate material 55 is disposed close to the hot plate 52, the temperature of the hot plate 52 may be set lower than the temperature of the hot plate 53.

First, the hot plates 52 and 53 are heated to a predetermined temperature in advance. The plate material 55 is separated from the hot plate 53, and the laminate 2 is installed on the plate material 55. Thus, by separating the plate material 55 on which the stacked body 2 is installed from the pair of hot plates 52 and 53, the heat from the hot plates 52 and 53 is hardly applied to the stacked body 2. For this reason, the resin layers 11, 13, and 15 of the laminate 2 are softened until the laminate 2 is pressurized with a predetermined pressure with a fluid after the laminate 2 is installed in the apparatus 5. , 13 and 15 are prevented from becoming large.
Next, a fluid is introduced into the container 51 through the pipe 511. As the fluid, gas is preferable, and examples thereof include air, inert gas (nitrogen gas, rare gas) and the like.
Thereafter, the hot plate 52 is brought into contact with the laminate 2 while maintaining the state where the laminate 2 is pressurized with a fluid. Further, the plate material 55 is slid on the pins 54, and the laminate 2 is clamped by the hot plates 52 and 53 along the lamination direction. The laminate 2 is directly sandwiched between the hot plate 52 and the plate material 55. The multilayer body 2 is heated to a temperature equal to or higher than the melting point of the solder layers 121A, 141A, and 161A (for example, 230 to 280 ° C.), and solder bonding is performed between the terminals 101 and 121, between the terminals 122 and 141, and between the terminals 142 and 161. . By sandwiching the laminate 2, even when resin is sandwiched between the terminals 101 and 121 (between the terminals 122 and 141 and between the terminals 142 and 161), the resin is removed and the terminals 101 and 121 (terminals 122) 141, terminals 142, 161) can be brought into contact with each other reliably and can be soldered stably. At this time, the laminate 2 is sandwiched between the hot plate 52 and the plate material 55, and the pressure (squeezing pressure) applied to the laminate 2 is, for example, 0.01 to 0.5 MPa. The clamping time is 5 to 12 seconds.

In this step, the resin layer 11 is heated to reduce the viscosity of the resin layer 11. Then, the laminated body 2 is sandwiched between the hot plate 52 and the plate material 55, so that the resin layer 11 disposed between the substrate 100 of the semiconductor element 10 and the substrate 120 of the semiconductor element 12 of the laminated body 2. A part will be pushed out from the outline of the region where the substrate 100 and the substrate 120 overlap.
Similarly, the laminate 2 is sandwiched between the hot plate 52 and the plate material 55, whereby the resin layer 13 disposed between the substrate 120 of the semiconductor element 12 and the substrate 140 of the semiconductor element 14 of the laminate 2. Is pushed out from between the substrates 120 and 140.
Further, similarly, the laminate 2 is sandwiched between the hot plate 52 and the plate material 55, whereby the resin located between the substrate 140 of the semiconductor element 14 and the substrate 160 of the semiconductor element 16 of the laminate 2. A part of the layer 15 is pushed out from the outline of the region where the substrates 140 and 160 overlap.
Each extruded resin layer 11, 13, 15 is located in a space sandwiched between the outer peripheral portion of the substrate 100 and the outer peripheral portion of the substrate 160 as shown in FIG.

  Here, the pressure applied when the laminate 2 is pressurized with a fluid is preferably 0.1 MPa or more and 10 MPa or less, more preferably 0.5 or more and 5 MPa or less. By pressurizing the laminate 2 with a fluid, the generation of voids in the resin layers 11, 13 and 15 can be suppressed. In particular, when the pressure is 0.1 MPa or more, this effect becomes remarkable. Moreover, the enlargement and complication of an apparatus can be suppressed by setting it as 10 Mpa or less. In addition, pressurizing with a fluid refers to making the pressure of the atmosphere of the laminated body 2 higher than the atmospheric pressure by the applied pressure. That is, the applied pressure of 10 MPa indicates that the pressure applied to the laminate 2 is 10 MPa greater than the atmospheric pressure.

Here, the laminate 2 is heated at a temperature equal to or higher than the melting point of the solder layers 121A, 141A, and 161A, for example, 240 ° C. to 260 ° C. for about 10 minutes. As a result, the solder layers 121A, 141A, and 161A can be melted to perform solder bonding. When the melting points of the solder layers 121A, 141A, and 161A are different, the laminate 2 may be heated to a temperature higher than the melting point of the solder layer having the highest melting point.
Thereafter, the hot plate 52 and the plate material 55 are separated from each other, and the fluid is further discharged from the container 51. The pressurization to the laminated body 2 by the fluid is stopped, and then the laminated body 2 is taken out from the container 51.

Here, in the first bonding step, when the resin layers 11, 13, and 15 are not completely cured, the curing of the resin layers 11, 13, and 15 is advanced using the apparatus 6 shown in FIG. May be. This device 6 has the same container 51 as the device 5 and heats the laminate 2 while pressurizing it with a fluid to cure the resin layers 11, 13 and 15. The same fluid as that used in the apparatus 6 can be used.
As a method of heating the laminated body 2, there is a method in which a heated fluid is put into the container 51 from the pipe 511 and the laminated body 2 is heated and pressurized. Moreover, the laminated body 2 can also be heated by flowing the fluid from the pipe 511 into the container 51 and heating the container 51 in a pressurized atmosphere.
The laminated body 2 is disposed in the container 51, a fluid is introduced, and the laminated body 2 is heated to a temperature higher than the curing temperature of the thermosetting resin of the resin layers 11, 13, 15 to cure the resin layers 11, 13, 15. To do. For example, heating is performed at 150 to 180 ° C. for 60 to 300 minutes. Here, the curing temperature is the curing temperature of the resin layer, and refers to the temperature at which the thermosetting resin contained in the resin layer becomes a C-stage according to JISK6900.
Note that the resin layers 11, 13, and 15 may be cured by putting a plurality of laminates 2 in the container 51 of the apparatus 6. In this way, productivity can be improved.
As described above, the stacked body 2 is obtained in which the semiconductor elements 10 and 12, the semiconductor elements 12 and 14, and the semiconductor elements 14 and 16 are solder-bonded (FIG. 5B).

(Second joining process)
Next, as shown in FIG. 7A, the up-down direction of the stacked body 2 is reversed, and as shown in FIG. The laminate 2 in which 14, 16 are soldered together is placed on the base material 18 and the laminate 2 and the base material 18 are soldered together.
First, the base material 18 is prepared. Here, the base material 18 may be a resin substrate, a silicon substrate, a ceramic substrate, or the like.

Terminals (laminated body connection terminals) 181 are formed on the surface of the substrate 18. The terminal 181 is made of the same structure and material as the terminal 101, and has a solder layer 181A on the surface. The terminal 181 is connected to the semiconductor element 16.
Next, the resin layer 17 is provided on the surface of the substrate 18. The resin layer 17 is provided so as to cover the terminal 181. The resin layer 17 may be the same as the resin layers 11, 13, and 15. For example, a paste-like no-flow type underfill material (NUF) may be used. In order to provide the resin layer 17 on a part of the surface of the substrate 18, it is preferable to apply a paste-like underfill material by dispensing or ink jet.

Examples of such a no-flow type underfill material include those disclosed in Japanese Patent Application Laid-Open No. 2008-13710, and the first epoxy resin that is liquid at room temperature and the curing temperature higher than that of the first epoxy resin. The resin composition includes a two-epoxy resin, a silicone-modified epoxy resin, an inorganic filler, and a curing agent having flux activity. This resin composition does not contain a solvent.
As the first epoxy resin, for example, bisphenol type epoxy resins such as bisphenol A type epoxy resin and bisphenol F type epoxy resin are preferable.
As the second epoxy resin, an epoxy resin having an allyl group (for example, diallyl bisphenol A type epoxy resin) is preferable.
The first epoxy resin is preferably 5 to 50% by weight in the resin composition, and the second epoxy resin is preferably 0.1 to 40% by weight.
Examples of the silicone-modified epoxy resin include silicone-modified (liquid) epoxy resins having a disiloxane structure, and specifically include silicone-modified epoxy resins represented by the following general formula (1).

The silicone modification rate of the silicone-modified epoxy resin is not particularly limited, but m of the silicone-modified resin is preferably 5 or less, and particularly preferably m is 1 or less.

  More specifically, the silicone-modified epoxy resin includes a silicone-modified liquid epoxy resin in which m of the silicone-modified liquid epoxy resin represented by the general formula (1) is 0, and a phenol represented by the following general formula (2). It is preferable that these are synthesized by heating reaction. Thereby, the wettability to a base material or a semiconductor element can be improved.

The molar ratio of the silicone-modified liquid epoxy resin represented by the general formula (1) in which m is 0 and the phenols represented by the general formula (2) (epoxy of the silicone-modified epoxy resin) (Group molar ratio / hydroxyl molar ratio of phenols) is not particularly limited, but is preferably 1 to 10, and particularly preferably 1 to 5. When the molar ratio is within the above range, the yield of the reaction product and low volatility are particularly excellent.
The content of the silicone-modified epoxy resin is preferably 0.1 to 20% by weight of the entire resin composition.

Furthermore, it is preferable to use two or more curing agents having flux activity having different melting points.
For example, as the first flux active curing agent, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, 2,5-dihydroxybenzoic acid, 2,6-dihydroxybenzoic acid, 3,4-dihydroxybenzoic acid are used. Acid is preferred.
As the second flux active curing agent, o-phthalic acid, trimellitic acid, hexahydrophthalic acid, methylhexahydrophthalic acid, 4-hydroxy (o-phthalic acid), 3-hydroxy (o-phthalic acid) ), Tetrahydrophthalic acid, maleic acid, those containing alkylene groups include succinic acid, malonic acid, glutaric acid, malic acid, sebacic acid, adipic acid, azelaic acid, suberic acid, pimelic acid, 1,9-nonanedicarboxylic acid And dodecanedioic acid. These may be used alone or in combination. Among these, sebacic acid is preferable.

After providing the resin layer 17 on the substrate 18, the laminate 2 is mounted on the resin layer 17. The laminate 2 is placed on the resin layer 17 so that the terminals 162 of the laminate 2 are located on the resin layer 17 side.
Thereafter, the laminate 2, the resin layer 17, and the substrate 18 are clamped in the laminating direction by the pair of clamping members 41 and 42, and the laminate 2, the resin layer 17, and the substrate 18 are brought to the melting point of the solder layer 181A or more. Heat to. At this time, the laminated body 2, the resin layer 17, and the base material 18 are clamped by the pair of clamping members 41 and 42, and the pair of clamping members 41 and 42 are heated, whereby the laminate 2 and the resin layer 17 are heated. The base material 18 is heated to the melting point or higher of the solder layer 181A. Thereby, the terminal 181 and the terminal 162 are soldered together. In this joining step, for example, a flip chip bonder is used, and the laminate 2 is soldered to the base material 18 one by one.
In this way, the plurality of stacked bodies 2 are installed on the base material 18, and the base material 18 and the plurality of stacked bodies 2 are soldered to obtain the structure 3 (see FIG. 7C).

Thereafter, the resin layer 17 of the structure 3 is cured as necessary. Here, the resin layer 17 is cured using the apparatus 6 shown in FIG. The curing method is the same as the method described above, and the structure 3 is heated to a temperature equal to or higher than the curing temperature of the thermosetting resin of the resin layer 17 while pressing the structure 3 with a fluid to cure the resin layer 17. Do.
By doing in this way, generation | occurrence | production of the void in the resin layer 17 can be prevented, and the generated void can be eliminated.

(Sealing process)
Next, the structure 3 is sealed. The sealing method may be potting, transfer molding, or compression molding.
Thereafter, for each stacked body 2, a plurality of semiconductor devices 1 shown in FIG. 1 can be obtained. In FIG. 1, reference numeral 19 denotes a sealing material, and reference numeral 18 </ b> A denotes a diced base material 18. Further, when the semiconductor device 1 has a plurality of stacked bodies 2, the semiconductor device 1 may be cut for each unit of the semiconductor device 1. In addition, a dicing blade, a laser, a router, etc. can be used for a cutting | disconnection.

According to the present embodiment as described above, the following effects can be obtained.
In the present embodiment, the semiconductor element 16 side surface of the semiconductor element 16 on the semiconductor element 14 side of the semiconductor element 16 and the semiconductor element 16 of the substrate 140 of the semiconductor element 14 are located inside the outline of the substrate 160 of the semiconductor element 16 in plan view from the stacking direction. A laminate 2 is prepared in which the outline of the region where the side surface overlaps is located. And this laminated body 2 is pressurized along the lamination direction.
Even if a part of the resin layer 15 is pushed out from the region where the substrate 160 of the semiconductor element 16 and the substrate 140 of the semiconductor element 14 are overlapped in this pressurizing step, the outline of the substrate 160 of the semiconductor element 16 is increased. However, the resin layer 15 is provided on the side surface of the substrate 160 of the semiconductor element 16 and further, the terminal 162 of the substrate 160 of the semiconductor element 16 is provided. It can suppress reaching to the substrate surface.
As a result, it is possible to prevent the hot plate 52 that is a clamping member that clamps the stacked body 2 from being contaminated by the resin layer 15, and to increase the productivity of the semiconductor device 1.
Moreover, in this embodiment, since it can prevent that the resin layer 15 adheres to the board | substrate surface in which the terminal 162 of the board | substrate 160 was provided, electrical connection with the terminal 162 and the terminal 181 of 18 A of base materials is taken reliably. Thus, the semiconductor device 1 having excellent connection reliability can be obtained.

In the present embodiment, the surface of the semiconductor element 10 on the semiconductor element 12 side of the substrate 100 of the semiconductor element 10 and the surface of the substrate 120 of the semiconductor element 12 on the semiconductor element 10 side overlap inside the outline of the substrate 100 of the semiconductor element 10. The laminated body 2 in which the outline of the region is located is prepared. And this laminated body 2 is pressurized along the lamination direction.
Also by this, the same effect as described above can be obtained, and it is possible to prevent the plate material 55 which is a clamping member for clamping the laminated body 2 from being contaminated by the resin layer 11 and to increase the productivity of the semiconductor device. be able to.

  Furthermore, in the present embodiment, the outer surface of the substrate 120 of the semiconductor element 12 and the outer surface of the semiconductor element 14 are located inside the outer surface of the substrate 100 of the semiconductor element 10 and the outer surface of the substrate 160 of the semiconductor element 16 in plan view from the stacking direction of the stacked body 2. The outline of the substrate 140 is located. Therefore, even when the resin layer 13 positioned between the substrates 120 and 140 is extruded from between the substrates 120 and 140 during the manufacture of the laminated body 2, the extruded resin layer 13 is removed from the outer periphery of the substrate 100 of the semiconductor element 10. And the outer periphery of the substrate 160 of the semiconductor element 16 can be accommodated.

  Furthermore, in this embodiment, the substrate 100 of the semiconductor element 10, the substrate 120 of the semiconductor element 12, the substrate 140 of the semiconductor element 14, and the substrate 160 of the semiconductor element 16 are all in a direction orthogonal to the substrate surface (of the stacked body 2 The cross-sectional shape in the direction along the stacking direction is a rectangular shape. By using a semiconductor element having a substrate whose shape is not complicated as described above, the substrate can be prevented from being broken, and the productivity of the semiconductor device can be increased.

Furthermore, in the present embodiment, the semiconductor elements 12 and 14 and the semiconductor element 16 have different sizes in plan view from the stacking direction of the stacked body 2, but in the present embodiment, dicing lines having the same pattern are used. These semiconductor elements 12, 14, and 16 are obtained by devising a dicing method for the wafers W1 to W3 on which D is formed. Specifically, the wafers W1 and W2 are diced with a blade B1 having a wide cutting edge to obtain semiconductor elements 12 and 14, and the wafer W3 is diced with a blade B2 having a narrow cutting edge to obtain a semiconductor element 16. Thus, by changing the blade used for dicing, semiconductor elements 12, 14, and 16 of different sizes can be easily obtained.
In particular, when the semiconductor elements 12, 14, and 16 all have the same function and the arrangement of the internal circuits is the same, the blades for cutting the same type of wafer obtained in the same production process are different. Since the semiconductor elements 12, 14, and 16 having different plane sizes can be obtained simply by using the semiconductor device 1, the semiconductor device 1 can be easily manufactured.

  In the present embodiment, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, the semiconductor element 14, the resin layer 15, and the semiconductor element 16 are stacked in this order to obtain the stacked body 2, and then the stacked body 2 The whole is heated and soldered. Therefore, thermal damage to each semiconductor element 10, 12, 14, 16 can be reduced. Therefore, the reliability of the semiconductor device 1 can be improved.

  In the present embodiment, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, the semiconductor element 14, the resin layer 15, and the semiconductor element 16 are stacked in this order to obtain the stacked body 2, and then the stacked body 2 The solder is joined by sandwiching the pin. During solder joining, the pinching is prevented a plurality of times, and damage to the semiconductor elements 10, 12, 14, and 16 is reduced.

In the present embodiment, after the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 of the multilayer body 2 are soldered together, the base material 18 and the multilayer body 2 are soldered.
After the laminated body 2 in a state where the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are not solder-bonded is placed on the base material 18, the laminated body 2 and the base material 18 are heated, A method of soldering the terminals 101 and 121, the terminals 122 and 141, the terminals 142 and 161, and the terminals 181 and 162 of the substrate 18 is also conceivable.
However, in such a method, when the difference in linear expansion coefficient between the base material 18 and the laminate 2 is large, the stress generated by the difference in linear expansion coefficient is applied to the laminate 2, and there is a shift in the laminate 2. May occur.
On the other hand, as in this embodiment, after the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are soldered together, the laminate 2 and the substrate 18 are soldered together. Thus, it is possible to prevent the occurrence of deviation in the laminate 2.

  Further, in the present embodiment, when the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 of the multilayer body 2 are soldered together, the multilayer body 2 is pressurized and heated with a fluid. By pressurizing the laminate 2 with a fluid, it is possible to prevent voids from being generated in the resin layers 11, 13, and 15 of the laminate 2. Further, when the laminate 2 is pressurized with a fluid, the voids in the resin layers 11, 13 and 15 of the laminate 2 are pressurized and become smaller. From the above, it is possible to prevent the terminals from being displaced due to voids.

In the present embodiment, in the step of preparing the laminate 2, the semiconductor elements 10 and 12 are bonded via the semi-cured resin layer 11. Similarly, the semiconductor elements 12 and 14 are bonded via the semi-cured resin layer 13, and the semiconductor elements 14 and 16 are bonded via the semi-cured resin layer 15. As described above, since the semiconductor elements are bonded to each other, it is possible to prevent the semiconductor elements from being displaced in the stacked body 2.
When the semiconductor elements 12 and 14 are bonded via the semi-cured resin layer 13 and when the semiconductor elements 14 and 16 are bonded via the semi-cured resin layer 15, the semiconductor element 10 , 12 and 14 are heated several times. However, since the heating is performed for bonding the semiconductor elements to each other by a semi-cured resin layer, the heating temperature can be set relatively low, and even if the heating temperature is increased. However, the heating time is relatively short. Therefore, the influence of heat on the semiconductor elements 10, 12, and 14 is considered to be very small.

  Furthermore, in the present embodiment, the resin layer 11 is provided on the semiconductor element 12 in the previous stage constituting the stacked body 2. Similarly, a resin layer 13 is provided on the semiconductor element 14, and a resin layer 15 is provided on the semiconductor element 16. Since the semiconductor elements 12, 14, and 16 all have a TSV structure and are very thin, by providing the resin layers 11, 13, and 15 respectively, warpage of the semiconductor elements 12, 14, and 16 can be prevented and handled. It can be made excellent in properties.

  In the present embodiment, the plurality of laminates 2 are solder-bonded to the base material 18, sealed, and then cut. Thereby, the productivity of the semiconductor device 1 can be improved.

(Second embodiment)
A second embodiment of the present invention will be described with reference to FIGS.
In the stacked body 2A of the semiconductor device of this embodiment, a semiconductor element 16A different from the semiconductor element 16 of the above embodiment is used. Other points are the same as those of the semiconductor device 1 of the embodiment.
As shown in FIG. 8A, in the present embodiment, a semiconductor element 16A is used.
The semiconductor element 16A has a T-shaped cross section along the stacking direction of the stacked body 2A, and includes a substrate 160A, terminals 161 and 162, and vias 163 similar to those in the above embodiment.
The substrate 160A is a semiconductor substrate, for example, a silicon substrate, and a main body portion 160B connected to the semiconductor element 14 and a flange portion 160C protruding outward from an end portion of the main body portion 160B opposite to the semiconductor element 14. With.

The main body 160B has a planar rectangular shape. The collar portion 160C is provided so as to surround the outer peripheral edge of the end surface where the terminal 162 of the main body portion 160B is provided, and extends outward from the outer peripheral edge of the main body portion 160B. In the present embodiment, the collar portion 160C is provided so as to surround the entire outer peripheral edge of the end portion of the main body portion 160B. The protruding dimension of the collar part 160C from the main body part 160B is, for example, 2.5 μm to 2.5 mm.
And it is preferable that ratio (B '/ B) of thickness B' of collar part 160C and thickness B of substrate 160A is 0.1-0.9. By setting (B ′ / B) to be 0.1 or more, cracking of the flange portion 160C can be suppressed, and by setting (B ′ / B) to be 0.9 or less, the semiconductor element 16 and The resin layer 15 protruding from the region where the semiconductor element 14 overlaps can be accommodated immediately below the collar portion 160C. Among these, (B ′ / B) is particularly preferably 0.3 to 0.7.

In a plan view from the stacking direction of the stacked body 2A, the outer shell of the collar portion 160C is located outside the outer shell of the main body 160B.
The terminal 161 is formed on the end surface (substrate surface) of the main body portion 160B on the semiconductor element 14 side, and the terminal 162 is formed on the end surface (substrate surface) of the main body portion 160B opposite to the semiconductor element 14. . The via 163 penetrates the main body 160B and is connected to the terminals 161 and 162.
And in laminated body 2A, in the planar view from the lamination direction,
An outline of a region in which the surface of the semiconductor element 16A on the substrate 160A side of the semiconductor element 14 and the surface of the semiconductor element 14 on the substrate 140 side of the semiconductor element 16A overlap;
An outline of a region where a surface of the substrate 140 of the semiconductor element 14 on the side of the semiconductor element 12 and a surface of the substrate 120 of the semiconductor element 12 on the side of the semiconductor element 14 overlap,
An outline of a region where the surface of the semiconductor element 12 on the substrate 120 side of the substrate 120 and the surface of the semiconductor element 10 on the substrate 100 side of the semiconductor element 10 overlap,
Are all located inside the outline without contacting the outline of the substrate 100 and the flange 160C of the semiconductor element 16A.
Note that the surface of the substrate 160A of the semiconductor element 16A on the semiconductor element 14 side is a surface on which the terminal 161 connected to the semiconductor element 14 is provided. Specifically, the terminal 161 of the main body 160B of the semiconductor element 16A is provided. Means a surface provided with This surface is the surface closest to the semiconductor element 14 of the substrate 160A and is a bonding surface.
In addition, the outline of the main body 160B coincides with the outline of the semiconductor elements 14 and 12 in plan view from the stacking direction of the stacked body 2A. That is, the side surface of the main body 160B and the side surfaces of the semiconductor elements 14 and 12 are flush with each other.
Furthermore, in a plan view from the stacking direction of the stacked body 2A, the outline of the flange portion 160C coincides with the outline of the semiconductor substrate 100 of the semiconductor element 10, and the side surface of the flange portion 160C, the side surface and the surface of the semiconductor substrate 100 It is one.

Here, the semiconductor element 16A can be manufactured as follows.
As in the above embodiment, as shown in FIG. 9A, a wafer W3 is prepared, and a resin layer 15A is provided on the wafer W3.
Thereafter, the wafer W3 and the resin layer 15A are cut along the dicing line from the resin layer 15A side.
First, a blade with a wide blade edge is prepared, and a groove T2 that penetrates through the resin layer 15A and reaches a middle position of the thickness of the wafer W3 is formed. The groove T2 is formed along the dicing line.
Thereafter, a blade having a narrower blade edge than the blade is inserted into the groove T2, and the wafer W3 is cut (the groove T1 is formed).
Thereby, the semiconductor element 16A can be obtained. In the semiconductor element 16A, the resin layer 15 is provided on the main body portion 160B and is not provided on the flange portion 160C.

As shown in FIG. 8A, the semiconductor element 10, the resin layer 11, the semiconductor element 12, the resin layer 13, and the semiconductor element 14 are stacked, and then the resin layer 15 is formed on the semiconductor element 14 as in the above embodiment. The attached semiconductor element 16A is stacked.
At the time of stacking as described above, in the plan view from the stacking direction of the stacked body, the outer layers of the resin layers 15, 11, and 13 Located inside the outer shell.
Subsequent processes are the same as those in the above embodiment, but when the stacked body 2A is sandwiched between the hot plates 52 and 53 of the apparatus 5 shown in FIG. 5, the substrate 100 and the semiconductor element 12 of the semiconductor element 10 of the stacked body 2A. The resin layer 11 disposed between the substrate 120 and the substrate 120 protrudes from between the substrates 100 and 120.
Similarly, the resin layer 13 disposed between the substrate 120 of the semiconductor element 12 and the substrate 140 of the semiconductor element 14 of the stacked body 2 </ b> A protrudes from between the substrates 120 and 140.
Further, similarly, the laminated body 2A is sandwiched between the hot plates 52 and 53, so that the resin layer located between the substrate 140 of the semiconductor element 14 of the laminated body 2A and the main body 160B of the semiconductor element 16A. 15 protrudes between the board | substrate 140 and the main-body part 160B.
As shown in FIG. 8B, each protruding resin layer is located in a space between the outer peripheral portion of the substrate 100 and the flange portion 160C of the substrate 160A.
Subsequent steps are the same as those in the above-described embodiment, in which the stacked body 2A is stacked on the base material 18, the base material 18 is diced, and the stacked body 2A is sealed with a sealing material. Can be obtained.

According to this embodiment as described above, the same effects as those of the above-described embodiment can be obtained, and the following effects can be obtained.
In the present embodiment, the substrate 160A includes a main body portion 160B and a flange portion 160C. The flange portion 160C is provided on the opposite side of the main body portion 160B from the semiconductor element 14. Thereby, a large distance can be ensured between the flange portion 160C and the outer peripheral portion of the semiconductor element 10 facing the flange portion 160C. Therefore, the resin layers 11, 13, and 15 that protrude when the stacked body 2A is sandwiched are reliably accommodated in the space between the flange portion 160C and the outer peripheral portion of the semiconductor element 10 facing the flange portion 160C. be able to.

  In addition, the resin layer 15 is provided on the main body 160B before the semiconductor element 16A is stacked on the semiconductor element 14, but the resin layer 15 is not provided on the flange 160C. Since the resin layer 15 is not provided in the collar portion 160C, when the laminated body 2A is sandwiched, the resin layer 15 protrudes to the side surface of the collar portion 160C and the side where the terminal 162 is provided. It can be surely suppressed.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.
In the present embodiment, semiconductor elements 14A and 12A having the same shape as the semiconductor element 16A are used.
Similar to the semiconductor element 16A, the semiconductor element 14A has a substantially T-shaped cross section in the stacking direction of the stacked body 2B, and includes a substrate 140A, terminals 141 and 142, and vias 143 similar to those in the above embodiment.
The substrate 140A is a semiconductor substrate, for example, a silicon substrate, a main body portion 140B connected to the semiconductor element 12A, and a collar portion 140C projecting outward from an end portion of the main body portion 140B opposite to the semiconductor element 12A. With. 140 C of collar parts are provided so that the outer periphery of the end surface in which the terminal 142 of the main-body part 140B was provided may be enclosed.
The main body 140B has the same shape as the main body 160B, and the collar 140C has the same shape as the collar 160C.
The terminal 141 is formed on the end surface (substrate surface) of the main body 140B on the semiconductor element 12 side, and the terminal 142 is formed on the end surface (substrate surface) on the opposite side of the main body 140B from the semiconductor element 12. . The via 143 passes through the main body 140B and is connected to the terminals 141 and 142.
The protruding dimension of the collar part 140C from the main body part 140B, the thickness of the collar part 140C, and the ratio of the thickness of the collar part 140C and the thickness of the substrate 140 are the same as those of the semiconductor element 16A.

The semiconductor element 12A is a semiconductor substrate, for example, a silicon substrate. Like the semiconductor element 16A, the cross section along the stacking direction of the stacked body 2B is substantially T-shaped, and the substrate 120A and the same terminal as in the above embodiment are used. 121 and 122 and vias 123.
The substrate 120A includes a main body portion 120B connected to the semiconductor element 10 and a flange portion 120C projecting outward from an end portion of the main body portion 120B located on the side opposite to the semiconductor element 10.
The main body 120B has the same shape as the main body 160B, and the flange 120C has the same shape as the flange 160C. 120 C of collar parts are provided so that the outer periphery of the end surface in which the terminal 122 of the main-body part 120B was provided may be enclosed.
The terminal 121 is formed on the end surface (substrate surface) on the semiconductor element 10 side of the main body 120B, and the terminal 122 is formed on the end surface (substrate surface) on the opposite side of the main body 120B from the semiconductor element 10. . The via 123 penetrates through the main body 120 </ b> B and is connected to the terminals 121 and 122.
The protruding dimension of the flange 120C from the main body 120B, the thickness of the flange 120C, and the ratio of the thickness of the flange 120C and the thickness of the substrate 120 are the same as those of the semiconductor element 16A.

In the laminate 2B,
A surface of the substrate 160A of the semiconductor element 16A on the semiconductor element 14A side (an end surface on which the terminal 161 of the main body 160B is provided) and a surface of the substrate 140A of the semiconductor element 14A on the semiconductor element 16A side (a surface on which the terminal 142 is provided). The outline of the overlapping area,
A surface of the substrate 140A of the semiconductor element 14A on the semiconductor element 12A side (an end surface on which the terminal 141 of the main body 140B is provided) and a surface of the substrate 120A of the semiconductor element 12A on the semiconductor element 14A side (a surface on which the terminal 122 is provided). The outline of the overlapping area,
An outline of a region where the surface of the semiconductor element 12A on the side of the semiconductor element 10 of the substrate 120A (the end surface on which the terminal 121 of the main body 120B is provided) and the surface of the substrate 100 of the semiconductor element 10 on the side of the semiconductor element 12A overlap;
Are all located inside the outline without contacting the outline of the substrate 100 and the flange 160C of the semiconductor element 16A.
In the present embodiment, the outlines of the flange portions 160C, 140C, and 120C coincide with each other in plan view from the stacking direction of the stacked body 2B.

  Each of the semiconductor elements 14A and 12A can be manufactured by a method similar to the manufacturing method of the semiconductor element 16A of the second embodiment.

As shown in FIG. 10A, similarly to the above embodiment, the semiconductor element 10, the semiconductor element 12A with the resin layer 11, and the semiconductor element 14A with the resin layer 13 are stacked, and then the resin is formed on the semiconductor element 14A. The semiconductor element 16A with the layer 15 is stacked.
Here, the resin layer 11 is provided only on the surface of the main body 120B of the semiconductor element 12A located on the semiconductor element 10 side, and is not provided on the flange 120C.
Further, the resin layer 13 is provided only on the surface of the main body 140B of the semiconductor element 14A located on the semiconductor element 12A side, and is not provided on the flange 140C.
Similarly, the resin layer 15 is provided only on the surface of the main body 160B of the semiconductor element 16A located on the semiconductor element 14A side, and is not provided on the flange 160C.
Subsequent processes are the same as those in the above embodiments, but when the stacked body 2A is clamped by the hot plates 52 and 53 of the apparatus 5 shown in FIG. 5, the substrate 100 and the semiconductor element of the semiconductor element 10 of the stacked body 2B The resin layer 11 disposed between the 12A substrate 120A and the main body 120B protrudes from between the substrate 100 and the main body 120B. As shown in FIG. 10B, the protruding resin layer 11 is accommodated in a space between the outer peripheral portion of the substrate 100 and the flange portion 120C of the semiconductor element 12A.
Similarly, the resin layer 13 disposed between the main body portion 120B of the substrate 120A of the semiconductor element 12A and the main body portion 140B of the substrate 140A of the semiconductor element 14A protrudes from between the main body portions 120B and 140B. As shown in FIG. 10B, the protruding resin layer 13 is accommodated in a space between the flange portion 120C of the semiconductor element 12A and the flange portion 140C of the semiconductor element 14A.
Further, similarly, the laminate 2B is sandwiched between the hot plates 52 and 53, so that the main body 140B of the substrate 140A of the semiconductor element 14A of the laminate 2B and the main body 160B of the substrate 160A of the semiconductor element 16A are interposed. The resin layer 15 located in the position protrudes from between the main body portions 140B and 160B. As shown in FIG. 10B, the protruding resin layer 15 is accommodated in a space between the flange portion 140C of the semiconductor element 14A and the flange portion 160C of the semiconductor element 16A.
Subsequent steps are the same as those in each of the above embodiments. The laminate 2B is laminated on the substrate 18, the substrate 18 is diced, and further, the laminate 2B is sealed with a sealing material. A device can be obtained.

According to the present embodiment as described above, the same effects as those of the above-described embodiment can be obtained, and the following effects can be obtained.
In this embodiment, each of the semiconductor elements 12A and 14A has the flange portions 120C and 140C, respectively. Thereby, for example, the resin layer 13 between the semiconductor element 14A and the semiconductor element 12A can be prevented from protruding to the semiconductor element 10 or the semiconductor element 16A side.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIGS.
In the present embodiment, the shapes of the semiconductor element 14B and the semiconductor element 12B are different from the semiconductor device 1 of the first embodiment. Other points are the same as in the first embodiment.
As shown in FIG. 11, the semiconductor element 14 </ b> B has a substantially T-shaped cross section along the stacking direction of the stacked body 2 </ b> C, and includes a substrate 140 </ b> D, terminals 141 and 142, and vias 143 similar to those in the above embodiment.
The substrate 140D is a semiconductor substrate, for example, a silicon substrate, and includes a main body portion 140E and a flange portion 140F.
The main body 140E is a portion connected to the semiconductor element 12B and the semiconductor element 16, and a terminal 141 is provided on the end surface of the main body 140E on the semiconductor element 12B side, and a terminal 142 is provided on the other end surface. Yes. The via 143 passes through the main body 140E and connects the terminals 141 and 142.
The flange portion 140F is provided so as to protrude from the outer peripheral portion of the main body portion 140E on the semiconductor element 12B side, and surrounds the entire outer periphery of the main body portion 140E on the semiconductor element 12B side portion. In other words, the collar portion 140F is provided so as to surround the outer periphery of the end surface on which the terminal 141 of the main body portion 140E is provided.
The protruding dimension of the collar part 140F from the main body part 140E, the thickness of the collar part 140F, and the ratio of the thickness of the collar part 140F and the thickness of the substrate 140D are the same as those of the semiconductor element 16A.

As shown in FIG. 11, the semiconductor element 12 </ b> B has a substantially T-shaped cross section along the stacking direction of the stacked body 2 </ b> C, and includes a substrate 120 </ b> D, terminals 121 and 122, and vias 123 similar to those in the above embodiment.
The substrate 120D is a semiconductor substrate, for example, a silicon substrate, and includes a main body portion 120E and a flange portion 120F.
The main body 120E is a portion connected to the semiconductor element 14B and the semiconductor element 10, and a terminal 121 is provided on one end surface of the main body 120E, and a terminal 122 is provided on the other end surface. The via 123 passes through the main body 120E and connects the terminals 121 and 122.
The flange portion 120F is provided so as to protrude from the outer peripheral portion of the portion of the main body portion 120E on the semiconductor element 10 side, and surrounds the entire outer periphery of the portion of the main body portion 120E on the semiconductor element 10 side. In other words, the flange portion 120F is provided so as to surround the outer periphery of the end surface on which the terminal 121 of the main body portion 120E is provided.
Note that the protruding dimension of the flange part 120F from the main body part 120E, the thickness of the flange part 120F, the ratio of the thickness of the flange part 140F and the thickness of the substrate 120D are the same as those of the semiconductor element 16A.

Here, in a plan view from the stacking direction of the stacked body 2C,
An outline of a region where the surface of the substrate 160 of the semiconductor element 16 on the side of the semiconductor element 14B and the surface of the substrate 140D of the semiconductor element 14B on the side of the semiconductor element 16 (the end surface on which the terminal 142 of the main body 140E is provided) overlap;
The surface of the semiconductor element 14B on the side of the semiconductor element 12B of the substrate 140D (the surface on which the terminal 141 is provided) and the surface of the substrate 120D of the semiconductor element 12B on the side of the semiconductor element 14B (the end surface on which the terminal 122 of the main body 120E is provided). The outline of the overlapping area,
An outline of a region where a surface of the substrate 120D of the semiconductor element 12B on the semiconductor element 10 side (surface on which the terminals 121 are provided) and a surface of the substrate 100 of the semiconductor element 10 on the side of the semiconductor element 12B overlap;
Are located inside these outlines without contacting the outline of the substrate 100 and the outline of the substrate 160 of the semiconductor element 16.
However, the outline of the substrate 160 of the semiconductor element 16 matches the outline of the flange 140F of the semiconductor element 14B, the outline of the flange 120F of the semiconductor element 12B, and the outline of the substrate 100. The side surface of the substrate 160 of the semiconductor element 16, the side surfaces of the main body portions 140E and 120E of the semiconductor elements 14B and 12B, and the side surface of the substrate 100 are flush with each other.

Here, the semiconductor elements 12B and 14B can be manufactured as follows.
As in the first embodiment, as shown in FIG. 12, a wafer W1 is prepared, and a resin layer 11A is provided on the wafer W1. At this time, the resin layer 11A is provided on the surface of the wafer W1 where the terminals 121 are formed.
Thereafter, the wafer W1 and the resin layer 11A are cut along the dicing line from the surface on which the resin layer 11A is not provided.
First, a blade having a wide blade edge is prepared, and the groove T3 reaching the middle position of the thickness of the wafer W1 is formed. The groove T3 is formed along the dicing line.
Thereafter, a blade having a narrower blade edge than the blade is inserted into the groove T3 to cut the wafer W1 and the resin layer 11A (form a groove T4).
Thereby, the semiconductor element 12B can be obtained. In the semiconductor element 12B, the resin layer 11 is provided over the main body portion 120E and the flange portion 120F.
The semiconductor element 14B is manufactured by the same method. A semiconductor element 14B can be obtained by preparing a wafer W2 to be the semiconductor element 14B, providing a resin layer 13A on the wafer W2, and performing dicing in the same manner.

Thereafter, as shown in FIG. 11B, similarly to the above-described embodiment, the semiconductor element 10, the semiconductor element 12B with the resin layer 11, and the semiconductor element 14B with the resin layer 13 are stacked, and then, on the semiconductor element 14B. A semiconductor element 16 with a resin layer 15 is stacked.
Subsequent processes are the same as those of the above embodiments, but when the stacked body 2C is clamped by the hot plates 52 and 53 of the apparatus 5 shown in FIG. 5, the substrate 100 and the semiconductor element of the semiconductor element 10 of the stacked body 2C The resin layer 11 disposed between the 12B substrate 120D protrudes from between the substrates 100 and 120D.
Further, by sandwiching the stacked body 2C, a portion of the resin layer 13 that is located between the main body portion 120E of the substrate 120D of the semiconductor element 12B of the stacked body 2C and the main body portion 140E of the semiconductor element 14B, It protrudes from between the main body parts 120E and 140E. The protruding resin layer 13 is accommodated between the flange portion 120F and the flange portion 140F.
Further, by sandwiching the stacked body 2C, a portion of the resin layer 15 that is located between the main body portion 140E of the semiconductor element 14B and the substrate 160 of the semiconductor element 16 in the stacked body 2C is separated from the main body portion 140E. It protrudes from the area between the substrate 160. The protruding resin layer 15 is accommodated between the flange portion 140F and the outer peripheral portion of the substrate 160 of the semiconductor element 16 facing the flange portion 140F.
Subsequent steps are the same as those in the above-described embodiment, in which the stacked body 2C is stacked on the base material 18, the base material 18 is diced, and the stacked body 2C is sealed with a sealing material. Can be obtained.

  According to the present embodiment as described above, the same effects as those of the respective embodiments can be obtained.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, in the above embodiment, a stacked body is formed by stacking four semiconductor elements, but the present invention is not limited to this. There may be a plurality of semiconductor elements.
Furthermore, in the said embodiment, although each semiconductor element 12, 14, 16, 16A, 14A, 12A, 14B, 12B was made into the TSV structure in the said embodiment, it is not restricted to this. For example, the semiconductor elements 16 and 16A may not be a semiconductor element having a TSV structure.

Furthermore, in each of the above embodiments, after the stacked body 2 is formed, the stacked body 2 is clamped to solder each semiconductor element at a time. However, the method for manufacturing a semiconductor device of the present invention is not limited to this. It is not something that can be done.
For example, after mounting the semiconductor element 12 on the semiconductor element 10, the semiconductor element 10 and the semiconductor element 12 may be sandwiched and soldered together in the stacking direction. Thereafter, the semiconductor element 12 and the semiconductor element 14 may be solder-bonded by a similar method.
In each of the above embodiments, the semiconductor element 10 may be a substrate such as a resin substrate instead of a semiconductor element.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Laminate 2A Laminate 2B Laminate 2C Laminate 3 Structure 5 Device 6 Device 10 Semiconductor element 11 Resin layer 11A Resin layer 11 Resin layer 12 Semiconductor element 12A Semiconductor element 12B Semiconductor element 13 Resin layer 13A Resin layer 14 Semiconductor element 14A Semiconductor element 14B Semiconductor element 15 Resin layer 15A Resin layer 16 Semiconductor element 16A Semiconductor element 17 Resin layer 18A Base material 18 Base material 19 Sealing material 41, 42 Clamping member 51 Container 52, 53 Hot plate 54 Pin 55 Plate material 100 Substrate 101 Terminal 120 Substrate 120A Substrate 120B Main Body 120C Gutter 120D Substrate 120F Gutter 120E Main Body
121 terminal 121A solder layer 122 terminal 123 via 140 substrate 140A substrate 140B main body 140C flange 140D substrate 140E main body 140F flange 141 terminal 141A solder layer 142 terminal 143 through via 160 substrate 160A substrate 160B body 160C flange 161 terminal 161A Solder layer 162 Terminal 163 Via 181 Terminal 181A Solder layer 511 Pipe T1 Groove T2 Groove T3 Groove T4 Groove W1 Wafer W2 Wafer W3 Wafer

Claims (20)

A first semiconductor element having a semiconductor substrate and a connection terminal provided on the semiconductor substrate;
A semiconductor substrate having connection terminals on the front and back surfaces and a second semiconductor element having a through via that connects between the connection terminals and penetrates the semiconductor substrate;
A laminate comprising a resin layer disposed between the semiconductor substrate of the first semiconductor element and the semiconductor substrate of the second semiconductor element;
In plan view from the stacking direction,
Inside the outer surface of the first semiconductor element, a surface of the first semiconductor element on the second semiconductor element side of the semiconductor substrate and a surface of the second semiconductor element on the first semiconductor element side of the semiconductor substrate. Preparing a laminate in which the outline of the overlapped region is located;
The stacked body is sandwiched from a stacking direction by a pair of pressing members, and the stacked body is pressed along the stacking direction to connect the connection terminal of the first semiconductor element and the first of the second semiconductor element. A method for manufacturing a semiconductor device, comprising: joining one of the connection terminals located on the semiconductor element side. In the manufacturing method of the semiconductor device according to claim 1,
In the step of pressing the laminate along the lamination direction,
While heating the laminated body above the melting point of the solder layer formed on the connecting terminal of the first semiconductor element or the one connecting terminal of the second semiconductor element, the laminated body is added along the laminating direction. Press
A method of manufacturing a semiconductor device, wherein the connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element are soldered together. In the manufacturing method of the semiconductor device according to claim 1 or 2,
In the step of preparing the laminate,
A third semiconductor element having a semiconductor substrate and a connection terminal provided on the semiconductor substrate, and another resin disposed between the semiconductor substrate of the second semiconductor element and the semiconductor substrate of the third semiconductor element Preparing the laminate comprising a layer,
The surface of the second semiconductor element on the side of the third semiconductor element of the semiconductor substrate and the surface of the semiconductor substrate of the third semiconductor element on the side of the second semiconductor element are overlapped inside the outline of the first semiconductor element. Prepare the laminate in which the outline of the area that was located is located,
In the step of pressing the laminate along the lamination direction,
The pressing member pressurizes the stacked body along the stacking direction to join the connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element, and to connect the second semiconductor A method of manufacturing a semiconductor device, wherein the other connection terminal of the element is joined to the connection terminal of the third semiconductor element. In the manufacturing method of the semiconductor device according to claim 1,
In the previous stage of the step of preparing the laminate,
Prepare two wafers with dicing lines of the same pattern,
The first semiconductor element is obtained by dicing the wafer on one side along the dicing line with a first blade,
The other wafer is diced along the dicing line with a second blade having a blade edge wider than the first blade, so that the planar shape is similar to that of the first semiconductor element, and the first blade Obtaining the second semiconductor element having a planar shape smaller than the planar shape of one semiconductor element;
In the step of preparing the laminate,
The first semiconductor element and the second semiconductor element are stacked so that an outer peripheral portion of the semiconductor substrate of the first semiconductor element is positioned outside an outer peripheral portion of the semiconductor substrate of the second semiconductor element. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
In the step of preparing the laminate,
Comprising a fourth semiconductor element or substrate;
The second semiconductor element is disposed between the fourth semiconductor element or the substrate and the first semiconductor element, and an outer peripheral portion of the fourth semiconductor element or the substrate is the semiconductor of the second semiconductor element. Prepare the laminate positioned outside the side of the substrate,
In the step of pressurizing the stacked body along the stacking direction, the semiconductor pressurizing the stacked body including the first semiconductor element, the second semiconductor element, and the fourth semiconductor element or the substrate along the stacking direction. Device manufacturing method. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 5,
In the step of preparing the laminate, the thermosetting resin layer is in a semi-cured state, and the resin layer disposed between the first semiconductor element and the second semiconductor element has a temperature of 60 ° C. to The minimum melt viscosity at 150 ° C. is 0.1 Pa · s or more and 10,000 Pa · s or less,
In the step of pressing the laminate along the lamination direction,
While heating the laminated body above the melting point of the solder layer formed on the connecting terminal of the first semiconductor element or the connecting terminal of the second semiconductor element, the laminated body is pressurized along the laminating direction, and the first A method of manufacturing a semiconductor device, wherein a connection terminal of one semiconductor element and a connection terminal of a second semiconductor element are joined by soldering. In the manufacturing method of the semiconductor device according to claim 1,
In the previous stage of the step of preparing the laminate,
Preparing a wafer, and cutting the wafer with a first blade having a blade edge of a predetermined width to a middle position of the thickness of the wafer to form a groove of a predetermined width,
By inserting a second blade having a blade width narrower than the first blade into the groove and cutting the wafer along the groove, a main body portion provided with the connection terminal on one end surface; Preparing a first semiconductor element comprising the semiconductor substrate having a flange projecting outward from the peripheral edge of the other end surface of the main body;
In the step of preparing the laminate,
The one end face side of the main body portion of the first semiconductor element is disposed on the second semiconductor element side,
In plan view from the stacking direction,
The one end surface of the main body portion of the first semiconductor element and the surface of the semiconductor substrate of the second semiconductor element on the side of the first semiconductor element are overlapped inside the outline of the flange portion of the first semiconductor element. A method for manufacturing a semiconductor device, comprising preparing a stacked body in which an outline of a certain region is located. In the manufacturing method of the semiconductor device according to claim 1,
In the previous stage of the step of preparing the laminate,
A wafer is prepared, and the wafer is cut with a first blade having a cutting edge of a predetermined width to a middle position of the thickness of the wafer to form a groove of a predetermined width, and the width of the cutting edge is larger than that of the first blade. By inserting a thin second blade into the groove and cutting the wafer along the groove, the one connection terminal is formed on one end surface, and the other connection terminal is formed on the other end surface. A step of preparing a second semiconductor element comprising the main body portion and the semiconductor substrate having a flange portion projecting outward from the peripheral edge of the other end surface of the main body portion;
Preparing the first semiconductor element having the semiconductor substrate having a larger planar shape than the main body of the second semiconductor element; and
In the step of preparing the laminate,
The one end surface of the main body portion of the second semiconductor element is disposed on the first semiconductor element side,
In a plan view from the direction along the stacking direction,
Inside the outer surface of the semiconductor substrate of the first semiconductor element, a surface of the semiconductor substrate of the first semiconductor element on the second semiconductor element side, and the first semiconductor element of the main body of the second semiconductor element A method of manufacturing a semiconductor device, comprising preparing a stacked body in which an outline of a region where the one end face located on the side overlaps is located. In the manufacturing method of the semiconductor device according to claim 1,
A dicing line is formed on the semiconductor substrate of the first semiconductor element,
A dicing line is formed on the semiconductor substrate of the second semiconductor element,
A method of manufacturing a semiconductor device, wherein a region surrounded by the dicing line of the first semiconductor element and a region surrounded by the dicing line of the second semiconductor element have the same size and shape. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 9,
The method of manufacturing a semiconductor device, wherein the first semiconductor element is a semiconductor element having the semiconductor substrate and a through via that penetrates the semiconductor substrate and is connected to the connection terminal. A first semiconductor element having a semiconductor substrate and connection terminals;
A semiconductor substrate having connection terminals formed on the front and back surfaces, and a through via that connects between the terminals and penetrates the semiconductor substrate, and one of the connection terminals is bonded to the connection terminal of the first semiconductor element A second semiconductor element,
A resin layer disposed between the semiconductor substrate of the first semiconductor element and the semiconductor substrate of the second semiconductor element;
In plan view from the stacking direction,
Inside the outer surface of the first semiconductor element, a surface of the first semiconductor element on the second semiconductor element side of the semiconductor substrate, and a surface of the second semiconductor element on the first semiconductor element side of the semiconductor substrate, Semiconductor device in which the outline of the region where the two overlap is located. The semiconductor device according to claim 11,
A third semiconductor element having a connection terminal connected to the other connection terminal of the second semiconductor element, and a semiconductor substrate provided with the connection terminal;
Another resin layer disposed between the semiconductor substrate of the third semiconductor element and the semiconductor substrate of the second semiconductor element;
In plan view from the stacking direction,
Inside the outer surface of the first semiconductor element, a surface on the third semiconductor element side of the semiconductor substrate of the second semiconductor element, and a surface on the second semiconductor element side of the semiconductor substrate of the third semiconductor element, Semiconductor device in which the outline of the region where the two overlap is located. The semiconductor device according to claim 11 or 12,
A dicing line is formed on the semiconductor substrate of the first semiconductor element,
A dicing line is formed on the semiconductor substrate of the second semiconductor element,
A semiconductor device in which a region surrounded by the dicing line of the first semiconductor element and a region surrounded by the dicing line of the second semiconductor element have the same size and shape. The semiconductor device according to claim 11,
A semiconductor device in which an outer peripheral part of the semiconductor substrate of the first semiconductor element is located outside an outer peripheral part of the semiconductor substrate of the second semiconductor element. The semiconductor device according to claim 11, wherein:
Having a fourth semiconductor element or substrate;
The second semiconductor element is disposed between the first semiconductor element and the fourth semiconductor element or the substrate;
A semiconductor device in which an outer peripheral part of the fourth semiconductor element or the substrate is located outward from an outer peripheral part of the semiconductor substrate of the second semiconductor element. The semiconductor device according to claim 11,
The semiconductor substrate of the first semiconductor element has a main body portion provided with the connection terminal on one end surface, and projects outward from the periphery of the other end surface of the main body portion, and A semiconductor device having a collar portion constituting the outer shell. The semiconductor device according to claim 16, wherein
A semiconductor device in which a side surface of the semiconductor substrate of the second semiconductor element is a surface position with a side surface of the main body of the first semiconductor element. The semiconductor device according to claim 16, wherein
The semiconductor substrate of the second semiconductor element has a main body portion in which the one connection terminal is formed on one end surface and the other connection terminal is formed on the other end surface, and the one of the main body portions. Having a buttock projecting outward from the peripheral edge of the end face,
A semiconductor device in which the flange portion of the first semiconductor element and the flange portion of the second semiconductor element are spaced apart from each other. The semiconductor device according to claim 11,
The semiconductor substrate of the second semiconductor element has a main body portion in which the one connection terminal is formed on one end surface and the other connection terminal is formed on the other end surface, and the other end surface of the main body portion. Having a buttock projecting outward from the periphery of the
The outer peripheral part of the semiconductor substrate of the first semiconductor element is located outside the outer peripheral part of the main body part of the second semiconductor element,
A semiconductor device in which an outer peripheral portion of the semiconductor substrate of the first semiconductor element and the flange portion of the second semiconductor element are spaced apart from each other. The semiconductor device according to claim 11,
The semiconductor device, wherein the first semiconductor element is a semiconductor element having the semiconductor substrate and a through via that penetrates the semiconductor substrate and is connected to the connection terminal.

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