JP6032345B2 - Adhesive film - Google Patents

Description

The present invention relates to an adhesive film .

Conventionally, a semiconductor device configured by stacking a plurality of semiconductor elements or a semiconductor device having semiconductor elements stacked on a substrate has been used (for example, Patent Document 1).
In such a semiconductor device, a resin layer (adhesive composition) that seals a connection portion between semiconductor elements or a connection portion between a semiconductor element and a substrate is used.
This adhesive composition is thermosetting, and in Patent Document 1, it contains a polyimide resin, an epoxy resin, a curing agent, a carboxylic acid, and the like.

JP 2011-29392 A

  In such a semiconductor device, there is a concern that cracks may occur in the semiconductor element.

As a result of studies by the present inventors, the following has been found as the cause of cracks occurring in the semiconductor element.
It is considered that there is a stress in the resin layer surrounding the connection part between the semiconductor elements, and this stress acts on the semiconductor element to cause a crack.
And it is thought that the stress which exists in this resin layer generate | occur | produces in the process of thermosetting a resin layer. In the thermosetting step, the resin layer after thermosetting is lowered from the thermosetting temperature to the glass transition point. It has been found that due to this temperature change, a stress is generated in the resin layer, and this stress is greatly related to the occurrence of cracks in the semiconductor element. And it discovered that generation | occurrence | production of the crack of a semiconductor element can be suppressed by satisfy | filling specific conditions.

That is, according to the present invention,
An adhesive film that bonds the first semiconductor element and the second semiconductor element that are connected to each other through the connection terminals,
The first semiconductor element and the second semiconductor element are respectively
A TSV structure semiconductor chip comprising a substrate and a through via that penetrates the substrate and is connected to the connection terminal;
The adhesive film is
A thermosetting resin;
A flux active compound,
The glass transition temperature of the adhesive film is Tg,
The average linear expansion coefficient of the cured product of the adhesive film from Tg to 280 ° C. is α ₂ (ppm / ° C.),
The elastic modulus at the Tg of the cured product of the adhesive film is E ′ (Pa),
When Tc is a thermosetting temperature exceeding the Tg in the cured product,
E ′ × α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa)
E ′ is 1.0 × 10 ⁸ Pa or more and 1.0 × 10 ¹⁰ Pa or less,
Α ₂ is 30 ppm / ° C. or more and 300 ppm / ° C. or less,
The (Tc−Tg) is 5 ° C. or more and 100 ° C. or less,
An adhesive film having the Tg of 80 ° C. or higher and 180 ° C. or lower is provided.
Also according to the invention,
An electronic component, a thermosetting first resin layer, a TSV structure first semiconductor element, a thermosetting second resin layer, and a TSV structure second semiconductor element are laminated in this order, and the first semiconductor element In a semiconductor device comprising a laminate in which the second semiconductor element and the second semiconductor element are connected to each other via a connection terminal, an adhesive film used for the first resin layer and the second resin layer,
A thermosetting resin;
A flux active compound,
The glass transition temperature of the adhesive film is Tg,
The average linear expansion coefficient of the cured product of the adhesive film from Tg to 280 ° C. is α ₂ (ppm / ° C.),
The elastic modulus at the Tg of the cured product of the adhesive film is E ′ (Pa),
When Tc is a thermosetting temperature exceeding the Tg in the cured product,
E ′ × α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa)
E ′ is 1.0 × 10 ⁸ Pa or more and 1.0 × 10 ¹⁰ Pa or less,
Α ₂ is 30 ppm / ° C. or more and 300 ppm / ° C. or less,
The (Tc−Tg) is 5 ° C. or more and 100 ° C. or less,
An adhesive film having the Tg of 80 ° C. or higher and 180 ° C. or lower is provided.
Also according to the invention,
An electronic component, a thermosetting first resin layer, a TSV structure first semiconductor element, a thermosetting second resin layer, and a TSV structure second semiconductor element are laminated in this order, and the first semiconductor element And the second semiconductor element are used for the first adhesive film used for the first resin layer and the second resin layer in a semiconductor device including a laminate in which the second semiconductor elements are connected to each other via a connection terminal An adhesive film for a TSV structure comprising a second adhesive film,
Each of the first adhesive film and the second adhesive film is
A thermosetting resin;
A flux active compound,
The glass transition temperature of the adhesive film is Tg,
The average linear expansion coefficient of the cured product of the adhesive film from Tg to 280 ° C. is α ₂ (ppm / ° C.),
The elastic modulus at the Tg of the cured product of the adhesive film is E ′ (Pa),
When Tc is a thermosetting temperature exceeding the Tg in the cured product,
E ′ × α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa)
E ′ is 1.0 × 10 ⁸ Pa or more and 1.0 × 10 ¹⁰ Pa or less,
Α ₂ is 30 ppm / ° C. or more and 300 ppm / ° C. or less,
The (Tc−Tg) is 5 ° C. or more and 100 ° C. or less,
An adhesive film having the Tg of 80 ° C. or higher and 180 ° C. or lower is provided.

ADVANTAGE OF THE INVENTION According to this invention , the adhesive film which can suppress generation | occurrence | production of the crack in a semiconductor device and can improve the productivity of a semiconductor device is provided.

It is process sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. It is a figure which shows the apparatus which heats a laminated body. It is process sectional drawing which shows the manufacturing process of a semiconductor device. It is process sectional drawing which shows the modification of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and detailed description thereof is appropriately omitted so as not to overlap.
First, a method for manufacturing a semiconductor device of this embodiment will be described with reference to FIG.
The semiconductor device manufacturing method of the present embodiment includes an electronic component (for example, a semiconductor chip 10), a thermosetting first resin layer (for example, a resin layer 11), a first semiconductor element (for example, a semiconductor chip 12), a heat This is a method for manufacturing a semiconductor device in which a curable second resin layer (for example, resin layer 13) and a second semiconductor element (for example, semiconductor chip 14) are laminated in this order.
In this manufacturing method, the connection terminal of the first semiconductor element and the connection terminal of the electronic component are brought into contact with each other, and the connection terminal that is in contact with each other between the first semiconductor element and the electronic component. Arrange the first resin layer to surround the periphery,
While contacting the other connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element,
A step of configuring the laminate 2 by disposing the other connection terminals in contact with each other and the second resin layer surrounding the connection terminals between the first semiconductor element and the second semiconductor element; ,
Heating the laminate 2 and thermosetting the first resin layer and the second resin layer.
In the step of heating the laminate 2 and thermosetting the first resin layer and the second resin layer,
At the thermosetting temperature Tc (° C.) exceeding the glass transition point Tg ₁ (° C.) of the first resin layer and the glass transition point Tg ₂ (° C.) of the second resin layer of the laminate 2 after the thermosetting, After thermosetting the first resin layer and the second resin layer of the laminate 2, the glass transition point Tg ₁ (° C.) of the first resin layer and the second resin layer from the thermosetting temperature Tc (° C.). The first resin layer and the second resin layer are cooled to a temperature lower than the glass transition point Tg ₂ (° C.).
And let the average linear expansion coefficient of said Tg ₁ or more and 280 degrees C or less of the said 1st resin layer of the said laminated body 2 after the said thermosetting be (alpha) _2-1 (ppm / degreeC),
When the elastic modulus at the Tg ₁ of the first resin layer of the laminate 2 after the thermosetting is E ′ ₁ (Pa),
E ′ ₁ × α _2-1 × (Tc-Tg ₁ ) ≦ 2.7 × 10 ⁷ (Pa)
And
The average linear expansion coefficient of the second resin layer of the laminate 2 after the thermosetting is not less than Tg _{2 and not} more than 280 ° C. is α _2-2 (ppm / ° C.),
When the elastic modulus at the Tg ₂ of the second resin layer of the laminate 2 after the thermosetting is E ′ ₂ (Pa),
E ′ ₂ × α _2-2 × (Tc-Tg ₂ ) ≦ 2.7 × 10 ⁷ (Pa)
It becomes.

Next, with reference to FIGS. 1-3, one Embodiment of the manufacturing method of the semiconductor device of this embodiment is described in detail.
First, as shown in FIG. 1A, a semiconductor chip 10 is prepared. The semiconductor chip 10 includes a substrate and terminals (terminals for connection to the semiconductor chip 12) 101 provided on the surface of the substrate. An internal circuit or the like is built in the substrate. In this embodiment, a via that penetrates the substrate is not provided. For example, the connection terminal 101 has a structure in which a copper layer, a nickel layer, and a gold layer are laminated in this order from the substrate side. However, the structure of the connection terminal 101 is not limited to this.
Here, the thickness of the semiconductor chip 10 is not particularly limited, but may be, for example, 50 to 750 μm.
Further, no terminal is provided on the other substrate surface (back surface) side of the semiconductor chip 10.

  Further, as shown in FIG. 1A, a semiconductor chip 12 is prepared. The semiconductor chip 12 is a semiconductor element having a TSV structure having a substrate (for example, a silicon substrate) 120 and a via 123 penetrating the substrate 120. An internal circuit or the like is built in the substrate 120. A terminal 121 is provided on one surface of the substrate 120, and a terminal 122 is provided on the other surface. The terminals 121 and 122 are connected by vias 123. The terminal 121 is a connection terminal connected to the semiconductor chip 10, and the terminal 122 is a connection terminal connected to the semiconductor chip 14.

The via 123 is made of, for example, a metal such as copper or conductive polysilicon doped with impurities.
The terminal 122 has a layer configuration similar to that of the terminal 101, for example.
The terminal 121 has a solder layer 121A on the surface. The connection terminal 121 has a structure in which, for example, a nickel layer is stacked on a copper layer, and a solder layer 121A is provided so as to cover the nickel layer.
The material of the solder layer 121A is not particularly limited, and examples thereof include an alloy containing at least one selected from the group consisting of tin, silver, lead, zinc, bismuth, indium, and copper. Among these, an alloy containing at least one selected from the group consisting of tin, silver, lead, zinc and copper is preferable. The melting point of the solder layer 121A is 110 to 250 ° C, preferably 170 to 230 ° C.

The resin layer 11 is provided on the surface of the semiconductor chip 12 on the side where the terminals 121 are provided.
The resin layer 11 covers the terminals 121. The resin layer 11 is a layer containing a thermosetting resin and a flux active compound, as will be described in detail later.

Further, a semiconductor chip 14 and a semiconductor chip 16 are also prepared (see FIG. 1A).
The semiconductor chip 14 is a semiconductor element having a TSV structure having a substrate (semiconductor substrate, for example, a silicon substrate) and a via 143 penetrating the substrate 140. An internal circuit or the like is built in the substrate. A terminal 141 is provided on one surface of the substrate, and a terminal 142 is provided on the other surface. The terminal 141 and the terminal 142 are connected by a via 143.
The semiconductor chip 16 is a semiconductor element having a TSV structure including a substrate (semiconductor substrate, for example, a silicon substrate) and a via 163 penetrating the substrate 160. An internal circuit or the like is built in the substrate, and a terminal 161 is provided on one surface of the substrate, and a terminal 162 is provided on the other surface. The terminal 161 and the terminal 162 are connected by a via 163.

The vias 143 and 163 are made of the same material as the via 123.
The terminals 142 and 162 have the same configuration and material as the terminal 122, and the terminals 141 and 161 have the same configuration and material as the terminal 121. Reference numerals 141A and 161A are solder layers similar to the solder layer 121A.
The semiconductor chip 14 is provided with a resin layer 13 that covers the terminals 141. The semiconductor chip 16 is provided with a resin layer 15 that covers the terminals 161.

Here, as a method of providing the resin layers 11, 13, and 15 on the semiconductor chips 12, 14, and 16, for example, the following methods can be cited.
Resin layers 11, 13, and 15 are attached to the semiconductor chips 12, 14, and 16, respectively.
In addition, a wafer in which the semiconductor chips 12, 14, and 16 are integrated is prepared in advance, and a resin sheet in which the resin layers 11, 13, and 15 are integrated is attached to the wafer. Then, the semiconductor chip 12 with the resin layer 11, the semiconductor chip 14 with the resin layer 13, and the semiconductor chip 16 with the resin layer 15 may be prepared by dicing the resin sheet and the wafer.
Further, a wafer in which the semiconductor chips 12, 14, and 16 are integrated is prepared, and a resin layer in which the resin layers 11, 13, and 15 are integrated is formed on the wafer by spin coating, and then dicing is performed, whereby the resin is formed. A semiconductor chip 12 with the layer 11, a semiconductor chip 14 with the resin layer 13, and a semiconductor chip 16 with the resin layer 15 may be prepared.

In the present embodiment, the semiconductor chips 10, 12, 14, and 16 have the same size in plan view (plan view when viewed from the substrate surface side). Further, the thickness of the substrates 120, 140, 160 of the semiconductor chips 12, 14, 16 is preferably 10 μm or more, more preferably 20 μm or more. Further, it is preferably 150 μm or less, more preferably 100 μm or less, and further preferably 50 μm or less, which is very thin.
Furthermore, in the present embodiment, examples of the semiconductor chips 10, 12, 14, and 16 include memory chips such as DRAM and SRAM, logic chips, CMOS image sensors, MEMS chips, and the like. , 16 can be selected from these.
Here, although not shown, dicing lines surrounding the internal circuit region remain in a frame shape at the peripheral edge portions of the substrates of the semiconductor chips 12, 14, and 16. A semiconductor element is obtained by cutting a wafer in which a plurality of semiconductor elements are integrated along a dicing line. However, a dicing line remains on the substrate of each semiconductor element. In the present embodiment, the size and shape of the region surrounded by the dicing line of each substrate is the same.
Further, the semiconductor chips 12, 14, 16 may be semiconductor elements having the same function, or may be semiconductor elements having different functions. For example, the internal circuits of the semiconductor elements 12, 14, and 16 may have the same layout or different layouts.

Next, the resin layers 11, 13, and 15 will be described.
The thickness of each resin layer 11, 13, 15 provided in each semiconductor chip is preferably 5 μm or more, for example, and more preferably 10 μm or more. Moreover, it is preferable that it is 100 micrometers or less, More preferably, it is 50 micrometers or less. By setting it to the above lower limit value or more, the resin layer can surely cover the solder layer, and the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 can be easily connected by the flux activity of the resin layer. it can. Moreover, by setting it as the said upper limit or less, the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 can be easily connected. Furthermore, the curvature of the semiconductor chips 12, 14, and 16 due to curing shrinkage of the resin layer can be suppressed by setting the upper limit value or less.

Here, the resin layers 11, 13, and 15 will be described. The resin layers 11, 13, and 15 are for filling gaps between the semiconductor chips 10 and 12, between the semiconductor chips 12 and 14, and between the semiconductor chips 14 and 16, respectively.
The resin layers 11, 13, and 15 each include a thermosetting resin and a flux active compound.
Here, all of the resin layers 11, 13, and 15 may be made of the same resin composition, or may be made of different resin compositions.
As the thermosetting resin, for example, epoxy resin, oxetane resin, phenol resin, (meth) acrylate resin, unsaturated polyester resin, diallyl phthalate resin, maleimide resin and the like can be used. These can be used individually or in mixture of 2 or more types.
Among them, an epoxy resin excellent in curability and storage stability, heat resistance, moisture resistance, and chemical resistance of a cured product is preferably used. The content of the thermosetting resin in the resin layers 11, 13, and 15 is preferably 10% by mass or more, and more preferably 25% by mass or more. Moreover, it is preferable that it is 70 mass% or less, More preferably, it is 60 mass% or less.

The resin layers 11, 13, and 15 are resin layers that have an action of removing an oxide film on the surface of the solder layer and the terminal during solder joining. Since the resin layers 11, 13, and 15 have a flux action, the oxide film covering the surface of the solder and the terminals is removed, so that the solder bonding can be performed. In order for the resin layers 11, 13, and 15 to have a flux action, the resin layers 11, 13, and 15 need to contain a flux active compound. The flux active compound contained in the resin layers 11, 13 and 15 is not particularly limited as long as it is used for solder bonding.
However, it is preferable that the flux active compound includes at least one of a compound having a carboxyl group and a compound having a phenolic hydroxyl group. Moreover, both may be included. The flux active compound may be a compound having both a carboxyl group and a phenolic hydroxyl group.

  It is preferable that the compounding quantity of the flux active compound in the resin layers 11, 13, and 15 is 1 mass% or more, More preferably, it is 3 mass% or more. Moreover, it is preferable that it is 30 mass% or less, More preferably, it is 20 mass% or less.

  Examples of the flux active compound having a carboxyl group include an aliphatic acid anhydride, an alicyclic acid anhydride, an aromatic acid anhydride, an aliphatic carboxylic acid, and an aromatic carboxylic acid.

  Examples of the aliphatic acid anhydride related to the flux active compound having a carboxyl group include succinic anhydride, polyadipic acid anhydride, polyazeline acid anhydride, polysebacic acid anhydride, and the like.

  Examples of alicyclic acid anhydrides related to flux active compounds having a carboxyl group include methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylhymic anhydride, hexahydrophthalic anhydride, tetrahydrophthalic anhydride, trialkyltetrahydro Examples thereof include phthalic anhydride and methylcyclohexene dicarboxylic acid anhydride.

  Aromatic acid anhydrides related to flux active compounds having a carboxyl group include phthalic anhydride, trimellitic anhydride, pyromellitic anhydride, benzophenone tetracarboxylic anhydride, ethylene glycol bistrimellitate, glycerol tris trimellitate, etc. Is mentioned.

Examples of the aliphatic carboxylic acid related to the flux active compound having a carboxyl group include compounds represented by the following general formula (I), formic acid, acetic acid, propionic acid, butyric acid, valeric acid, pivalic acid caproic acid, caprylic acid, lauric acid , Myristic acid, palmitic acid, stearic acid, acrylic acid, methacrylic acid, crotonic acid, oleic acid, fumaric acid, maleic acid, oxalic acid, malonic acid, oxalic acid and the like.
_{HOOC- (CH 2) n -COOH (} I)
(In the formula (I), n represents an integer of 0 or more and 20 or less.)

  Aromatic carboxylic acids related to flux active compounds with carboxyl groups include benzoic acid, phthalic acid, isophthalic acid, terephthalic acid, hemimellitic acid, trimellitic acid, trimesic acid, merophanic acid, planitic acid, pyromellitic acid, merit Acid, triyl acid, xylyl acid, hemelic acid, mesitylene acid, prenylic acid, toluic acid, cinnamic acid, salicylic acid, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2,5-dihydroxy) Benzoic acid), 2,6-dihydroxybenzoic acid, 3,5-dihydroxybenzoic acid, gallic acid (3,4,5-trihydroxybenzoic acid), 1,4-dihydroxy-2-naphthoic acid, 3,5 -Naphthoic acid derivatives such as dihydroxy-2-naphthoic acid, phenolphthaline, diphenol Etc. The.

  Among these flux active compounds having a carboxyl group, there is a good balance between the activity of the flux active compound, the amount of outgas generated when the resin layer is cured, and the elastic modulus and glass transition temperature of the cured resin layer. The compound represented by the general formula (I) is preferable. And among the compounds shown by said general formula (I), while the compound whose n in Formula (I) is 3-10 can suppress that the elasticity modulus in the resin layer after hardening increases. In particular, it is preferable in that the adhesiveness can be improved.

Among the compounds represented by the general formula (I), examples of the compound in which n in the formula (I) is 3 to 10 include, for example, n = 3 glutaric acid (HOOC— (CH ₂ ) ₃ —COOH), n = 4 adipic acid (HOOC— (CH ₂ ) ₄ —COOH), n = 5 pimelic acid (HOOC— (CH ₂ ) ₅ —COOH), n = 8 sebacic acid (HOOC— (CH ₂ ) ₈ -COOH) and of _{n = 10 HOOC- (CH 2)} 10 -COOH , and the like.

  Examples of the flux active compound having a phenolic hydroxyl group include phenols. Specifically, for example, phenol, o-cresol, 2,6-xylenol, p-cresol, m-cresol, o-ethylphenol, 2 , 4-xylenol, 2,5-xylenol, m-ethylphenol, 2,3-xylenol, meditol, 3,5-xylenol, p-tertiarybutylphenol, catechol, p-tertiaryamylphenol, resorcinol, p-octylphenol , Monomers containing phenolic hydroxyl groups such as p-phenylphenol, bisphenol A, bisphenol F, bisphenol AF, biphenol, diallyl bisphenol F, diallyl bisphenol A, trisphenol, tetrakisphenol , Phenol novolak resins, o- cresol novolak resin, bisphenol F novolac resin, bisphenol A novolac resins.

The flux active compounds described above may be used singly or in combination of two or more.
A compound having either a carboxyl group or a phenolic hydroxyl group as described above, or a compound having both a carboxyl group and a phenolic hydroxyl group is incorporated three-dimensionally by reaction with a thermosetting resin such as an epoxy resin.

Therefore, from the viewpoint of improving the formation of a three-dimensional network of the epoxy resin after curing, the flux active compound is preferably a flux active curing agent having a flux action and acting as a curing agent for the epoxy resin. Examples of the flux active curing agent include, in one molecule, two or more phenolic hydroxyl groups that can be added to an epoxy resin, and one or more carboxyls directly bonded to an aromatic group that exhibits a flux action (reduction action). And a compound having a group.
Such flux active curing agents include 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2,5-dihydroxybenzoic acid), 2,6-dihydroxybenzoic acid, 3,4- Benzoic acid derivatives such as dihydroxybenzoic acid and gallic acid (3,4,5-trihydroxybenzoic acid); 1,4-dihydroxy-2-naphthoic acid, 3,5-dihydroxy-2-naphthoic acid, 3,7- Examples thereof include naphthoic acid derivatives such as dihydroxy-2-naphthoic acid; phenolphthaline; and diphenolic acid. These may be used alone or in combination of two or more.
Especially, in order to make the joining between terminals favorable, it is particularly preferable to use phenolphthaline.

  Further, the blending amount of the flux active curing agent in the resin layer is preferably 1% by mass or more, more preferably 3% by mass or more. Moreover, it is preferable that it is 30 mass% or less, More preferably, it is 20 mass% or less. When the blending amount of the flux active curing agent in the resin layer is within the above range, the flux activity of the resin layer can be improved, and the thermosetting resin and the unreacted flux active curing agent are contained in the resin layer. Is prevented from remaining.

Moreover, the resin layer may contain the inorganic filler. By including an inorganic filler in the resin layer, it is possible to increase the minimum melt viscosity of the resin layer and to prevent a gap from being formed between the terminals. Here, examples of the inorganic filler include silica and alumina, and any one or more of them can be used.
The inorganic filler is preferably 20% by mass or more in the resin layer, more preferably 25% by mass or more, and particularly preferably 30% by mass or more. Moreover, it is preferable that it is 80 mass% or less, More preferably, it is 70 mass% or less, Most preferably, it is 60 mass% or less. By setting the content of the inorganic filler to the above lower limit value or more, the linear expansion coefficient of the resin layer can be reduced. On the other hand, the moldability of a resin layer can be made favorable by making content of an inorganic filler below into the said upper limit.
The inorganic filler preferably has an average particle size of 0.5 μm or less. By setting the average particle size of the inorganic filler to 0.5 μm or less, conduction between the terminals can be ensured even if the inorganic filler may be sandwiched between the terminals. As will be described in detail later, when the terminals are soldered together, a resin layer is interposed between the terminals, the terminal bites into this resin layer, the resin layer is excluded from between the terminals, and the terminals are soldered together To do. In this step, the inorganic filler may be sandwiched between the terminals. However, by setting the average particle size of the inorganic filler to 0.5 μm or less, conduction between the terminals can be secured, and connection reliability can be ensured. A high semiconductor device can be provided.

  Furthermore, the resin layer may contain a thermoplastic resin. Thereby, the resin layer can be easily formed into a film shape, and a semiconductor device excellent in connectivity and insulation reliability can be manufactured efficiently.

  Examples of the thermoplastic resin include (meth) acrylic resin, phenoxy resin, polyester resin, polyurethane resin, polyimide resin, siloxane-modified polyimide resin, polybutadiene, polypropylene, styrene-butadiene-styrene copolymer, styrene-ethylene-butylene. -Styrene copolymer, polyacetal resin, polyvinyl butyral resin, polyvinyl acetal resin, butyl rubber, chloroprene rubber, polyamide resin, acrylonitrile-butadiene copolymer, acrylonitrile-butadiene-acrylic acid copolymer, acrylonitrile-butadiene-styrene copolymer , Polyvinyl acetate, nylon and the like. Any one or more of these can be used.

  Among these, (meth) acrylic resins and phenoxy resins are preferable. By applying a (meth) acrylic resin or a phenoxy resin, it is possible to achieve both film formability of the resin layer and adhesion to the support and adherend. A thermoplastic resin may be used alone or in combination of two or more.

  In the thermoplastic resin, the (meth) acrylic resin means a polymer of (meth) acrylic acid and its derivative, or a copolymer of (meth) acrylic acid and its derivative and another monomer. To do. Here, when it describes with (meth) acrylic acid etc., it means acrylic acid or methacrylic acid.

Specific examples of the acrylic resin used as the thermoplastic resin include polyacrylic acid, polymethacrylic acid, polymethyl acrylate, polyethyl acrylate, polybutyl acrylate, and polyacrylic acid-2-ethylhexyl. Acrylic acid ester; polymethacrylic acid ester such as polymethyl methacrylate, polyethyl methacrylate, polybutyl methacrylate; polyacrylonitrile, polymethacrylonitrile, polyacrylamide, butyl acrylate-ethyl acrylate-acrylonitrile copolymer, acrylonitrile -Butadiene copolymer, acrylonitrile-butadiene-acrylic acid copolymer, acrylonitrile-butadiene-styrene copolymer, acrylonitrile-styrene copolymer, methyl methacrylate-styrene copolymer, Methyl crylate-acrylonitrile copolymer, methyl methacrylate-α-methylstyrene copolymer, butyl acrylate-ethyl acrylate-acrylonitrile-2-hydroxyethyl methacrylate-methacrylic acid copolymer, butyl acrylate-ethyl acrylate -Acrylonitrile-2-hydroxyethyl methacrylate-acrylic acid copolymer, butyl acrylate-acrylonitrile-2-hydroxyethyl methacrylate copolymer, butyl acrylate-acrylonitrile-acrylic acid copolymer, butyl acrylate-ethyl acrylate- Examples include acrylonitrile copolymer, ethyl acrylate-acrylonitrile-N, N dimethylacrylamide copolymer, and the like. Any one or more of these can be used.
Among these, any of butyl acrylate-ethyl acrylate-acrylonitrile copolymer and ethyl acrylate-acrylonitrile-N, N dimethylacrylamide copolymer is preferable.

  In addition, by using a (meth) acrylic resin obtained by copolymerizing a monomer having a functional group such as a nitrile group, an epoxy group, a hydroxyl group, or a carboxyl group as the acrylic resin, Adhesiveness to a support and an adherend and compatibility with a thermosetting resin can be improved.

The acrylic resin preferably has a weight average molecular weight of, for example, 1,000 or more and 1,000,000 or less, and more preferably 3000 or more and 900,000 or less.
When the weight average molecular weight of the acrylic resin is within the above range, the film formability of the resin layer can be further improved and the fluidity at the time of curing can be ensured.

Moreover, when using a phenoxy resin as a thermoplastic resin, it is preferable that the number average molecular weights are 5000 or more and 20000 or less.
When the number average molecular weight of the phenoxy resin is within the above range, the fluidity of the resin layer can be suppressed and the thickness of the film-like resin layer can be made uniform.

  The skeleton of the phenoxy resin is not particularly limited, and examples thereof include bisphenol A type, bisphenol F type, biphenyl skeleton type, and biphenol skeleton type.

In the resin layer, the content of the thermoplastic resin relative to the entire resin layer is not particularly limited, but is preferably 0.1% by mass or more, and more preferably 0.2% by mass or more. Moreover, it is preferable that it is 20 mass% or less, More preferably, it is 10 mass% or less.
By making content of a thermoplastic resin in the said range, the increase in the elasticity modulus in the film-form resin layer after hardening can be suppressed, suppressing the film formability fall of a film-form resin layer. As a result, the adhesion between the film-like resin layer, the support and the adherend can be further improved. Furthermore, an increase in the melt viscosity of the film-like resin layer can be suppressed.

(Process for forming a laminate)
Next, as shown in FIGS. 1A to 1D, a laminate including the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, the semiconductor chip 14, the resin layer 15, and the semiconductor chip 16. 2 is formed.
First, as shown in FIG. 1A, the surface of the semiconductor chip 10 on which the terminals 101 are formed and the resin layer 11 provided on the semiconductor chip 12 face each other, and the resin layer 11 is formed on the semiconductor chip 10. Then, the semiconductor chip 12 is stacked.
At this time, alignment is performed by confirming the alignment mark formed on the semiconductor chip 10 and the alignment mark formed on the semiconductor chip 12.
Thereafter, the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12 are heated, and the semiconductor chip 10 and the semiconductor chip 12 are bonded via the semi-cured resin layer 11 (B stage). At this time, the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12 are sandwiched between a pair of sandwiching members with built-in heaters, thereby heating the semiconductor chip 10, the resin layer 11, and the semiconductor chip 12, and the pair of sandwiching members. The semiconductor chip 10 and the semiconductor chip 12 can be bonded together by being pinched by the pressure member and applying a load. For example, using a flip chip bonder, the semiconductor chip 10 and the semiconductor chip 12 are bonded via the resin layer 11 in the atmosphere under atmospheric pressure. The heating temperature at this time is not particularly limited as long as the thermosetting resin of the resin layer 11 is not completely cured, but is preferably lower than the curing temperature of the thermosetting resin.
Whether or not the position of the semiconductor chip 12 relative to the semiconductor chip 10 after bonding can be accurately confirmed using, for example, an X-ray microscope or an infrared microscope.
The resin layer being in a semi-cured state (B stage) is a state having a hardness that can fix the electronic components and semiconductor elements above and below the resin layer, and there is room for further curing reaction. State. Such a semi-cured state is not particularly limited, but can be confirmed, for example, by measuring the reaction rate of the resin layer. Specifically, the uncured resin layer and the cured resin layer are measured by DSC (differential scanning calorimeter), and the reaction rate calculated from the DSC measurement result exceeds 0% and is 60% or less. The state is preferably 0.5% to 55%, more preferably 1% to 50%.

Next, as shown in FIG. 1B, the surface of the semiconductor chip 12 on which the terminals 122 are provided and the resin layer 13 face each other, and the semiconductor chip 14 is placed on the semiconductor chip 12 with the resin layer 13 interposed therebetween. Laminate.
At this time, alignment is performed by confirming the alignment mark formed on the semiconductor chip 12 and the alignment mark formed on the semiconductor chip 14.
Thereafter, the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, and the semiconductor chip 14 are heated, and the semiconductor chip 12 and the semiconductor chip 14 are moved through the resin layer 13 in a semi-cured state (B stage). Glue. At this time, the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, and the semiconductor chip 14 are heated by sandwiching the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, and the semiconductor chip 14 with a pair of sandwiching members, The semiconductor chip 12 and the semiconductor chip 14 can be bonded by applying a load. For example, the semiconductor chip 12 and the semiconductor chip 14 are bonded in the atmosphere under atmospheric pressure using a flip chip bonder. The heating temperature at this time is not particularly limited as long as the thermosetting resin of the resin layer 13 is not completely cured, but is preferably lower than the curing temperature of the thermosetting resin.
Whether or not the position of the semiconductor chip 14 relative to the semiconductor chip 12 after bonding can be accurately confirmed using, for example, an X-ray microscope or an infrared microscope.
In the above process, the solder layers 121A and 141A are not melted, and the terminals 101 and 121 and the terminals 122 and 141 are not soldered. The terminals 101 and 121 may be in physical contact with each other, and the resin of the resin layer 11 may be interposed between the terminals 101 and 121. The same applies to the terminals 122 and 141.

As shown in FIG. 1C, the semiconductor chip 16 with the resin layer 15 is attached to the pinching member 43. On the other hand, a laminated body including the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, and the semiconductor chip 14 is installed on the pinching member 44.
Next, the clamping members 44 and 43 are brought close to each other, and the resin layer 15 of the semiconductor chip 16 with the resin layer 15 is brought into contact with the semiconductor chip 14. Thus, the stacked body 2 is configured. Here, the semiconductor chip 16 is not bonded to the semiconductor chip 14 via the resin layer 15.
Thereafter, the heaters in the pinching members 44 and 43 start to rise in temperature. The laminated body 2 is heated to the melting point or higher of the solder layers 121A, 141A, 161A via the pinching members 44, 43 and is pinched by the pinching members 44, 43 so that the terminals 101, 121 and the terminals 122, 141 are The terminals 142 and 161 are soldered together.

At this time, when the resin layer 11 is interposed between the solder layer 121A of the terminal 101 and the terminal 121, the terminal 101 and the solder layer 121A of the terminal 121 bite into the interposed resin layer 11, and the terminal 101, terminal The resin layer 11 between the 121 solder layers 121A is eliminated, the terminals 101 and 121A of the solder layers 121A come into contact with each other, and then soldered.
The same is true between the solder layer 141A of the terminal 122 and the terminal 141 and between the solder layer 161A of the terminal 142 and the terminal 161.
That is, when the resin layer 13 is interposed between the solder layer 141A of the terminal 122 and the terminal 141, the terminal 122 and the solder layer 141A of the terminal 141 bite into the interposed resin layer 13, and the terminal 122 and the terminal 141 are inserted. The resin layer 13 between the solder layers 141A is eliminated, the terminals 122 and the solder layers 141A of the terminals 141 are brought into contact, and then soldered.
When the resin layer 15 is interposed between the solder layer 161A of the terminal 142 and the terminal 161, the terminal 142 and the solder layer 161A of the terminal 161 bite into the interposed resin layer 15, and the terminal 142 and the terminal 161 are inserted. The resin layer 15 between the solder layers 161A is eliminated, the terminals 142 and the solder layer 161A of the terminals 161 come into contact with each other, and then soldered.

Here, for example, solder bonding can be performed using a flip chip bonder.
Whether or not the position of the semiconductor chip 16 with respect to the semiconductor chip 14 after bonding can be accurately confirmed using, for example, an X-ray microscope or an infrared microscope.
The soldering between terminals means the following. The laminated body 2 is heated to the melting point or higher of the solder layers 121A, 141A, 161A, and the solder layers 121A, 141A used for bonding between the semiconductor chips 10, 12, between the semiconductor chips 12, 14, and between the semiconductor chips 14, 16 are used. 161A is melted, and the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are in contact with each other via the solder layers 121A, 141A, and 161A, and at least a part forms an alloy. It is.

In the laminated body 2 obtained as described above, the side surfaces of the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, the semiconductor chip 14, the resin layer 15, and the semiconductor chip 16 are gradually viewed from the top. The resin layers 11, 13, and 15 may protrude from the side surfaces of the semiconductor chips 10, 12, 14, and 16.
Moreover, although the laminated body 2 is formed by the above process, in the laminated body 2, the resin layers 11, 13, and 15 are in a semi-cured state without being completely cured.

(Thermosetting process)
Next, as shown in FIG. 2, the resin layers 11, 13, and 15 of the laminate 2 in which the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are solder-bonded are cured (thermosetting process). ). By passing through this thermosetting process, the curing of the resin layers 11, 13, and 15 proceeds greatly. In the semiconductor device manufacturing process, there are a plurality of processes in which the resin layer is heated. In this thermosetting process, the resin layers 11, 13, and 15 are most cured, and the resin layer 11 is semi-cured. , 13, 15 are C-stages (complete curing).
Rb _{11 represents} the reaction rate (%: the same applies hereinafter) of the resin layer 11 after the solder bonding step and before this heat curing step (immediately before the heat curing step), and Ra _{11 represents} the reaction rate of the resin layer 11 immediately after the heat curing step. In this case, Ra ₁₁ -Rb ₁₁ is 60% or more, preferably 85% or more.
Similarly, when the reaction rate of the resin layer 13 before the thermosetting step after the solder bonding step is Rb ₁₃ and the reaction rate of the resin layer 13 immediately after the thermosetting step is Ra ₁₃ , Ra ₁₃ -Rb ₁₃ is: 60% or more, preferably 85% or more.
Further, when the reaction rate of the resin layer 15 after the soldering step and before the thermosetting step is Rb ₁₅ , and the reaction rate of the resin layer 15 immediately after the thermosetting step is Ra ₁₅ , Ra ₁₅ -Rb ₁₅ is 60 % Or more, preferably 85% or more.
Here, “immediately after the thermosetting process” is a state in which no subsequent process is performed after the end of the thermosetting process, and a heating process that changes the reaction rate of the resin layer is added after the end of the thermosetting process. It means no state.

The resin layers 11, 13, and 15 can be cured using, for example, the apparatus 6 shown in FIG.
First, the device 6 includes a container 61 and a pipe 611 that supplies a fluid into the container 61.
The container 61 is a pressure container, and examples of the material of the container 61 include metals, and examples thereof include any metal such as stainless steel, titanium, and copper.
A fluid for pressurizing the stacked body 2 is supplied from the pipe 611. As the fluid, gas is preferable, and examples thereof include air and inert gas (nitrogen gas, rare gas).
The pressure applied when the laminate 2 is pressurized with a fluid is preferably 0.1 MPa or more and 10 MPa or less, more preferably 0.5 MPa or more and 5 MPa or less. By pressurizing the laminate 2 with a fluid, the generation of voids in the resin layers 11, 13 and 15 can be suppressed. In particular, when the pressure is 0.1 MPa or more, this effect becomes remarkable. Moreover, the enlargement and complication of an apparatus can be suppressed by setting it as 10 Mpa or less. In addition, pressurizing with a fluid refers to making the pressure of the atmosphere of the laminated body 2 higher than the atmospheric pressure by the applied pressure. That is, the applied pressure of 10 MPa indicates that the pressure applied to the laminate 2 is 10 MPa greater than the atmospheric pressure.
When the laminated body 2 is heated and pressurized, a fluid heated from the pipe 611 may be introduced and the laminated body 2 may be heated and pressurized, or the fluid is allowed to flow into the container 61 from the pipe 611 under a pressurized atmosphere. In addition, the stacked body 2 can be heated by heating the container 61.

The laminated body 2 is disposed in the container 61, a fluid is introduced, and the laminated body 2 is heated to a temperature equal to or higher than the curing temperature of the thermosetting resin of the resin layers 11, 13, and 15 to cure the resin layers 11, 13, and 15. To do. The glass transition point Tg ₁₁ (° C.) of the resin layer 11 of the laminate 2, the glass transition point Tg ₁₃ (° C.) of the resin layer 13, and the glass transition point Tg ₁₅ (° C.) of _the resin layer 15 immediately after this thermosetting step are obtained. The resin layers 11, 13, and 15 of the laminate 2 are thermally cured at a heat curing temperature Tc that exceeds the temperature.
Tg ₁₁ , Tg _{13, and} Tg ₁₅ preferably satisfy Tc−Tg ≧ 5 ° C. (Equation (1)), respectively. In the mathematical formula (1), Tg is any one of Tg ₁₁ , Tg _{13, and} Tg ₁₅ . By doing in this way, the effect that the resin layer can be C-staged (completely cured) can be produced.
Especially, it is preferable that Tc-Tg is 15 degreeC or more. Moreover, it is preferable that Tc-Tg is 100 degrees C or less from a viewpoint of the heat-shrinkage suppression after hardening.
For example, when Tg ₁₁ , Tg _{13 and} Tg ₁₅ are 100 ° C. to 160 ° C., Tc is set to 115 ° C. to 260 ° C. _{Incidentally, Tg 11, Tg 13, Tg} 15 is, 80 ° C. or higher, more preferably 180 ° C. or less.

The laminated body 2 is heated at the temperature Tc, for example, for 1 hour. While the laminated body 2 is heated at the temperature Tc, it is pressurized by the fluid.
Thereafter, the fluid is discharged from the container 61. The pressurization to the laminated body 2 by the fluid is stopped, and then the laminated body 2 is taken out from the container 61. Thereby, the laminated body 2 from which the pressurization by the fluid is released is cooled to the room temperature through the glass transition temperature of each resin layer from Tc.

Here, α _2-11 (ppm / ° C.) is the average linear expansion coefficient of the glass transition point (Tg ₁₁ ) or more and 280 ° C. or less of the resin layer 11 of the laminate 2 immediately after the thermosetting step, and the glass transition point Tg ₁₁ Let the elastic modulus be E ′ ₁₁ (Pa).
Similarly, the average linear expansion coefficient of the glass transition point (Tg ₁₃ ) or more and 280 ° C. or less of the resin layer 13 of the laminate 2 immediately after the thermosetting step is α _2-13 (ppm / ° C.), and the glass transition point Tg ₁₃ Let the elastic modulus be E ′ ₁₃ (Pa).
Further, similarly, the average linear expansion coefficient of the glass transition point _{(Tg 15)} over 280 ° C. or less of the resin layer 15 of the laminate 2 just after the heat curing step the α _2-15 (ppm / ℃), a glass transition temperature Tg The elastic modulus at ₁₅ is defined as E ′ ₁₅ (Pa).
And in each resin layer 11, 13, 15,
E ′ (Pa) × α ₂ (ppm / ° C.) × (Tc−Tg) (° C.) ≦ 2.7 × 10 ⁷ (Pa) (Formula (2))
The resin of each resin layer 11, 13, 15 is selected so as to satisfy the condition, and Tc is set.
Here, in the case of E ′ = E ′ ₁₁ , Tg = Tg ₁₁ and α ₂ = α _2-11 . In the case of E '= E' ₁₃ is, Tg = _{Tg 13,} an α ₂ = α _2-13. Furthermore, in the case of E '= E' ₁₅ is, Tg = _{Tg 15,} an α ₂ = α _2-15.

E ′ × α ₂ × (Tc−Tg) may be 2.7 × 10 ⁷ Pa or less, and more preferably 2.5 × 10 ⁷ Pa or less.
Further, E ′ × α ₂ × (Tc−Tg) is preferably 5.0 × 10 ⁵ Pa or more. In particular, E ′ × α ₂ × (Tc−Tg) is preferably 5.0 × 10 ⁶ Pa or more.
By setting E ′ × α ₂ × (Tc−Tg) to be equal to or higher than the lower limit, the adhesion between the electronic component and the semiconductor element via the resin layer or the semiconductor element via the resin layer is improved. Can do.
α ₂ , that is, α _2-11 , α _2-13 , and α _2-15 are all preferably 30 ppm / ° C. or more, and particularly preferably 80 ppm / ° C. or more. Moreover, it is preferable that it is 300 ppm / degrees C or less, and it is especially preferable that it is 250 ppm / degrees C or less especially.
resin layer alpha ₂ is not less than the lower limit, since it has a sufficient fluidity at the time of solder bonding, it is possible to suppress the generation of unfilled portions of the inner resin layer due to the flow resistance decreases.
On the other hand, the stress which generate | occur | produces in a resin layer can be suppressed because (alpha) ₂ shall be below the said upper limit.
Furthermore, E ′, that is, E ′ ₁₁ , E ′ ₁₃ , and E ′ ₁₅ are all preferably 1.0 × 10 ⁸ Pa or more, and more preferably 8.0 × 10 ⁸ Pa or more. It is particularly preferred. Also, preferably not more than 1.0 × ¹⁰ 10 Pa, among them, particularly preferably not more than 5.0 × ¹⁰ 9 Pa.
By setting E ′ to be equal to or more than the above lower limit value, the joined terminals can be protected by the resin layer. On the other hand, the stress which generate | occur | produces in a resin layer can be suppressed by making E 'below into the said upper limit.

  Note that the resin layers 11, 13, and 15 may be cured by putting a plurality of laminates 2 in the container 61 of the apparatus 6. In this way, productivity can be improved.

As described above, the stacked body 2 is obtained in which the semiconductor chips 10 and 12, the semiconductor chips 12 and 14, and the semiconductor chips 14 and 16 are solder-bonded (FIGS. 1D and 3A).
Here, an average linear expansion coefficient of 25 ° C. or more and a glass transition point (Tg ₁₁ ) or less of the resin layer 11 of the laminate 2 immediately after the thermosetting step is _defined as α _1-11 (ppm / ° C.).
Similarly, an average linear expansion coefficient of 25 ° C. or more and a glass transition point (Tg ₁₃ ) or less of the resin layer 13 of the laminate 2 immediately after the thermosetting step is _defined as α _1-13 (ppm / ° C.).
Furthermore, _let α _1-15 (ppm / ° C.) be an average linear expansion coefficient of 25 ° C. or more and a glass transition point (Tg ₁₅ ) or less of the resin layer 15 of the laminate 2 immediately after the thermosetting step.
And when it is set as the average linear expansion coefficient α _1-s (ppm / ° C.) at 25 ° C. or more and 300 ° C. or less of the semiconductor element,
α ₁ −α _1−s ≦ 80 (ppm / ° C.) (Formula (3)) is preferable.

Here, α ₁ is any one of α _1-11 , α _{1-13, and} α _1-15 , and α _1-s is any semiconductor chip in contact with the resin layer of α _1-1 .
For example, when α ₁ is α _1-11 , α _1-s is an average linear expansion coefficient of the semiconductor chip 10 or the semiconductor chip 12 directly on the resin layer 11. In addition, when α ₁ is α _1-13 , α _1-s is an average linear expansion coefficient of the semiconductor chip 12 or the semiconductor chip 14 directly on the resin layer 13. In addition, when α ₁ is α _1-15 , α _1-s is an average linear expansion coefficient of the semiconductor chip 14 or the semiconductor chip 16 directly on the resin layer 15. In addition, it is preferable that each resin layer satisfy | fills said Numerical formula (3) in the relationship with all the adjacent semiconductor chips.

By doing in this way, the average linear expansion coefficient difference between a semiconductor chip and each resin layer becomes small, and generation | occurrence | production of the crack of a semiconductor chip can be suppressed.
Especially, it is preferable that (alpha) _{1- (} alpha) _1-s is 70 ppm / degrees C or less, especially 50 ppm / degrees C or less. In addition, the lower limit value of α ₁ -α _1-s is not particularly limited, but is 15 ppm / ° C. from the viewpoint of the upper limit value of the inorganic filler compounded in order to reduce the linear expansion coefficient of the resin layer. It is preferable.
Α ₁ is preferably 20 ppm / ° C. or higher. Moreover, it is preferable that it is 75 ppm / degrees C or less, and it is especially preferable that it is 55 ppm / degrees C or less, Furthermore, it is 50 ppm / degrees C or less.

Here, the measuring methods of E ′ (Pa), α ₂ (ppm / ° C.), Tg (° C.), α ₁ (ppm / ° C.) _, α _1-s (ppm / ° C.) are as follows.
Using TMA, a tensile load of 3 g is applied to the resin layer after the thermosetting step, and the glass transition point Tg is measured at a temperature increase rate of 10 ° C./min and in a temperature range of −100 ° C. to 300 ° C. .
Moreover, linear expansion coefficient (alpha) ₁ below 25 degreeC and a glass transition temperature is acquired by the same measurement. Further, the glass transition temperature or higher by the same measurement to obtain a coefficient of linear expansion alpha ₂ of 280 ° C. or less.
Α _1-s which is the linear expansion coefficient of the semiconductor chip can also be measured by the same measuring method.
Further, the elastic modulus can be measured at a measurement temperature Tg using a dynamic viscoelasticity measuring device with a tensile mode, a frequency of 10 Hz, and a temperature rising rate of 5 ° C./min.

(Joining process)
Next, as shown in FIG. 3A, the stacked body 2 is turned upside down, and as shown in FIG. 3B, the semiconductor chips 10, 12, the semiconductor chips 12, 14, the semiconductor chips 14, The laminate 2 in which the 16 members are soldered together is placed on the base material 18, and the laminate 2 and the base material 18 are soldered together.
First, the base material 18 is prepared. Here, the base material 18 may be a resin substrate, or may be a silicon substrate, a glass substrate, a ceramic substrate, or the like.

Terminals (laminated body connection terminals) 181 are formed on the surface of the base material 18. The terminal 181 is made of the same structure and material as the terminal 101, and has a solder layer 181A on the surface. The terminal 181 is connected to the semiconductor chip 16. Although not shown on the back surface of the substrate 18, for example, terminals and the like are formed, and are electrically connected to the terminals 181 provided on the front surface (surface on the semiconductor chip 16 side).
Next, the resin layer 17 is provided on the surface of the substrate 18. The resin layer 17 is provided so as to cover the terminal 181. The resin layer 17 may be the same as the resin layers 11, 13, and 15. For example, a paste-like no-flow type underfill material (NUF) may be used. In order to provide the resin layer 17 on a part of the surface of the substrate 18, it is preferable to apply a paste-like underfill material by dispensing or ink jet.

Examples of such a no-flow type underfill material include those disclosed in Japanese Patent Application Laid-Open No. 2008-13710, and the first epoxy resin that is liquid at room temperature and the curing temperature higher than that of the first epoxy resin. The resin composition includes a two-epoxy resin, a silicone-modified epoxy resin, an inorganic filler, and a curing agent having flux activity. This resin composition does not contain a solvent.
As the first epoxy resin, for example, bisphenol type epoxy resins such as bisphenol A type epoxy resin and bisphenol F type epoxy resin are preferable.
As the second epoxy resin, an epoxy resin having an allyl group (for example, diallyl bisphenol A type epoxy resin) is preferable.
The first epoxy resin is preferably 5 to 50% by mass in the resin composition, and the second epoxy resin is preferably 0.1 to 40% by mass.
Examples of the silicone-modified epoxy resin include silicone-modified (liquid) epoxy resins having a disiloxane structure, and specifically include silicone-modified epoxy resins represented by the following general formula (1).

  The silicone modification rate of the silicone-modified epoxy resin is not particularly limited, but m of the silicone-modified resin is preferably 5 or less, and particularly preferably m is 1 or less.

  More specifically, the silicone-modified epoxy resin includes a silicone-modified liquid epoxy resin in which m of the silicone-modified liquid epoxy resin represented by the general formula (1) is 0, and a phenol represented by the following general formula (2). It is preferable that these are synthesized by heating reaction. Thereby, the wettability to a base material or a semiconductor chip can be improved.

The molar ratio of the silicone-modified liquid epoxy resin represented by the general formula (1) in which m is 0 and the phenols represented by the general formula (2) (epoxy of the silicone-modified epoxy resin) The group / phenolic hydroxyl group of the phenols is not particularly limited, but is preferably 1 to 10, and particularly preferably 1 to 5. When the molar ratio is within the above range, the yield of the reaction product and low volatility are particularly excellent.
The content of the silicone-modified epoxy resin is preferably 0.1 to 20% by mass based on the entire resin composition.

Furthermore, the hardening agent which has flux activity can also use 2 or more types from which melting | fusing point differs.
For example, as the first flux active curing agent, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, 2,5-dihydroxybenzoic acid, 2,6-dihydroxybenzoic acid, 3,4-dihydroxybenzoic acid are used. Acid is preferred.
As the second flux active curing agent, o-phthalic acid, trimellitic acid, hexahydrophthalic acid, methylhexahydrophthalic acid, 4-hydroxy (o-phthalic acid), 3-hydroxy (o-phthalic acid) ), Tetrahydrophthalic acid, maleic acid, those containing alkylene groups include succinic acid, malonic acid, glutaric acid, malic acid, sebacic acid, adipic acid, azelaic acid, suberic acid, pimelic acid, 1,9-nonanedicarboxylic acid And dodecanedioic acid. These may be used alone or in combination. Among these, sebacic acid is preferable.

After providing the resin layer 17 on the substrate 18, the laminate 2 is mounted on the resin layer 17. The laminate 2 is placed on the resin layer 17 so that the terminals 162 of the laminate 2 are located on the resin layer 17 side.
Thereafter, the laminate 2, the resin layer 17, and the substrate 18 are clamped in the laminating direction by the pair of clamping members 41 and 42, and the laminate 2, the resin layer 17, and the substrate 18 are brought to the melting point of the solder layer 181A or more. Heat to. At this time, the laminated body 2, the resin layer 17, and the base material 18 are clamped by the pair of clamping members 41 and 42, and the pair of clamping members 41 and 42 are heated, whereby the laminate 2 and the resin layer 17 are heated. The base material 18 is heated to the melting point or higher of the solder layer 181A. Thereby, the terminal 181 and the terminal 162 are soldered together. In this joining step, for example, a flip chip bonder is used, and the laminate 2 is soldered to the base material 18 one by one.
In this way, the plurality of laminated bodies 2 are installed on the base material 18, and the base material 18 and the plurality of laminated bodies 2 are soldered to obtain the structure 3 (see FIG. 3C).

Thereafter, the resin layer 17 of the structure 3 is cured as necessary. Here, the resin layer 17 is cured using the apparatus 6 shown in FIG. The curing method is the same as the method described above, and the structure 3 is heated to a temperature equal to or higher than the curing temperature of the thermosetting resin of the resin layer 17 while pressing the structure 3 with a fluid to cure the resin layer 17. Do.
By doing in this way, generation | occurrence | production of the void in the resin layer 17 can be prevented, and the generated void can be eliminated.

(Sealing process)
Next, the structure 3 is sealed. The sealing method may be potting, transfer molding, or compression molding.
After that, each of the stacked bodies 2 can be cut to obtain a plurality of semiconductor devices 1 shown in FIG. In FIG. 3D, reference numeral 19 denotes a sealing material, and reference numeral 18A denotes a diced base material 18. Further, when the semiconductor device 1 has a plurality of stacked bodies 2, the semiconductor device 1 may be cut for each unit of the semiconductor device 1. In addition, a dicing blade, a laser, a router, etc. can be used for a cutting | disconnection.

According to the present embodiment as described above, the following effects can be obtained.
In this embodiment, in the manufacturing process of the semiconductor device, in the thermosetting process, which is the process of making the curing of the resin layers 11, 13, 15 of the laminate 2 the most,
E ′ × α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa) (Formula (2))
Thermosetting is performed under conditions that satisfy the above conditions.
Thereby, the internal stress which exists in each resin layer 11, 13, 15 after a thermosetting process can be reduced, and it can prevent that a crack generate | occur | produces in a semiconductor chip resulting from the internal stress of a resin layer. Therefore, a semiconductor device can be manufactured with high productivity.
In addition, when a plurality of resin layers are stacked and thermoset as in this embodiment, the stress generated in the range of the thermoset temperature to the glass transition point, which has not been recognized at all, is greatly increased in the semiconductor chip. It was found that cracking was affected, and it was found that it is extremely important to perform thermosetting under the condition satisfying the above formula (2).
Further, when the semiconductor chip has a TSV structure as in this embodiment, the thickness of the semiconductor substrate is very thin. Therefore, it is possible to perform thermosetting under the condition satisfying the above formula (2). This is effective for preventing cracks in the chip.

Moreover, in this embodiment, when hardening the resin layers 11, 13, and 15, the laminated body 2 is pressurized from the circumference by the fluid. Therefore, by pressurizing the laminate 2 with a fluid, the resin layer is thermally cured in a strained state, and thus internal stress may remain in the resin layer due to the pressurization with the fluid. In addition, the internal stress remaining in the resin layer includes an internal stress generated due to thermal shrinkage when cooling from Tc to Tg.
Therefore, when the manufacturing method as in this embodiment is used, generation of voids can be reduced by pressurizing the laminate 2 with a fluid, but a relatively large internal stress may remain in the resin layer. There is.
Therefore, the resin layer is cured while pressurizing the laminate 2 with a fluid, while thermosetting is performed under a condition satisfying E ′ × α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa). This makes it possible to reduce the internal stress of the resin layer while reducing the generation of voids. As a result, it is possible to provide a semiconductor device in which cracks are unlikely to occur in the semiconductor chip and voids can be reduced and connection reliability is high.

  In the present embodiment, the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, the semiconductor chip 14, the resin layer 15, and the semiconductor chip 16 are stacked in this order, and the entire stacked body 2 is heated and soldered. Since bonding is performed, thermal damage to the semiconductor chips 10, 12, 14, and 16 can be reduced as compared with the case where the semiconductor chips are sequentially soldered together. Therefore, the reliability of the semiconductor device 1 can be improved.

Further, after the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, the semiconductor chip 14, the resin layer 15, and the semiconductor chip 16 are stacked in this order to obtain the stacked body 2, the entire stacked body 2 is heated. Thus, the solder bonding between the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 is simultaneously performed. Therefore, productivity at the time of soldering can be improved as compared with the case where a plurality of semiconductor components are stacked while sequentially performing soldering for each semiconductor component.
In other words, after the step of forming the laminated body from the semiconductor chip and the resin layer, the step of soldering the semiconductor chips to each other can be performed at a time, so that the semiconductor device has three or more semiconductor chips. If it exists, a semiconductor device can be manufactured more efficiently.
In the present embodiment, when the laminated body 2 is obtained, heating is performed every time a semiconductor chip with a resin layer is stacked on the semiconductor chip 10. The heating at this time is performed between the semiconductor chips by the resin layer. It is heating for bonding. Therefore, since the heating time is relatively short and the heating temperature is low, productivity can be improved even when the step of obtaining the laminate 2 is performed as compared with the conventional manufacturing method.

Furthermore, in this embodiment, the laminate 2 is sandwiched and soldered.
Conventionally, each time a semiconductor chip is stacked, it is clamped and soldered, so the underlying semiconductor chip is clamped multiple times and is easily damaged.
On the other hand, in the present embodiment, the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, the semiconductor chip 14, the resin layer 15, and the semiconductor chip 16 are stacked in this order to obtain the stacked body 2. Then, the laminate 2 is clamped and soldered. It is prevented that the semiconductor chip is clamped a plurality of times during solder bonding, and damage to the semiconductor chips 10, 12, 14, and 16 is reduced.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, in the embodiment, the semiconductor chip 10 has the same size as other semiconductor chips, but is not limited thereto. For example, as shown in FIG. 4, a structure comprising a resin layer 11, a semiconductor chip 12, a resin layer 13, a semiconductor chip 14, a resin layer 15, and a semiconductor chip 16 on a semiconductor wafer 10A in which a plurality of semiconductor chips 10 are formed. A plurality of bodies may be arranged and heated in this state to perform solder bonding between the terminals 101, 121, the terminals 122, 141, and the terminals 142, 161. Thereafter, the same thermosetting process as in the above embodiment may be performed, and then the semiconductor wafer may be cut.

  Furthermore, in each said embodiment, although the semiconductor chip 10 shall not have a TSV structure, it is not restricted to this, It is good also as a semiconductor chip of a TSV structure.

Moreover, in each said embodiment, although the semiconductor device 1 which has four semiconductor chips was manufactured, it is not restricted to this.
Further, in each of the embodiments, the terminals 121, 141, 161, and 181 have the solder layers 121A, 141A, 161A, and 181A. However, the present invention is not limited to this, and the terminals 122, 142, and 162 have solder layers on the surface. You may have. Further, all of the terminals 101, 121, 141, 161, 181 and the terminals 122, 142, 162 may have a solder layer on the surface. These solder layers may be melted to perform solder bonding between the semiconductor chips 10, 12, 14, 16, and further between the multilayer body 2 and the substrate 18.
Furthermore, in the said embodiment, although the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 were soldered simultaneously, it is not restricted to this.
For example, after the semiconductor chip 12 is laminated on the semiconductor chip 10 via the resin layer 11, the terminals 101 and 121 are soldered together. Thereafter, the resin layer 13 and the semiconductor chip 14 are disposed on the semiconductor chip 12, and the terminals 122 and 141 are soldered together. Further, the resin layer 15 and the semiconductor chip 16 are stacked on the semiconductor chip 14 and the terminals 142 and 161 are soldered together. In this way, the terminals may be soldered sequentially.
In other words, the embodiment of the present invention includes a step of soldering the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 to form the stacked body 2. 121 a step of bringing 121 into contact with each other, a step of bringing terminals 122 and 141 into contact with each other, a step of soldering, and a step of bringing terminals 142 and 161 into contact with each other and a step of soldering together. It may be a step of performing these steps in order.

  Next, examples of the present invention will be described.

Example 1
A semiconductor device was manufactured by the same method as in the previous embodiment.
(Production of resin layer)
A resin layer was prepared.
A resin layer having the composition shown in Table 1 was prepared.
Specifically, it is as follows.
5.1 parts by mass of cresol novolac resin (manufactured by DIC Corporation (trade name “KA-1160”)), 5.1 parts by mass of phenol aralkyl resin (trade name “Millex XLC-4L” by Mitsui Chemicals), 14.19 parts by mass of bisphenol F type epoxy resin (manufactured by DIC Corporation (trade name “EXA-830LVP”)), 14.19 parts by weight, bisphenol A type epoxy resin (manufactured by DIC Corporation (trade name “EPICLON-840”)) Part, 7.5 parts by mass of trimellitic acid (Tokyo Chemical Industry Co., Ltd.) which is a flux active compound, 3.63 parts by mass of phenoxy resin (Mitsubishi Chemical Co., Ltd. (trade name “YX-6654”)), curing acceleration 2-phenyl-4-methylimidazole (manufactured by Shikoku Kasei Kogyo Co., Ltd., (trade name “2P4MZ”)) 0.06 mass Part, 3-glycidoxypropyltrimethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd. (trade name “KBM-403”)) which is a silane coupling agent, silica filler (manufactured by Admatex Co., Ltd. (product) Name “SC1050”)) 50 parts by mass was dissolved in methyl ethyl ketone (inorganic filler was mixed) to prepare a resin varnish having a solid content concentration of 50% by mass. The obtained resin varnish was applied to a base polyester film (Purex A53, manufactured by Teijin DuPont Films Co., Ltd.) to a thickness of 50 μm, and then dried at 100 ° C. for 5 minutes to obtain a flux activity of 25 μm thickness. A resin layer having was obtained.
The average particle size of the silica filler was 0.25 μm. This average particle size was measured by dispersing the silica filler in water by ultrasonic treatment for 1 minute and measuring with a particle size distribution meter (manufactured by Shimadzu Corporation, product name: Laser diffraction particle size distribution analyzer SALD series) (D50). Is.

(Process for preparing a laminate)
Semiconductor chips 10, 12, 14, and 16 were prepared. The resin layer (herein referred to as “resin layer 11”) prepared in the above-mentioned section (Preparation of resin layer) was laminated so as to cover the terminals 121 of the semiconductor chip 12.
Similarly, the above-described resin layer (here, referred to as resin layer 13) was laminated so as to cover the terminal 141 of the semiconductor chip 14.
Further, the above-described resin layer (herein referred to as the resin layer 15) was laminated so as to cover the terminals 161 of the semiconductor chip 16.
Lamination was performed at a temperature of 95 ° C. and a pressure of 0.8 MPa for 30 seconds.
Thereafter, the surface of the semiconductor chip 10 on which the terminals 101 are formed and the resin layer 11 provided on the semiconductor chip 12 face each other, and the semiconductor chip 12 is stacked on the semiconductor chip 10 with the resin layer 11 interposed therebetween. At this time, using a flip chip bonder, the semiconductor chip 10 and the semiconductor chip 12 were bonded via the resin layer 11 in a semi-cured state (B stage) under atmospheric pressure and in the air. This adhesion was performed at 100 ° C. for the lower stage, 150 ° C. for the bonding tool, 0.1 MPa for pressure, and 2 seconds. Adhesion between semiconductor chips to be described later is also the same condition.
Next, the surface of the semiconductor chip 12 on which the terminals 122 are formed and the resin layer 13 provided on the semiconductor chip 14 face each other, and the semiconductor chip 14 is stacked on the semiconductor chip 12 via the resin layer 13. . At this time, using a flip chip bonder, the semiconductor chip 12 and the semiconductor chip 14 were bonded via the resin layer 13 in a semi-cured state (B stage) in the atmosphere at atmospheric pressure.
In the above process, the solder layer was not melted. In addition, a resin layer is interposed between the terminals.
Next, as shown in FIG. 1C, the semiconductor chip 16 with the resin layer 15 was attached to the pinching member 43. On the other hand, the pinching member 44 was set to 100 ° C., and a laminate composed of the semiconductor chip 10, the resin layer 11, the semiconductor chip 12, the resin layer 13, and the semiconductor chip 14 was installed.
Then, the laminated body is pressurized under the condition of a load of 0.5 MPa / 12 sec with the clamping member 43 heated to 150 ° C., then the temperature of the clamping member 43 is rapidly increased, and the temperature of the clamping member 43 is increased to 280 ° C. The terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 were soldered together by setting and pressurizing with a load of 0.5 MPa / 12 sec.
The semiconductor chip 10 had a thickness of 200 μm, and the semiconductor chips 12, 14, 16 all had a thickness of 50 μm.

(Thermosetting process)
The resin layers 11, 13, and 15 of the laminate 2 in which the terminals 101 and 121, the terminals 122 and 141, and the terminals 142 and 161 are solder-bonded were cured. Using a pressurizing / heating device (manufactured by Kyoshin Engineering Co., Ltd., model number: HPV-5050MAH-D), it was cured by pressure.
The laminate 2 was put in a container 61 of a heating / pressurizing device, and heating was started from room temperature and was pressurized with a pressurized fluid. The pressure applied by the pressurized fluid was 0.8 MPa. The laminate 2 was heated at 180 ° C. for 2 hours with the above pressure. Thereafter, pressurization with the pressurized fluid was released, and the laminate 2 was allowed to cool from 180 ° C. to 25 ° C.
Thereafter, the laminate 2 was taken out from the container 61.
When the average linear expansion coefficient of the glass transition point (Tg) and 280 ° C. or less of each resin layer after thermosetting is α ₂ and the elastic modulus at the glass transition point Tg is E ′,
E ′ (Pa) × α ₂ (ppm / ° C.) × (Tc−Tg) (° C.) = 2.5 × 10 ⁷ (Pa).
Tables 2 and 3 show the measurement results of the elastic modulus (E ′) and glass transition temperature (Tg) average linear expansion coefficients α ₂ and α ₁ of the resin layer.
Thereafter, similarly to the embodiment, the laminate 2 was soldered to the base material 18 that is a silicon substrate.

(Example 2)
(Production of resin layer)
A resin layer was prepared.
A resin layer having the composition shown in Table 1 was prepared.
Specifically, it is as follows.
Phenol aralkyl resin (Mitsui Chemicals Co., Ltd. (trade name “Mirex XLC-4L”)) 5.1 parts by mass, phenol novolac resin (Sumitomo Bakelite Co., Ltd. (trade name “PR-55617”)) 5.1 parts by mass 14.19 parts by mass of bisphenol F type epoxy resin (manufactured by DIC Corporation (trade name “EXA-830LVP”)), bisphenol A type epoxy resin (manufactured by DIC Corporation, (trade name “EPICLON-840”)) 19 parts by weight, 7.5 parts by weight of trimellitic acid (manufactured by Tokyo Chemical Industry Co., Ltd.) which is a flux active compound, acrylic acid ester copolymer (manufactured by Nagase ChemteX Corporation (trade name “SG-P3”)) 3 .63 parts by mass, 2-methylimidazole (manufactured by Shikoku Kasei Co., Ltd. (trade name “2MZ-H”)) as a curing accelerator .06 parts by mass, silane coupling agent 3-methacryloxypropyltriethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd. (trade name “KBE-503”)), 0.25 parts by mass, silica filler (manufactured by Admatex Co., Ltd.) (Product name “SC1050”)) 50 parts by mass was dissolved in methyl ethyl ketone (mixed with inorganic filler) to prepare a resin varnish having a solid content concentration of 50% by mass. The obtained resin varnish was applied to a base polyester film (Purex A53, manufactured by Teijin DuPont Films Co., Ltd.) to a thickness of 50 μm, and then dried at 100 ° C. for 5 minutes to obtain a flux activity of 25 μm thickness. A resin layer having was obtained.
This resin layer is the same as that of Example 1 except that the resin layers 11, 13, and 15 are used, the curing temperature is 150 ° C., and the curing time is 5 hours.

(Comparative Example 1)
(Production of resin layer)
A resin layer was prepared.
A resin layer having the composition shown in Table 1 was prepared.
Specifically, it is as follows.
Cresol novolac resin (DIC Corporation (trade name “KA-1160”) 20.38 parts by mass, bisphenol F type epoxy resin (DIC Corporation (trade name “EXA-830LVP”)) 28.38 parts by mass, bisphenol A Type epoxy resin (manufactured by DIC Corporation (trade name “EPICLON-840”)) 28.38 parts by weight, flux active compound trimellitic acid (manufactured by Tokyo Chemical Industry Co., Ltd.) 15 parts by mass, phenoxy resin (Mitsubishi Chemical Corporation) 7.25 parts by mass (trade name “YX-6594”) manufactured by the company, 2-phenyl-4-methylimidazole (manufactured by Shikoku Kasei Kogyo Co., Ltd., (trade name “2P4MZ”)) 0.13 mass 3-glycidoxypropyltrimethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd. (product) "KBM-403")) was dissolved in 0.5 parts by weight of methyl ethyl ketone to prepare a solid concentration of 50 wt% of the resin varnish. The obtained resin varnish was applied to a base polyester film (Purex A53, manufactured by Teijin DuPont Films Co., Ltd.) to a thickness of 50 μm, and then dried at 100 ° C. for 5 minutes to obtain a flux activity of 25 μm thickness. A resin layer having was obtained.
This resin layer is the same as that of Example 1 except that the resin layers 11, 13, and 15 are used, the curing temperature is 230 ° C., and the curing time is 1 hour.

(Comparative Example 2)
(Production of resin layer)
A resin layer was prepared.
A resin layer having the composition shown in Table 1 was prepared.
Specifically, it is as follows.
7.64 parts by mass of phenol aralkyl resin (Mitsui Chemicals Co., Ltd. (trade name “Mirex XLC-4L”)), phenol novolac resin (manufactured by Sumitomo Bakelite Co., Ltd. (trade name “PR-55617”)) 7.64 parts by mass 21.28 parts by mass of bisphenol F type epoxy resin (manufactured by DIC Corporation (trade name “EXA-830LVP”)), bisphenol A type epoxy resin (manufactured by DIC Corporation, (trade name “EPICLON-840”)) 28 parts by weight, 11.25 parts by weight of trimellitic acid (produced by Tokyo Chemical Industry Co., Ltd.) which is a flux active compound, acrylic ester copolymer (produced by Nagase ChemteX Corporation (trade name “SG-P3”)) 5 .44 mass parts, 2-methylimidazole (product name “2MZ- )) 0.09 parts by mass, 3-methacryloxypropyltriethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd. (trade name “KBE-503”)) which is a silane coupling agent, 0.38 parts by mass, silica filler (stock) 25 parts by mass (manufactured by Admatechs (trade name “SC1050”)) was dissolved in methyl ethyl ketone (inorganic filler was mixed) to prepare a resin varnish having a solid concentration of 50% by mass. The obtained resin varnish was applied to a base polyester film (Purex A53, manufactured by Teijin DuPont Films Co., Ltd.) to a thickness of 50 μm, and then dried at 100 ° C. for 5 minutes to obtain a flux activity of 25 μm thickness. A resin layer having was obtained.
This resin layer is the same as that of Example 1 except that the resin layers 11, 13, and 15 are used, the curing temperature is 230 ° C., and the curing time is 1 hour.

(Comparative Example 3)
The same resin layer as in Example 1 is used for the resin layers 11, 13, and 15, except that the curing temperature is 230 ° C. and the curing time is 1 hour.

(Measurement)
(Glass transition temperature (Tg) average linear expansion coefficient α ₂ , α _{1 of} resin layer)
In each example and each comparative example, the produced resin layer was cured at 180 ° C. for 2 hours. Then, it cut and obtained the test piece of 20 mm x 3 mm x 0.025 mm. This test piece was measured using a TMA / SS120 manufactured by Seiko Instruments Inc. under a compression load of 3 g and a temperature range of −100 ° C. to 300 ° C. under conditions of a temperature increase rate of 10 ° C./min to obtain a glass transition point Tg. .
Moreover, average linear expansion coefficient (alpha) ₁ in the range below 25 degreeC and a glass transition temperature was acquired by the same measurement. Furthermore, average linear expansion coefficient (alpha) ₂ in the range more than glass transition temperature and 280 degrees C or less was acquired by the same measurement.

(Average linear expansion coefficient of semiconductor chip)
Α _1-s, which is an average linear expansion coefficient of the semiconductor chip, was measured by the following method.
The wafer was cut to obtain a test piece of 20 mm × 3 mm × 0.05 mm. This test piece was measured using a Seiko TMA / SS120 with a compression load of 3 g and a temperature range of −100 ° C. to 300 ° C. under a temperature increase rate of 10 ° C./min, and an average in a range of 25 ° C. or more and 300 ° C. or less. A linear expansion coefficient α _1-s was obtained.

(Elastic modulus E ′ of the resin layer)
In each example and each comparative example, the produced resin layer was cured at 180 ° C. for 2 hours. Then, it cut and obtained the test piece of 20 mm x 5 mm x 0.025 mm. Using this test piece, the storage elastic modulus was measured at a measurement temperature Tg, using a dynamic viscoelasticity measuring device, in a tensile mode, a frequency of 10 Hz, and a heating rate of 5 ° C./min.

(result)
The semiconductor chip of the laminated body 2 of the semiconductor device obtained in each example and each comparative example was observed with an optical microscope (200 times).
In Examples 1 and 2, no crack was generated in the semiconductor chip of the stacked body 2 of the semiconductor device.
On the other hand, in Comparative Example 1-3, after manufacturing a laminated body, it turned out that the crack has arisen in the semiconductor chip.
Hereinafter, examples of the reference form will be added.
[1]
A method of manufacturing a semiconductor device in which an electronic component, a thermosetting first resin layer, a first semiconductor element, a thermosetting second resin layer, and a second semiconductor element are laminated in this order,
The connection terminal of the first semiconductor element and the connection terminal of the electronic component are brought into contact with each other, and the periphery of the connection terminal in contact with each other is surrounded between the first semiconductor element and the electronic component. The first resin layer is disposed on the
While contacting the other connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element,
A step of configuring a laminate by disposing a second resin layer surrounding the other connection terminals and the connection terminals that are in contact with each other between the first semiconductor element and the second semiconductor element; and
Heating the laminate, and thermosetting the first resin layer and the second resin layer,
In the step of heating the laminate and thermosetting the first resin layer and the second resin layer,
The thermosetting temperature Tc (° C.) exceeding the glass transition point Tg ₁ (° C.) of the first resin layer and the glass transition point Tg ₂ (° C.) of the second resin layer of the laminate after the thermosetting , After thermosetting the first resin layer and the second resin layer of the laminate, the glass transition point Tg ₁ (° C.) of the first resin layer and the glass of the second resin layer from the thermosetting temperature Tc (° C.). The first resin layer and the second resin layer are cooled to a temperature below the transition point Tg ₂ (° C.),
The average linear expansion coefficient of the Tg _{1 to} 280 ° C. of the first resin layer of the laminate after the thermosetting is α _2-1 (ppm / ° C.),
When the elastic modulus at the Tg ₁ of the first resin layer of the laminate after the thermosetting is E ′ ₁ (Pa),
E ′ ₁ × α _2-1 × (Tc-Tg ₁ ) ≦ 2.7 × 10 ⁷ (Pa)
And
The average linear expansion coefficient of Tg ₂ or more and 280 ° C. or less of the second resin layer of the laminate after the thermosetting is α _2-2 (ppm / ° C.),
When the elastic modulus at the Tg ₂ of the second resin layer of the laminate after the thermosetting is E ′ ₂ (Pa),
E ′ ₂ × α _2-2 × (Tc-Tg ₂ ) ≦ 2.7 × 10 ⁷ (Pa)
A method for manufacturing a semiconductor device.
[2]
In the manufacturing method of the semiconductor device according to 1,
Tc−Tg ₁ ≧ 5 ° C.
A method for manufacturing a semiconductor device in which Tc−Tg ₂ ≧ 5 ° C.
[3]
In the manufacturing method of the semiconductor device according to 1 or 2,
The method of manufacturing a semiconductor device, wherein the first semiconductor element is a semiconductor chip having a TSV (Through-Silicon Via) structure including a substrate and a through via that penetrates the substrate and is connected to the connection terminal.
[4]
In the method for manufacturing a semiconductor device according to any one of 1 to 3,
A solder layer is formed on at least one surface of the connection terminal of the first semiconductor element and the connection terminal of the electronic component,
The first resin layer contains a flux active compound,
A solder layer is formed on the surface of at least one of the other connection terminals of the first semiconductor element and the connection terminals of the second semiconductor element,
The second resin layer contains a flux active compound,
In the step of constructing the laminate,
The film-like first resin layer is provided on at least one of the facing surface of the first semiconductor element facing the electronic component and the facing surface of the electronic component facing the first semiconductor element,
The film-like second resin layer is provided on at least one of the facing surface of the first semiconductor element facing the second semiconductor element and the facing surface of the second semiconductor element facing the first semiconductor element,
Soldering the connection terminal of the first semiconductor element and the connection terminal of the electronic component,
A method for manufacturing a semiconductor device, wherein the other connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element are soldered to form the stacked body.
[5]
4. The method of manufacturing a semiconductor device according to 4,
The method for manufacturing a semiconductor device, wherein the first resin layer and the second resin layer contain 20% by mass or more and 80% by mass or less of an inorganic filler having an average particle size of 0.5 μm or less.
[6]
In the method of manufacturing a semiconductor device according to 4 or 5,
In the step of constructing the laminate,
The first resin layer is interposed between the connection terminal of the first semiconductor element and the connection terminal of the electronic component,
The second resin layer is interposed between the connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element,
By sandwiching the first semiconductor element, the first resin layer, and the electronic component, the first resin layer between the connection terminals is eliminated, and the connection terminals are soldered together.
By sandwiching the first semiconductor element, the second resin layer, and the second semiconductor element, the second resin layer between the other connection terminal and the connection terminal of the second semiconductor element is eliminated. A method for manufacturing a semiconductor device, wherein the other connection terminal and the connection terminal are soldered.
[7]
In the method for manufacturing a semiconductor device according to any one of 4 to 6,
The method for manufacturing a semiconductor device, wherein the first resin layer and the second resin layer include a flux active compound having a carboxyl group and / or a flux active compound having a phenolic hydroxyl group.
[8]
In the method for manufacturing a semiconductor device according to any one of 1 to 7,
In the step of heating the laminate and thermosetting the first resin layer and the second resin layer,
A manufacturing method of a semiconductor device, wherein the first resin layer and the second resin layer are thermally cured by heating the laminate with a fluid while being pressurized.
[9]
In the method for manufacturing a semiconductor device according to any one of 1 to 8,
An average linear expansion coefficient α _1-1 (ppm / ° C.) of 25 ° C. or more and the glass transition point or less of the first resin layer of the laminated body after the thermosetting, and 25 ° C. or more of the first semiconductor element, 300 When the average linear expansion coefficient α _1-s (ppm / ° C.) at or below ℃,
α _1-1 -α _1-s ≦ 80 (ppm / ° C.),
When the average linear expansion coefficient α _1-2 (ppm / ° C.) is 25 ° C. or more and the glass transition point or less of the second resin layer of the laminate after the thermosetting ,
A method for manufacturing a semiconductor device, wherein α _1-2 -α _1-s ≦ 80 (ppm / ° C.).

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Laminated body 3 Structure 6 Device 10A Semiconductor wafer 10,12,14,16 Semiconductor chip 11,13,15 Resin layer 17 Resin layer 18 Base material 18A Base material 19 Sealing material 41, 42 Nipping member 44 43 Pinching member 61 Container 101 Terminals 120, 140, 160 Substrate 121A, 141A, 161A Solder layers 121, 141, 161 Terminals 122, 142, 162 Terminals 123, 143, 163 Via 181 Terminal 181A Solder layer 611 Piping

Claims (12)

  An adhesive film that bonds the first semiconductor element and the second semiconductor element that are connected to each other through the connection terminals,
  The first semiconductor element and the second semiconductor element are respectively
  A TSV structure semiconductor chip comprising a substrate and a through via that penetrates the substrate and is connected to the connection terminal;
  The adhesive film is
  A thermosetting resin;
  A flux active compound,
  The glass transition temperature of the adhesive film is Tg,
  The average linear expansion coefficient of the cured product of the adhesive film of Tg to 280 ° C. is α ₂ (Ppm / ° C)
  The elastic modulus at the Tg of the cured product of the adhesive film is E ′ (Pa),
  When Tc is a thermosetting temperature exceeding the Tg in the cured product,
  E '× α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa)
  E ′ is 1.0 × 10 ⁸ Pa or more 1.0 × 10 ¹⁰ Pa or less,
  Α ₂ Is 30 ppm / ° C. or more and 300 ppm / ° C. or less,
  The (Tc−Tg) is 5 ° C. or more and 100 ° C. or less,
  The adhesive film, wherein the Tg is 80 ° C or higher and 180 ° C or lower.   An electronic component, a thermosetting first resin layer, a TSV structure first semiconductor element, a thermosetting second resin layer, and a TSV structure second semiconductor element are laminated in this order, and the first semiconductor element In a semiconductor device comprising a laminate in which the second semiconductor element and the second semiconductor element are connected to each other via a connection terminal, an adhesive film used for the first resin layer and the second resin layer,
  A thermosetting resin;
  A flux active compound,
  The glass transition temperature of the adhesive film is Tg,
  The average linear expansion coefficient of the cured product of the adhesive film of Tg to 280 ° C. is α ₂ (Ppm / ° C)
  The elastic modulus at the Tg of the cured product of the adhesive film is E ′ (Pa),
  When Tc is a thermosetting temperature exceeding the Tg in the cured product,
  E '× α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa),
  E ′ is 1.0 × 10 ⁸ Pa or more 1.0 × 10 ¹⁰ Pa or less,
  Α ₂ Is 30 ppm / ° C. or more and 300 ppm / ° C. or less,
  The (Tc−Tg) is 5 ° C. or more and 100 ° C. or less,
  The adhesive film, wherein the Tg is 80 ° C. or higher and 180 ° C. or lower.   An electronic component, a thermosetting first resin layer, a TSV structure first semiconductor element, a thermosetting second resin layer, and a TSV structure second semiconductor element are laminated in this order, and the first semiconductor element And the second semiconductor element are used for the first adhesive film used for the first resin layer and the second resin layer in a semiconductor device including a laminate in which the second semiconductor elements are connected to each other via a connection terminal An adhesive film for a TSV structure comprising a second adhesive film,
  Each of the first adhesive film and the second adhesive film is
  A thermosetting resin;
  A flux active compound,
  The glass transition temperature of the adhesive film is Tg,
  The average linear expansion coefficient of the cured product of the adhesive film of Tg to 280 ° C. is α ₂ (Ppm / ° C)
  The elastic modulus at the Tg of the cured product of the adhesive film is E ′ (Pa),
  When Tc is a thermosetting temperature exceeding the Tg in the cured product,
  E '× α ₂ × (Tc−Tg) ≦ 2.7 × 10 ⁷ (Pa),
  E ′ is 1.0 × 10 ⁸ Pa or more 1.0 × 10 ¹⁰ Pa or less,
  Α ₂ Is 30 ppm / ° C. or more and 300 ppm / ° C. or less,
  The (Tc−Tg) is 5 ° C. or more and 100 ° C. or less,
  The adhesive film, wherein the Tg is 80 ° C or higher and 180 ° C or lower.   The adhesive film according to any one of claims 1 to 3,
  The adhesive film whose board | substrate thickness of said 1st semiconductor element and said 2nd semiconductor element is 10 micrometers or more and 200 micrometers or less.   The adhesive film according to any one of claims 1 to 4,
  The adhesive film whose film thickness of the said adhesive film is 5 micrometers or more and 100 micrometers or less.   The adhesive film according to any one of claims 1 to 5,
  An adhesive film in which the connection between the connection terminal of the first semiconductor element and the connection terminal of the second semiconductor element is solder bonding.   The adhesive film according to any one of claims 1 to 6,
  The adhesive film further includes an inorganic filler, and the content of the inorganic filler is 20% by weight or more and 80% by weight or less with respect to the entire adhesive film.   The adhesive film according to claim 7,
  The adhesive film whose average particle diameter of the said inorganic filler is 0.5 micrometer or less.   The adhesive film according to any one of claims 1 to 8,
  The adhesive film further includes a thermoplastic resin, and the content of the thermoplastic resin is 0.1 wt% or more and 10 wt% or less with respect to the entire adhesive film.   The adhesive film according to any one of claims 1 to 9,
  The adhesive film in which the flux active compound includes a flux active compound having a carboxyl group or a flux active compound having a phenolic hydroxyl group.   The adhesive film according to any one of claims 1 to 10,
  The average linear expansion coefficient of the cured product of the adhesive film of 25 ° C. or more and Tg or less is α ₁ (Ppm / ° C)
  Average linear expansion coefficient α of the first semiconductor element at 25 to 300 ° C. _1-s (Ppm / ° C)
  α ₁ -Α _1-s ≦ 80 (ppm / ° C.) Adhesive film.   The adhesive film according to claim 11,
  Α ₁ However, the adhesive film is 20 ppm / ° C. or more and 75 ppm / ° C. or less.

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