JP4692101B2 - Part joining method - Google Patents

Part joining method Download PDF

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JP4692101B2
JP4692101B2 JP2005186730A JP2005186730A JP4692101B2 JP 4692101 B2 JP4692101 B2 JP 4692101B2 JP 2005186730 A JP2005186730 A JP 2005186730A JP 2005186730 A JP2005186730 A JP 2005186730A JP 4692101 B2 JP4692101 B2 JP 4692101B2
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component
pressure
resin layer
bonding
temporarily fixed
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JP2007005707A (en
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浅見  博
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Sony Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Description

本発明は、例えば配線基板への半導体装置の実装工程に用いて好適な部品接合方法およびこの方法に用いられる部品接合用治具に関する。   The present invention relates to a component bonding method suitable for use in, for example, a process of mounting a semiconductor device on a wiring board, and a component bonding jig used in this method.

半導体装置の配線基板等への接合(実装)形態は、電子機器の軽薄短小の要求に応えてピン挿入型から表面実装型へ移行してきている。表面実装型の中でも接続リードが半導体装置の側面から突出するタイプよりも、半導体装置の裏面にバンプをアレイ状に並べたBGA(Ball Grid Array)タイプが、特に多ピン化に対して有利とされている。   The bonding (mounting) form of a semiconductor device to a wiring board or the like has been shifted from a pin insertion type to a surface mounting type in response to the demand for light and thin electronic devices. The BGA (Ball Grid Array) type in which bumps are arranged in an array on the back surface of the semiconductor device is more advantageous than the surface mount type in which the connection leads protrude from the side surface of the semiconductor device. ing.

BGAタイプの半導体装置の接合方法としては、例えば図6に示す方法が知られている(下記特許文献1参照)。図6Aに示すように、半導体装置81には高温はんだのバンプ82が形成され、基板84の導体部(ランド)85上には低温はんだ86が塗布されている。基板84上には、酸化膜を除去して接合性を高めるためのフラックス83が塗布されている。   As a method for bonding a BGA type semiconductor device, for example, a method shown in FIG. 6 is known (see Patent Document 1 below). As shown in FIG. 6A, bumps 82 of high-temperature solder are formed on the semiconductor device 81, and low-temperature solder 86 is applied on the conductor portion (land) 85 of the substrate 84. On the substrate 84, a flux 83 is applied to remove the oxide film and improve the bonding property.

図6Bに示すように、半導体装置81は基板84に対して押圧されながら加熱され、低温はんだ86が溶融してバンプ82が導体部85と電気的に接合される。接合後、図6Cに示すように、フラックス83が洗浄により除去される。そして、図6Dに示すように、半導体装置81と基板84との間の間隙に熱硬化性樹脂でなるアンダーフィル材87を供給し加熱硬化させて接合部を保護する。   As shown in FIG. 6B, the semiconductor device 81 is heated while being pressed against the substrate 84, the low-temperature solder 86 is melted, and the bumps 82 are electrically joined to the conductor portions 85. After joining, as shown in FIG. 6C, the flux 83 is removed by washing. Then, as shown in FIG. 6D, an underfill material 87 made of a thermosetting resin is supplied to the gap between the semiconductor device 81 and the substrate 84 and is cured by heating to protect the joint.

この方法では、半導体装置81と基板84とを接合した後、接合部に残存するフラックス83を除去する工程が必要とされるが、バンプピッチの微細化によりフラックスの洗浄が十分できなくなりつつあると同時に、洗浄力のある有機溶剤は環境負荷が大きいため使用制限の要請が高い。   In this method, after the semiconductor device 81 and the substrate 84 are bonded, a step of removing the flux 83 remaining in the bonded portion is required. However, the flux cannot be sufficiently cleaned due to the finer bump pitch. At the same time, organic solvents with detergency have a high environmental impact, so there is a high demand for use restrictions.

一方、最近では、図7Aに示すように、フラックス機能を有する樹脂材94を基板95上に前もって塗布しておき、図7Bに示すように、半導体装置91のバンプ92の先端部92aと基板95の導体部96との接合を行うと同時に、樹脂材94を加熱硬化させてアンダーフィルを形成する方法も提案されている(下記特許文献2参照)。   On the other hand, recently, as shown in FIG. 7A, a resin material 94 having a flux function is applied in advance onto the substrate 95, and as shown in FIG. 7B, the tip end portions 92a of the bumps 92 of the semiconductor device 91 and the substrate 95 are applied. A method has also been proposed in which an underfill is formed by heat-curing the resin material 94 at the same time as bonding to the conductor portion 96 (see Patent Document 2 below).

これに用いられる樹脂材94は、未硬化状態では接合面及びはんだ材料の酸化物等を除去して接合性を高め、さらに接合時(リフロー時)に硬化して接合部を補強する。この樹脂材94は、一般的なフラックス材料と異なり、接合後の洗浄除去が不要とされる。   In the uncured state, the resin material 94 used for this removes the joining surface and the oxide of the solder material to improve the joining property, and further hardens at the time of joining (during reflow) to reinforce the joined part. Unlike the general flux material, the resin material 94 does not require cleaning and removal after bonding.

ところで、上述した従来の半導体装置91の接合方法には、フリップチップマウンタと呼ばれる実装機を用いて行われている。図8に模式的に示すように、実装機101は、半導体装置91を吸着保持する吸着具102をガイド軸103に沿って移動自在な構成を有している。実装機91は、吸着ノズル102に保持された半導体装置91を加熱冷却する機構が内蔵されている。   Incidentally, the above-described conventional bonding method of the semiconductor device 91 is performed using a mounting machine called a flip chip mounter. As schematically illustrated in FIG. 8, the mounting machine 101 has a configuration in which the suction tool 102 that sucks and holds the semiconductor device 91 can be moved along the guide shaft 103. The mounting machine 91 has a built-in mechanism for heating and cooling the semiconductor device 91 held by the suction nozzle 102.

半導体装置91と接合される基板95は、作業台103上の基板保持面104に保持され、吸着ノズル102に吸着された半導体装置91と対向される。そして、接合時、吸着ノズル102が矢印A方向に移動し半導体装置91を基板95へ所定圧力で押し付けながら、半導体装置91をリフロー温度に加熱してはんだ付けする。その後、半導体装置91の冷却工程を経て、吸着ノズル102による半導体装置91の吸着動作が解除され、接合が完了とされる。   The substrate 95 to be bonded to the semiconductor device 91 is held on the substrate holding surface 104 on the work table 103 and is opposed to the semiconductor device 91 sucked by the suction nozzle 102. At the time of bonding, the suction nozzle 102 moves in the direction of arrow A, and the semiconductor device 91 is heated to the reflow temperature and soldered while pressing the semiconductor device 91 against the substrate 95 with a predetermined pressure. Thereafter, through the cooling process of the semiconductor device 91, the suction operation of the semiconductor device 91 by the suction nozzle 102 is released, and the joining is completed.

特開2005−51128号公報JP 2005-51128 A 特開2003−158153号公報JP 2003-158153 A

図8に示した実装機101を用いる従来の部品接合方法においては、上述したように実装機101で半導体装置91を機械的に押圧しながらバンプ92を基板95の導体部96へ接合するようにしている。半導体装置91に加えられる押圧力は、予め設定された圧力に制限されている。   In the conventional component bonding method using the mounting machine 101 shown in FIG. 8, the bump 92 is bonded to the conductor portion 96 of the substrate 95 while mechanically pressing the semiconductor device 91 with the mounting machine 101 as described above. ing. The pressing force applied to the semiconductor device 91 is limited to a preset pressure.

しかしながら、例えばリフロー加熱時等に発生する熱で、実装機101の機構部が熱膨張し、これが原因で半導体装置91に過荷重が加わり、バンプや半導体装置91あるいは基板95の損傷を招くおそれがある。また、過荷重によりバンプが潰れ、隣接するバンプと接触する等してブリッジが発生するおそれがある。   However, for example, the heat generated during reflow heating causes the mechanical portion of the mounting machine 101 to thermally expand, which may cause an overload to the semiconductor device 91 and cause damage to the bumps, the semiconductor device 91, or the substrate 95. is there. Further, the bump may be crushed due to overload, and a bridge may be generated due to contact with an adjacent bump.

更に、従来の部品接合方法では、実装機101を用いて半導体装置91を1個ずつ基板95へ接合する工法であるので、生産性の向上が図れないという問題もある。なお、実装機101を複数台用いて生産性を高めることも可能であるが、作業スペースおよび装置コストが増大し現実的でない。   Furthermore, since the conventional component bonding method is a method of bonding the semiconductor devices 91 to the substrate 95 one by one using the mounting machine 101, there is a problem that productivity cannot be improved. Although it is possible to increase the productivity by using a plurality of mounting machines 101, the work space and the apparatus cost increase, which is not realistic.

本発明は上述の問題に鑑みてなされ、接合時における部品の過荷重を防止でき、生産性の向上をも図ることができる部品接合方法およびこれに用いられる部品接合用治具を提供することを課題とする。   The present invention has been made in view of the above-described problems, and provides a component bonding method that can prevent overload of components during bonding and can improve productivity, and a component bonding jig used therefor. Let it be an issue.

以上の課題を解決するに当たり、本発明の部品接合方法は、突起電極を有する第1の被接合部品と、突起電極と接合される端子部を有する第2の被接合部品と、を相互に接合する部品接合方法であって、突起電極または端子部にははんだ層が形成されており、第2の被接合部品の端子形成面に粘着性樹脂層を形成する工程と、粘着性樹脂層に突起電極を食い込ませて第1,第2の被接合部品の仮固定体を作製する工程と、仮固定体を流体圧で一定加圧しながら上記はんだ層を溶融させ突起電極と端子部とを接合する工程を有する。   In solving the above problems, the component joining method of the present invention joins a first joined component having a protruding electrode and a second joined component having a terminal portion joined to the protruding electrode. A solder bonding layer is formed on the protruding electrode or the terminal portion, and a step of forming an adhesive resin layer on the terminal forming surface of the second bonded component, and a protrusion on the adhesive resin layer A process of making a temporary fixing body of the first and second parts to be joined by biting in the electrodes, and melting the solder layer while joining the temporary fixing body with fluid pressure to join the protruding electrode and the terminal portion. Process.

本発明においては、第1の被接合部品と第2の被接合部品とを粘着性樹脂層を介して仮固定した後、その仮固定体に一定の流体圧を作用させながら加熱し、はんだ層をリフローさせて突起電極と端子部とを相互に接合する。一定の流体圧を部品に作用させることで、リフロー加熱時における部品の過荷重を防止し、接合部の破損やブリッジの発生を回避する。   In the present invention, the first and second parts to be joined are temporarily fixed via the adhesive resin layer, and then heated while applying a certain fluid pressure to the temporarily fixed body, and the solder layer Are reflowed to bond the protruding electrode and the terminal portion to each other. By applying a constant fluid pressure to the parts, the parts are prevented from being overloaded during reflow heating, and damage to the joints and occurrence of bridges are avoided.

一方、本発明の部品接合用治具は、治具本体と、この治具本体の内部に形成され流体圧が導入される圧力室と、治具本体の内部に形成され第1,第2の被接合部品の仮固定体を収容する部品収容室と、圧力室と部品収容室との間を仕切る弾性シート体と、圧力室に導入された流体圧が所定圧を超えたときに開弁するリリーフ弁とを備えている。   On the other hand, the component joining jig of the present invention includes a jig body, a pressure chamber formed in the jig body and into which fluid pressure is introduced, and formed in the jig body. The component storage chamber for storing the temporarily fixed body of the component to be joined, the elastic sheet body for partitioning between the pressure chamber and the component storage chamber, and the valve is opened when the fluid pressure introduced into the pressure chamber exceeds a predetermined pressure. And a relief valve.

本発明に係る部品接合用治具は、そのままリフロー炉等の加熱装置へ装填される構成となっている。リフロー炉内では、治具本体の部品収容室に収容された被接合部品の仮固定体が、弾性シート材を介して流体圧による加圧作用を受けて接合される。流体圧には空気等のガス圧、油等の液圧が適用可能であるが、空気圧が取り扱い上有利である。   The component joining jig according to the present invention is configured to be loaded in a heating device such as a reflow furnace as it is. In the reflow furnace, the temporarily fixed bodies of the parts to be joined housed in the parts housing chamber of the jig main body are joined by receiving a pressurizing action by fluid pressure through the elastic sheet material. As the fluid pressure, a gas pressure such as air and a fluid pressure such as oil can be applied, but air pressure is advantageous in handling.

加熱により膨張した空気圧は、リリーフ弁を介して圧力室から開放されるので、仮固定体に対する押圧力を常に一定に維持することができる。また、処理室内に複数の仮固定体を収容することで、同時に複数の接合処理が可能となるので、生産性の向上を図ることができる。   Since the air pressure expanded by heating is released from the pressure chamber via the relief valve, the pressing force against the temporarily fixed body can always be kept constant. In addition, by accommodating a plurality of temporarily fixed bodies in the processing chamber, a plurality of joining processes can be performed at the same time, so that productivity can be improved.

したがって本発明によれば、接合時における部品の過荷重を防止できるので、接合部の破損やブリッジの発生を回避することができる。また、同時に複数の接合処理が可能となるので、生産性の向上を図ることができる。   Therefore, according to the present invention, it is possible to prevent overloading of components at the time of joining, so that it is possible to avoid breakage of the joint and occurrence of a bridge. In addition, since a plurality of joining processes can be performed at the same time, productivity can be improved.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1および図2は、本発明の実施の形態による部品接合方法を説明する断面工程図である。図1Aは、半導体チップ11と、この半導体チップ11と接合される配線基板21を示している。本実施の形態では、半導体チップ11が本発明の「第2の被接合部品」に対応し、配線基板21が本発明の「第1の被接合部品」に対応している。   1 and 2 are cross-sectional process diagrams for explaining a component joining method according to an embodiment of the present invention. FIG. 1A shows a semiconductor chip 11 and a wiring substrate 21 bonded to the semiconductor chip 11. In the present embodiment, the semiconductor chip 11 corresponds to the “second bonded component” of the present invention, and the wiring board 21 corresponds to the “first bonded component” of the present invention.

半導体チップ11の能動面にはパッシベーション膜13を介して複数の電極パッド14がグリッド状に配列されている。電極パッド14の上には、例えばAg(銀)の微粒子が分散されたペースト膜を加熱硬化させた導電性膜15が形成されている。導電性膜15の上には、Cu(銅)、Ni(ニッケル)、Au(金)の多層膜構造でなる凸型の接合パッド18が形成されている。接合パッド18は、本発明の「端子部」に相当する。   A plurality of electrode pads 14 are arranged in a grid on the active surface of the semiconductor chip 11 with a passivation film 13 interposed therebetween. On the electrode pad 14, a conductive film 15 is formed by heat-curing a paste film in which, for example, Ag (silver) fine particles are dispersed. A convex bonding pad 18 having a multilayer structure of Cu (copper), Ni (nickel), and Au (gold) is formed on the conductive film 15. The bonding pad 18 corresponds to the “terminal portion” of the present invention.

半導体チップ11の具体的な大きさとしては、縦横の寸法が10mm、厚さは250μmで、接合パッド18の配列ピッチは200μmである。また、接合パッド18を構成するCu膜、Ni膜、Au膜の厚さはそれぞれ22μm、3μm、0.05μmである。   The specific size of the semiconductor chip 11 is a vertical and horizontal dimension of 10 mm, a thickness of 250 μm, and an array pitch of the bonding pads 18 of 200 μm. The thicknesses of the Cu film, Ni film, and Au film constituting the bonding pad 18 are 22 μm, 3 μm, and 0.05 μm, respectively.

以上のように構成される半導体チップ11は、配線基板21への実装に先だって、後述するように接合パッド18の形成面(端子形成面)に活性樹脂層19が形成される。活性樹脂層19は、未硬化状態で粘着性とフラックス機能を有する熱硬化性樹脂を半導体チップ11の端子形成面に塗布して形成される。なお、この活性樹脂層は、本発明の「粘着性樹脂層」に相当する。   In the semiconductor chip 11 configured as described above, the active resin layer 19 is formed on the formation surface (terminal formation surface) of the bonding pad 18 as described later prior to mounting on the wiring substrate 21. The active resin layer 19 is formed by applying a thermosetting resin having adhesiveness and a flux function in an uncured state to the terminal forming surface of the semiconductor chip 11. This active resin layer corresponds to the “adhesive resin layer” of the present invention.

この種の熱硬化性樹脂は、例えば、液状のビスフェノール系エポキシ系樹脂に硬化剤の作用とフラックスの作用とを有するジヒドロキシ安息香酸とフェノールフタリン、および硬化促進剤を添加したもの(特開2003−105054号公報)があるがこれに限られない。なお、この活性樹脂層19にシリカ微粒子等のフィラーを添加して、完全硬化後の弾性率あるいは熱膨張係数を調整するようにしてもよい。   This type of thermosetting resin is, for example, a liquid bisphenol-based epoxy resin to which dihydroxybenzoic acid having an action of a curing agent and an action of flux, phenolphthaline, and a curing accelerator are added (Japanese Patent Laid-Open No. 2003-1999). -105054 gazette), but is not limited thereto. A filler such as silica fine particles may be added to the active resin layer 19 to adjust the elastic modulus or thermal expansion coefficient after complete curing.

一方、配線基板21は、マザー基板でもよいしインターポーザ基板でもよい。配線基板21には、半導体チップ11の接合パッド18の配列間隔に対応してバンプ28が設けられている。このバンプ28は、本発明の「突起電極」に相当する。   On the other hand, the wiring substrate 21 may be a mother substrate or an interposer substrate. The wiring board 21 is provided with bumps 28 corresponding to the arrangement intervals of the bonding pads 18 of the semiconductor chip 11. The bumps 28 correspond to “projection electrodes” of the present invention.

バンプ28は、配線基板21上の外層絶縁樹脂膜23上に形成されビアを介して配線層24に接続された銅核26と、銅核26の周囲に形成されたはんだ27とで構成されている。銅核26は、接合後の半導体チップ11と配線基板21との間の間隙を確保する作用を有し、リフロー時に溶融しない材料であれば銅に限られない。銅核26には、はんだ27との密着性を高めるために例えばNi/Auめっきが施される。   The bump 28 includes a copper core 26 formed on the outer insulating resin film 23 on the wiring substrate 21 and connected to the wiring layer 24 through a via, and a solder 27 formed around the copper core 26. Yes. The copper core 26 is not limited to copper as long as it has a function of ensuring a gap between the bonded semiconductor chip 11 and the wiring substrate 21 and does not melt during reflow. The copper core 26 is subjected to, for example, Ni / Au plating in order to improve the adhesion with the solder 27.

はんだ27は本発明の「はんだ層」に相当し、リフロー時に溶融して半導体チップ11の接合パッド18に濡れ広がる。はんだ27としてはSnAgCu系、特に、Sn3Ag0.5Cuはんだが用いられている。なおこれ以外にも、Sn系、SnAg系、SnBi系、SnCu系、SnAgBi系、SnAgBiCu系等の他のSn系はんだを用いてもよい。   The solder 27 corresponds to the “solder layer” of the present invention, melts during reflow, and spreads wet on the bonding pads 18 of the semiconductor chip 11. As the solder 27, SnAgCu series, in particular, Sn3Ag0.5Cu solder is used. In addition, other Sn-based solders such as Sn-based, SnAg-based, SnBi-based, SnCu-based, SnAgBi-based, and SnAgBiCu-based may be used.

以上のように構成される半導体チップ11と配線基板21との接合は、以下のようにして行われる。   The semiconductor chip 11 configured as described above and the wiring substrate 21 are joined as follows.

まず、半導体チップ11の端子形成面に活性樹脂層19が形成される(図1A)。   First, the active resin layer 19 is formed on the terminal formation surface of the semiconductor chip 11 (FIG. 1A).

活性樹脂層19の形成方法としては、印刷法やスピンコート法等による塗布、ドライフィルムのラミネート処理等がある。活性樹脂層19の厚さは、例えば30μmである。なお、活性樹脂層19の形成は、半導体チップ11の製造工程の際に行ってもよいし、配線基板21への実装直前に行ってもよい。   Examples of the method for forming the active resin layer 19 include coating by a printing method, spin coating method, and the like, and a dry film laminating process. The thickness of the active resin layer 19 is, for example, 30 μm. The active resin layer 19 may be formed during the manufacturing process of the semiconductor chip 11 or may be performed immediately before mounting on the wiring substrate 21.

次に、半導体チップ11を配線基板21の上に仮止めし、半導体チップ11と配線基板21の仮固定体10Aを作製する(図1B)。   Next, the semiconductor chip 11 is temporarily fixed on the wiring board 21, and the temporarily fixed body 10A of the semiconductor chip 11 and the wiring board 21 is manufactured (FIG. 1B).

半導体チップ11は、その接合パッド18が配線基板21のバンプ28の直上に位置するように位置合わせされた後、140℃程度に加熱され、配線基板21に対して軽く押し当てられる。配線基板21に対する半導体チップ11の押圧量は、活性樹脂層19にバンプ28の先端が食い込む程度の大きさとされる。なお、配線基板21に対する半導体チップ11の位置合わせは、チップマウンタ等の位置合わせ機能を備えた機器を用いて行われる。   The semiconductor chip 11 is aligned so that the bonding pad 18 is located immediately above the bump 28 of the wiring board 21, and then heated to about 140 ° C. and lightly pressed against the wiring board 21. The amount of pressing of the semiconductor chip 11 against the wiring substrate 21 is set to such a size that the tip of the bump 28 bites into the active resin layer 19. The alignment of the semiconductor chip 11 with respect to the wiring board 21 is performed using a device having an alignment function such as a chip mounter.

続いて、配線基板21に対する半導体チップ11のリフロー実装を行う(図2C)。   Subsequently, the semiconductor chip 11 is reflow mounted on the wiring board 21 (FIG. 2C).

このリフロー実装工程において、半導体チップ11はその上面に一定の空気圧を受けて加圧されながら、リフロー温度(本例では250℃)に加熱される。これにより、活性樹脂層19が溶融しバンプ28が接合パッド18に接触する。そして、はんだ27が溶融し接合パッド18上に濡れ広がる。活性樹脂層19は、溶融したはんだ27の周囲を取り囲みフラックス機能で酸化物を除去する。その後、冷却工程に移行してはんだ27が固化する。これにより、接合パッド18と銅核26との間に接合部30が形成された部品実装体10Bが作製される。   In this reflow mounting process, the semiconductor chip 11 is heated to the reflow temperature (250 ° C. in this example) while being pressurized by receiving a constant air pressure on the upper surface thereof. As a result, the active resin layer 19 is melted and the bumps 28 come into contact with the bonding pads 18. Then, the solder 27 is melted and spreads on the bonding pad 18. The active resin layer 19 surrounds the molten solder 27 and removes the oxide with a flux function. Thereafter, the process proceeds to a cooling step and the solder 27 is solidified. Thereby, the component mounting body 10 </ b> B in which the bonding portion 30 is formed between the bonding pad 18 and the copper core 26 is manufactured.

なお、リフロー実装工程は、図3に示す部品接合用治具35を用いて行われる。部品接合用治具35の構成および当該リフロー実装工程の詳細については後述する。また、接合後における活性樹脂層19の洗浄除去は行われない。   The reflow mounting process is performed using a component joining jig 35 shown in FIG. Details of the configuration of the component joining jig 35 and the reflow mounting process will be described later. Further, the active resin layer 19 is not cleaned and removed after bonding.

最後に、作製された実装体10Bの接合部30をアンダーフィル31で封止する工程が行われる(図2D)。これにより、半導体装置10Cが作製される。   Finally, a process of sealing the joint portion 30 of the manufactured mounting body 10B with the underfill 31 is performed (FIG. 2D). Thereby, the semiconductor device 10C is manufactured.

アンダーフィル31の構成樹脂は、活性樹脂層19の物性との関係で決められる。本実施の形態では、活性樹脂層19よりもアンダーフィル31の方が弾性率が低く、かつ熱膨張係数が大きくなるように材料設計されている。これにより、接合部31に作用するストレス(熱応力)から、接合部18を効果的に保護することが可能となる。   The constituent resin of the underfill 31 is determined by the relationship with the physical properties of the active resin layer 19. In the present embodiment, the material design is such that the underfill 31 has a lower elastic modulus and a higher thermal expansion coefficient than the active resin layer 19. Thereby, it is possible to effectively protect the joint 18 from stress (thermal stress) acting on the joint 31.

続いて、図3を参照して本発明に係る部品接合用治具35の構成について説明する。   Next, the configuration of the component joining jig 35 according to the present invention will be described with reference to FIG.

図3は本実施の形態の部品接合用治具35の概略構成を示す断面図である。ステンレスやアルミニウム合金等の金属製の治具本体36の内部に、圧力室37と部品収容室38とを上下で区画する弾性シート体39が設けられている。治具本体36は、上本体部36Aと下本体部36Bの2分割構造で、弾性シート体39は上本体部36Aの下面側に固定されており、下本体36Bとの組合せ時に上下の本体部36A,36B間に周縁部および中間部が挟圧される。   FIG. 3 is a cross-sectional view showing a schematic configuration of the component joining jig 35 of the present embodiment. An elastic sheet body 39 that divides the pressure chamber 37 and the component storage chamber 38 in the upper and lower directions is provided inside a jig body 36 made of metal such as stainless steel or aluminum alloy. The jig main body 36 has a two-part structure of an upper main body portion 36A and a lower main body portion 36B. The elastic sheet 39 is fixed to the lower surface side of the upper main body portion 36A, and the upper and lower main body portions are combined with the lower main body 36B. A peripheral part and an intermediate part are clamped between 36A and 36B.

圧力室37は、図示しない圧力源(エアタンクあるいはエアコンプレッサ)に接続される圧力供給口40と連通している。この圧力供給口40には、上記圧力源から圧力室37への空気の流入を許容しその逆の流れを禁止する逆止弁41が設けられている。これにより、圧力室37に導入された所定圧の空気圧の流出が防止され、圧力源との接続が解除された治具単独での取り回しが可能となっている。   The pressure chamber 37 communicates with a pressure supply port 40 connected to a pressure source (an air tank or an air compressor) (not shown). The pressure supply port 40 is provided with a check valve 41 that allows air to flow into the pressure chamber 37 from the pressure source and prohibits the reverse flow. As a result, the air pressure of a predetermined pressure introduced into the pressure chamber 37 is prevented from flowing out, and the jig alone that is disconnected from the pressure source can be handled.

また、上本体部36Aには、導入された空気圧が所定圧を超えた際にその超過圧力を外部に解放するリリーフ弁42が設けられている。このリリーフ弁42は即ち、リフロー炉への装填時に加熱により膨張した空気の増圧分を外部に解放し、圧力室37の内部を一定の圧力に維持する機能を果たす。   The upper body portion 36A is provided with a relief valve 42 that releases the excess pressure to the outside when the introduced air pressure exceeds a predetermined pressure. That is, the relief valve 42 functions to release the increased pressure of the air expanded by heating when it is loaded into the reflow furnace to maintain the inside of the pressure chamber 37 at a constant pressure.

部品収容室38は、図1Bを参照して説明した半導体チップ11と配線基板21の仮固定体10Aを収容する。部品収容室38は、複数の仮固定体10Aを同時に収容できる広さに形成することができる。仮固定体10Aが載置される部品収容室38の底部には、貫通孔43が形成されており、部品収容室38の内外における空気の移動が可能となっている。   The component accommodating chamber 38 accommodates the semiconductor chip 11 and the temporarily fixed body 10A of the wiring board 21 described with reference to FIG. 1B. The component storage chamber 38 can be formed to a size that can simultaneously store a plurality of temporarily fixed bodies 10A. A through hole 43 is formed at the bottom of the component storage chamber 38 on which the temporarily fixed body 10A is placed, and air can be moved inside and outside the component storage chamber 38.

部品収容室38に収容される複数の仮固定体10Aは、図1Bに示したように各々個片化された形態のものでもよいが、本実施の形態では図4に示したように、共通の配線基板21A上に複数の半導体チップ11が仮固体された複合仮固定体10としている。なお、この複合仮固定体10は、いわゆるマルチチップパッケージであってもよいし、接合後に個々に個片化されてもよい。   The plurality of temporarily fixed bodies 10A accommodated in the component accommodating chamber 38 may be in the form of individual pieces as shown in FIG. 1B, but in this embodiment, as shown in FIG. A composite temporarily fixed body 10 in which a plurality of semiconductor chips 11 are temporarily solidified on the wiring board 21A is formed. The composite temporarily fixed body 10 may be a so-called multi-chip package, or may be individually separated after joining.

治具本体36は、リフロー炉へ装填できる大きさの範囲内で、複数の部品収容室38を有する構成とされている。部品収容室38と部品収容室38との間は隔壁36C(図3)で隔てられている。各部品収容室38は、圧力室37が共通とされている。   The jig main body 36 is configured to have a plurality of component housing chambers 38 within a range that can be loaded into the reflow furnace. The component storage chamber 38 and the component storage chamber 38 are separated by a partition wall 36C (FIG. 3). Each component storage chamber 38 has a common pressure chamber 37.

弾性シート体39は、リフロー温度に耐え得る耐熱強度を有する材料であれば特に制限されず、フッ素系ゴムやシリコーン系ゴム等が用いられる。この弾性シート体39は、圧力室38に所定の空気圧が導入された際に、図5に示すように部品収容室38側へ弾性変形し、各部品収容室38に収容された仮固体体10の上面側を均等に押圧できる程度の弾性率を有する。   The elastic sheet 39 is not particularly limited as long as it is a material having heat resistance that can withstand the reflow temperature, and fluorine rubber, silicone rubber, or the like is used. When a predetermined air pressure is introduced into the pressure chamber 38, the elastic sheet body 39 is elastically deformed toward the component storage chamber 38 as shown in FIG. 5, and the temporary solid body 10 stored in each component storage chamber 38. The elastic modulus is such that the upper surface side can be evenly pressed.

以上のように構成される本実施の形態の部品接合用治具35は、上本体部36Aと下本体部36Bとを分離することで開放された各部品収容室38に、図4に示した構成の半導体チップ11と配線基板21Aの仮固定体10がそれぞれ収容される。その後、上本体部と下本体部36Bとが一体化され、弾性シート体39により圧力室37と部品収容室38との間が気密に区画される。   The component joining jig 35 of the present embodiment configured as described above is shown in FIG. 4 in each component storage chamber 38 opened by separating the upper main body portion 36A and the lower main body portion 36B. The semiconductor chip 11 having the configuration and the temporarily fixed body 10 of the wiring board 21A are accommodated. Thereafter, the upper main body portion and the lower main body portion 36B are integrated, and the elastic sheet 39 partitions the pressure chamber 37 and the component storage chamber 38 in an airtight manner.

ここで、仮固定体10を構成する半導体チップ11と配線基板21Aとはタック性(粘着性)のある活性樹脂層19(図1B)を介して位置決めされているので、両者間に位置ズレを起こすことなく部品収容室38へ収容することができる。また、リフロー炉の移送過程での位置ズレも防止される。   Here, since the semiconductor chip 11 and the wiring board 21A constituting the temporarily fixed body 10 are positioned via the active resin layer 19 (FIG. 1B) having tackiness (adhesiveness), there is a misalignment between them. It can be accommodated in the component accommodating chamber 38 without being raised. Further, misalignment in the transfer process of the reflow furnace is also prevented.

次に、圧力供給口40に図示しない圧力源が接続され、圧力室37内に所定圧(本例ではゲージで0.1気圧以下)の圧縮空気が導入される。これにより、弾性シート体39は部品収容室38側へ弾性変形し、図5に示したように、各部品収容室38において仮固定体10を構成する各々の半導体チップ11上面を均等な圧力で加圧する。   Next, a pressure source (not shown) is connected to the pressure supply port 40, and compressed air having a predetermined pressure (in this example, 0.1 atmospheric pressure or less) is introduced into the pressure chamber 37. As a result, the elastic sheet 39 is elastically deformed toward the component housing chamber 38, and as shown in FIG. 5, the upper surface of each semiconductor chip 11 constituting the temporarily fixed body 10 in each component housing chamber 38 is equalized. Pressurize.

その後、部品接合用治具35は、図示しないリフロー炉へ装填される。リフロー炉において、部品接合用治具35はリフロー温度に加熱される。そして、仮固定体10を構成する半導体チップ11と配線基板21Aとは、圧力室37からの加圧作用を受けながら図2Cに示したように相互にはんだ接合されることで、部品実装体10Bが製造される。   Thereafter, the component joining jig 35 is loaded into a reflow furnace (not shown). In the reflow furnace, the component joining jig 35 is heated to the reflow temperature. Then, the semiconductor chip 11 and the wiring board 21A constituting the temporarily fixed body 10 are soldered to each other as shown in FIG. 2C while receiving a pressurizing action from the pressure chamber 37, so that the component mounting body 10B. Is manufactured.

本実施の形態によれば、リフロー炉において、圧力室37内の圧縮空気が加熱作用で膨張するが、その増圧分がリリーフ弁42を介して外部へ解放される。従って、圧力室37の内部は加熱前後において常に一定の圧力に維持されるので、半導体チップ11に対する加圧力も一定とされる。これにより、過荷重よるはんだ接合部の破損や、ブリッジの発生を確実に回避することができ、信頼性の高い部品接合を実現することができる。   According to the present embodiment, in the reflow furnace, the compressed air in the pressure chamber 37 is expanded by the heating action, but the increased pressure is released to the outside through the relief valve 42. Therefore, since the inside of the pressure chamber 37 is always maintained at a constant pressure before and after heating, the pressure applied to the semiconductor chip 11 is also constant. Thereby, breakage of the solder joint due to overload and occurrence of a bridge can be reliably avoided, and highly reliable component joining can be realized.

特に、半導体チップ11の接合時に所望の接合圧力を付与することができるので、半導体チップ11の自重や活性樹脂層19の粘性、バンプ28の先端形状等に応じて最適な接合圧力を設定できる。また、品種変更や条件出しが容易に行えるようになる。さらに、活性樹脂層19へのフィラー混入量の自由度が高まり、熱膨張係数を例えば60ppm以下(40ppm)へ低減することができた。   In particular, since a desired bonding pressure can be applied when the semiconductor chip 11 is bonded, an optimum bonding pressure can be set according to the weight of the semiconductor chip 11, the viscosity of the active resin layer 19, the tip shape of the bump 28, and the like. Moreover, it becomes possible to easily change the product type and set the conditions. Furthermore, the degree of freedom in the amount of filler mixed into the active resin layer 19 was increased, and the thermal expansion coefficient could be reduced to, for example, 60 ppm or less (40 ppm).

また、本実施の形態の部品接合用治具35によれば、これ一台で同時に複数の部品実装体10B(図2C)を製造することができるので、従来のチップマウンタを用いた実装工程と比較して、生産性の向上を図ることができる。実際に、チップマウンタを用いる場合に比べて処理時間を半分にまで短縮できたことが確認されている。   Further, according to the component joining jig 35 of the present embodiment, a plurality of component mounting bodies 10B (FIG. 2C) can be manufactured simultaneously with this single unit, so that a mounting process using a conventional chip mounter can be achieved. In comparison, productivity can be improved. In fact, it has been confirmed that the processing time can be reduced by half compared to the case of using a chip mounter.

さらに、本実施の形態の部品接合用治具35によれば、圧力源と接続される圧力供給口40に空気の逆流を防止する逆止弁41が設けられているので、当該治具35を圧力源に常に接続しておく必要がなく、治具単独での取り回しが可能となる。   Furthermore, according to the component joining jig 35 of the present embodiment, the check valve 41 for preventing the backflow of air is provided at the pressure supply port 40 connected to the pressure source. There is no need to always connect to the pressure source, and it is possible to handle the jig alone.

以上、本発明の実施の形態について説明したが、勿論、本発明はこれに限定されることなく、本発明の技術的思想に基づいて種々の変形が可能である。   The embodiment of the present invention has been described above. Of course, the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.

例えば以上の実施の形態では、半導体チップ11側に活性樹脂層19を設けたが、これに代えて、配線基板21(21A)側に活性樹脂層19を設けてもよい。また、半導体チップ11側に突起電極を形成し、配線基板21側に端子部を形成してもよい。更に、はんだ27はバンプ28に形成する場合に限らず、接合パッド18上に設けてもよい。   For example, in the above embodiment, the active resin layer 19 is provided on the semiconductor chip 11 side, but instead, the active resin layer 19 may be provided on the wiring board 21 (21A) side. Further, the protruding electrode may be formed on the semiconductor chip 11 side, and the terminal portion may be formed on the wiring board 21 side. Furthermore, the solder 27 is not limited to being formed on the bump 28, and may be provided on the bonding pad 18.

なお、本発明に係る部品接合方法は、半導体チップ11と配線基板21(21A)との接合に限らず、半導体チップどうしの接合にも適用可能である。また、半導体チップ11はベアチップに限らず、半導体チップを樹脂でモールドしたパッケージ部品であってもよい。   The component bonding method according to the present invention is not limited to bonding between the semiconductor chip 11 and the wiring substrate 21 (21A), but can be applied to bonding between semiconductor chips. The semiconductor chip 11 is not limited to a bare chip, and may be a package component obtained by molding a semiconductor chip with a resin.

また、以上の実施の形態では、粘着性樹脂層として活性樹脂層19を用いたが、これに限らず、例えば異方性導電フィルム(ACF)等の未硬化状態で一定の粘着性がある樹脂層を用いてもよい。   In the above embodiment, the active resin layer 19 is used as the adhesive resin layer. However, the present invention is not limited to this, and for example, a resin having a certain adhesive property in an uncured state such as an anisotropic conductive film (ACF). Layers may be used.

さらに、以上の実施の形態では、部品接合用治具35をリフロー炉へ装填することで、半導体チップ11と配線基板21Aとの接合を行うようにしたが、この部品接合用治具にヒータ等の加熱源を内蔵させ、リフロー炉を用いることなく治具単独で部品の接合を行うことも可能である。   Further, in the above embodiment, the component bonding jig 35 is loaded into the reflow furnace to bond the semiconductor chip 11 and the wiring board 21A. The component bonding jig includes a heater or the like. It is also possible to incorporate the heat source and to join the components with a jig alone without using a reflow furnace.

なお、上述の実施形態で説明した部品接合用治具35に対し、更に、空気圧が設定圧を下回った際に不足圧力を外部から補充可能なように逆止弁等の弁機構を設けてもよい。これにより、リフロー炉において、冷却工程での圧力不足を緩和でき、半導体チップ11に対して終始一定の圧力を付与することが可能となる。   In addition, a valve mechanism such as a check valve may be provided for the component joining jig 35 described in the above embodiment so that the underpressure can be replenished from the outside when the air pressure falls below the set pressure. Good. Thereby, in a reflow furnace, the pressure shortage in a cooling process can be relieved, and it becomes possible to apply a fixed pressure to the semiconductor chip 11 from beginning to end.

本発明の実施の形態による部品接合方法を説明する工程断面図である。It is process sectional drawing explaining the component joining method by embodiment of this invention. 本発明の実施の形態による部品接合方法を説明する工程断面図である。It is process sectional drawing explaining the component joining method by embodiment of this invention. 本発明の実施の形態による部品接合用治具35の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the jig | tool 35 for component joining by embodiment of this invention. 配線基板21Aに複数の半導体チップ11が仮止めされた複合仮固定体10を示す図である。It is a figure which shows the composite temporarily fixed body 10 by which several semiconductor chip 11 was temporarily fixed to the wiring board 21A. 部品接合用実35の一作用を説明する断面図である。It is sectional drawing explaining one effect | action of the components for actual 35. 従来の部品接合方法を説明する工程断面図である。It is process sectional drawing explaining the conventional component joining method. 従来の他の部品接合方法を説明する工程断面図である。It is process sectional drawing explaining the other conventional component joining method. チップマウンタの概略構成図である。It is a schematic block diagram of a chip mounter.

符号の説明Explanation of symbols

10,10A…仮固体体、10B…部品実装体、10C…半導体装置、11…半導体チップ、18…接合パッド(端子部)、19…活性樹脂層(粘着性樹脂層)、21…配線基板、27…はんだ、28…バンプ(突起電極)、30…接合部、31…アンダーフィル、35…部品接合用治具、36…治具本体、37…圧力室、38…部品収容室、39…弾性シート体、40…圧力供給口、41…逆止弁、42…リリーフ弁。   DESCRIPTION OF SYMBOLS 10,10A ... Temporary solid body, 10B ... Component mounting body, 10C ... Semiconductor device, 11 ... Semiconductor chip, 18 ... Bonding pad (terminal part), 19 ... Active resin layer (adhesive resin layer), 21 ... Wiring board, DESCRIPTION OF SYMBOLS 27 ... Solder, 28 ... Bump (projection electrode), 30 ... Joint part, 31 ... Underfill, 35 ... Jig for component joining, 36 ... Jig main body, 37 ... Pressure chamber, 38 ... Component accommodation chamber, 39 ... Elasticity Sheet body, 40 ... pressure supply port, 41 ... check valve, 42 ... relief valve.

Claims (5)

突起電極を有する第1の被接合部品と、前記突起電極と接合される端子部を有する第2の被接合部品と、を相互に接合する部品接合方法であって、
前記突起電極または前記端子部にははんだ層が形成されており、
前記第2の被接合部品の端子形成面に粘着性樹脂層を形成する工程と、
前記粘着性樹脂層に前記突起電極を食い込ませて前記第1,第2の被接合部品の仮固定体を作製する工程と、
前記仮固定体を流体圧で一定加圧しながら前記はんだ層を溶融させ前記突起電極と前記端子部とを接合する工程を有する
部品接合方法。
A component bonding method for bonding a first bonded component having a protruding electrode and a second bonded component having a terminal portion bonded to the protruding electrode to each other,
A solder layer is formed on the protruding electrode or the terminal portion,
Forming an adhesive resin layer on the terminal forming surface of the second bonded part;
Producing the temporarily fixed body of the first and second bonded parts by biting the protruding electrode into the adhesive resin layer;
Component bonding method and a step of joining the said protruding electrode temporarily fixed member by melting the solder layer while applying a constant pressure in the fluid pressure and the terminal portion.
前記粘着性樹脂層として、フラックス機能を有する活性樹脂を用いる
請求項1に記載の部品接合方法。
The component bonding method according to claim 1, wherein an active resin having a flux function is used as the adhesive resin layer.
前記第1,第2の被接合部品は、一方が配線基板で他方が半導体素子である
請求項1に記載の部品接合方法。
The component joining method according to claim 1, wherein one of the first and second parts to be joined is a wiring board and the other is a semiconductor element.
前記第1,第2の被接合部品は、ともに半導体素子である
請求項1に記載の部品接合方法。
The component joining method according to claim 1, wherein the first and second parts to be joined are both semiconductor elements.
前記仮固定体のリフロー工程では、複数の仮固定体を同時に一括処理する
請求項1に記載の部品接合方法。
The component joining method according to claim 1, wherein in the reflow process of the temporarily fixed body, a plurality of temporarily fixed bodies are collectively processed simultaneously.
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JP5579996B2 (en) * 2009-04-09 2014-08-27 パナソニック株式会社 Solder joining method
WO2011132384A1 (en) * 2010-04-23 2011-10-27 住友ベークライト株式会社 Device and method for producing electronic device, and pair of compressed members thereof
JP2012104782A (en) * 2010-11-15 2012-05-31 Elpida Memory Inc Method and apparatus for manufacturing semiconductor device
JP6172654B2 (en) * 2013-03-14 2017-08-02 アルファーデザイン株式会社 Component pressing device and heating system using the component pressing device
JP2016009850A (en) * 2014-06-26 2016-01-18 東レエンジニアリング株式会社 Mounting device and mounting method
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