KR20120051562A - 레벨 변환기, 그것을 포함하는 시스템-온-칩, 그리고 그것을 포함하는 멀티미디어 장치 - Google Patents

레벨 변환기, 그것을 포함하는 시스템-온-칩, 그리고 그것을 포함하는 멀티미디어 장치 Download PDF

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Publication number
KR20120051562A
KR20120051562A KR1020110005020A KR20110005020A KR20120051562A KR 20120051562 A KR20120051562 A KR 20120051562A KR 1020110005020 A KR1020110005020 A KR 1020110005020A KR 20110005020 A KR20110005020 A KR 20110005020A KR 20120051562 A KR20120051562 A KR 20120051562A
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KR
South Korea
Prior art keywords
voltage
clock
inverter
processor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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KR1020110005020A
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English (en)
Korean (ko)
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구자천
임경묵
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삼성전자주식회사
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Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to DE201110084985 priority Critical patent/DE102011084985A1/de
Priority to US13/292,180 priority patent/US8970454B2/en
Priority to JP2011247518A priority patent/JP2012105277A/ja
Priority to CN2011103594188A priority patent/CN102545874A/zh
Publication of KR20120051562A publication Critical patent/KR20120051562A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
KR1020110005020A 2010-11-12 2011-01-18 레벨 변환기, 그것을 포함하는 시스템-온-칩, 그리고 그것을 포함하는 멀티미디어 장치 Withdrawn KR20120051562A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE201110084985 DE102011084985A1 (de) 2010-11-12 2011-10-21 Pegelschieber sowie System-auf-Chip und Multimedia-Bauelement mit selbigem
US13/292,180 US8970454B2 (en) 2010-11-12 2011-11-09 Level shifter, system-on-chip including the same, and multimedia device including the same
JP2011247518A JP2012105277A (ja) 2010-11-12 2011-11-11 レベル変換器、それを含むシステムオンチップ、及びそれを含むマルチメディア装置
CN2011103594188A CN102545874A (zh) 2010-11-12 2011-11-14 电平转换器、包括其的片上系统、和包括其的多媒体设备

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41295210P 2010-11-12 2010-11-12
US61/412,952 2010-11-12

Publications (1)

Publication Number Publication Date
KR20120051562A true KR20120051562A (ko) 2012-05-22

Family

ID=46268624

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110005020A Withdrawn KR20120051562A (ko) 2010-11-12 2011-01-18 레벨 변환기, 그것을 포함하는 시스템-온-칩, 그리고 그것을 포함하는 멀티미디어 장치

Country Status (3)

Country Link
JP (1) JP2012105277A (enrdf_load_stackoverflow)
KR (1) KR20120051562A (enrdf_load_stackoverflow)
CN (1) CN102545874A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018063712A1 (en) * 2016-09-27 2018-04-05 Intel Corporation Fused voltage level shifting latch
US11588485B2 (en) 2020-12-15 2023-02-21 SK Hynix Inc. Power domain change circuit and operating method thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015159434A (ja) 2014-02-24 2015-09-03 ソニー株式会社 電圧変換回路、および、電子回路
JP2017069942A (ja) * 2015-09-30 2017-04-06 ラピスセミコンダクタ株式会社 インターフェース回路
US10651832B2 (en) * 2018-08-10 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifter
CN110136667B (zh) * 2019-05-06 2021-06-04 晶晨半导体(上海)股份有限公司 一种驱动电路
CN113098486B (zh) * 2021-04-29 2024-11-26 浙江芯劢微电子股份有限公司 低电平逻辑转高电平逻辑的高频levelshift电路与电路系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11163713A (ja) * 1997-11-25 1999-06-18 Hitachi Ltd 半導体集積回路装置
US7190206B2 (en) * 2003-07-22 2007-03-13 Samsung Electronics Co., Ltd. Interface circuit and signal clamping circuit using level-down shifter
KR20060106106A (ko) * 2005-04-06 2006-10-12 삼성전자주식회사 고속 레벨 쉬프터
US7355446B2 (en) * 2005-05-20 2008-04-08 Samsung Electronics Co., Ltd. Voltage conversion circuit with stable transition delay characteristic
JP4656040B2 (ja) * 2006-10-19 2011-03-23 株式会社デンソー 電子回路
US7808294B1 (en) * 2007-10-15 2010-10-05 Netlogic Microsystems, Inc. Level shifter with balanced rise and fall times
CN201323565Y (zh) * 2008-11-30 2009-10-07 中兴通讯股份有限公司 时钟信号电平转换电路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018063712A1 (en) * 2016-09-27 2018-04-05 Intel Corporation Fused voltage level shifting latch
US10756736B2 (en) 2016-09-27 2020-08-25 Intel Corporation Fused voltage level shifting latch
US11588485B2 (en) 2020-12-15 2023-02-21 SK Hynix Inc. Power domain change circuit and operating method thereof
US11855628B2 (en) 2020-12-15 2023-12-26 SK Hynix Inc. Power domain change circuit and operating method thereof

Also Published As

Publication number Publication date
JP2012105277A (ja) 2012-05-31
CN102545874A (zh) 2012-07-04

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20110118

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid