KR20110129254A - Three dimensional semiconductor memory device - Google Patents

Abstract

PURPOSE: A three-dimensional semiconductor memory apparatus is provided to arrange memory cells and selection transistors in different levels from each other, thereby highly integrating the three-dimensional semiconductor memory apparatus. CONSTITUTION: A three-dimensional semiconductor memory apparatus comprises a memory structure and a control structure laminated on a substrate. The control structure is laminated on the substrate. The memory structure comprises a plurality of successively laminated word lines(WL1-WL6) and a semiconductor pattern. The semiconductor pattern faces sidewalls of the word lines while crossing the word lines. The control structure comprises a string which respectively touches both ends of the semiconductor pattern and ground-selection transistors(SST,GST). A detection amplifier(40) is integrated on the substrate and arranged between the substrate and memory structure.

Description

Three dimensional semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a three-dimensional structure.

There is a demand for increasing the integration of semiconductor devices in order to meet the high performance and low price demanded by consumers. In the case of semiconductor memory devices, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of the conventional two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by the area occupied by the unit memory cell, it is greatly influenced by the level of the fine pattern formation technique. However, since expensive equipment is required for pattern miniaturization, the degree of integration of a two-dimensional semiconductor memory device is increasing but is still limited.

In order to overcome this limitation, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, for mass production of 3D semiconductor memory devices, a process technology capable of realizing reliable product characteristics while reducing manufacturing cost per bit than that of 2D semiconductor memory devices is required.

An object of the present invention is to provide a three-dimensional semiconductor memory device that can be easily integrated.

The problem to be solved by the present invention is not limited to the above-mentioned problem, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a control structure and at least one memory structure sequentially stacked on a substrate, the memory structure is a plurality of words stacked in sequence And at least one semiconductor pattern opposite the sidewalls of the wordlines across the lines and the wordlines, and the control structure includes string and ground select transistors that respectively connect both ends of the semiconductor pattern.

In order to achieve the above object, a 3D semiconductor memory device according to another embodiment of the present invention includes a plurality of cell strings, each of which uses a plurality of word lines stacked in turn as a gate electrode. A memory structure including a plurality of MOS-field effect transistors, a ground select transistor connected in series at one end of the memory structure, and a string select transistor connected in series at the other end of the memory structure, wherein the memory structure is disposed in the memory region, Ground and string select transistors are disposed in a non-memory region of a different height than the memory region.

According to the three-dimensional semiconductor memory device of the present invention, in a cell string including three-dimensionally stacked memory cells and select transistors, the three-dimensional semiconductor memory device can be more highly integrated by disposing the memory cells and the select transistors at different levels. have.

In addition, non-memory circuits such as a sense amplifier and a word line driver may be disposed under the memory cells to further increase integration of the 3D semiconductor memory device.

1 is a block diagram of a 3D semiconductor memory device according to an embodiment of the present invention.
2 is a circuit diagram of a cell array of a 3D semiconductor memory device according to an embodiment of the present invention.
3 is a perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the present invention, and shows a cross section of FIG. 3.
5 is a cross-sectional view of a three-dimensional semiconductor memory device for explaining a modification of the present invention.
6 is a perspective view illustrating a portion of a cell array according to an embodiment of the present invention.
7 is a cross-sectional view illustrating an information storage pattern according to an embodiment of the present invention.
8 to 12 are diagrams for describing an arrangement structure of non-memory circuits in a 3D semiconductor memory device according to an embodiment of the present invention.
13 is a perspective view illustrating a 3D semiconductor memory device according to another exemplary embodiment of the present invention.
14 and 15 are views for explaining an arrangement structure of a wiring structure that connects a word line and a word line driver in another embodiment of the present invention.
16 and 17 are perspective views illustrating a structure of contact portions of word lines according to another exemplary embodiment of the present invention.
18 to 23 are diagrams for describing an arrangement structure of non-memory circuits in a 3D semiconductor memory device according to another exemplary embodiment.
24 is a cross-sectional view of a three-dimensional semiconductor device according to still another embodiment of the present invention.
25 is a schematic block diagram illustrating an example of a memory system including a 3D semiconductor memory device according to example embodiments.
FIG. 26 is a schematic block diagram illustrating an example of a memory card including a 3D semiconductor memory device according to example embodiments. FIG.
27 is a schematic block diagram illustrating an example of an information processing system having a three-dimensional semiconductor memory device according to the present invention.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

1 is a block diagram of a 3D semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a 3D semiconductor memory device includes a memory cell array 10, a row decoder 20, a page buffer 30, and a column decoder 40.

The memory cell array 10 may store data including a plurality of word lines, bit lines, and memory cells. In addition, the predetermined number of memory cells may configure the memory blocks BLK0 to BLKn, which are data erasing units. The memory cell array 10 will be described in detail with reference to FIG. 2.

The row decoder 20 selects memory blocks BLK0 to BLKn of the memory cell array and selects word lines of the selected memory block according to the address information.

The word line driver 30 drives the word lines selected by the row decoder 20 to a program voltage or a pass voltage. For example, the word line driver 30 drives a word line connected to a selected memory cell at a program voltage and a word line connected to an unselected memory cell at a pass voltage.

The sense amplifier 40 senses and amplifies the amount of current in the selected bit line in the read operation mode. Although not shown in the drawing, the sense amplifier 40 may include page buffers respectively connected to bit lines or connected to bit line pairs, respectively.

The column decoder 50 may provide a data transfer path between the page buffers and an external device (eg, a memory controller).

2 is a circuit diagram of a cell array of a 3D semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, a structure of a cell array according to embodiments of the present invention will be briefly described. A cell array includes a plurality of cell strings STR, and each cell string STR is a bit line. BL, a common source electrode CSL, and a plurality of unit memory cells UC connected in series therebetween. In addition, the cell string STR includes a string select transistor SST between the bit line BL and the unit memory cell UC, and a ground select transistor GST between the common source electrode CSL and the unit memory cell UC. ).

3 to 7 will be described in detail the structure of the cell array according to the embodiments of the present invention.

3 is a perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the present invention, and shows an x-z cross section of FIG. 3.

3 and 4, the 3D semiconductor memory device includes a non-memory layer L1 and a memory layer L2 stacked vertically, and the memory layer L2 is non-memory. It may be disposed on the memory layer L1.

The non-memory layer L1 includes a semiconductor substrate 100, a string constituting the cell string STR, ground select transistors SST and GST, and non-memory circuits. The memory layer L2 includes a cell array region CAR and a word line contact region (not shown), and the cell array region CAR includes unit memory cells connected in series with strings and ground select transistors SST and GST. (UC of FIG. 2). The unit memory cells (UC of FIG. 2) are three-dimensionally disposed on the insulating layer 200. In addition, the unit memory cells (UC of FIG. 2) are electrically connected to the selection transistors SST and GST disposed below them to form a cell string (STR of FIG. 2). The word line contact region is described in more detail with reference to FIGS. 13 to 17.

In more detail with respect to the non-memory layer L1, the semiconductor substrate 100 may be a single crystal semiconductor having a first conductivity type (eg, a p-type silicon wafer). The semiconductor substrate 100 may include a region (that is, a well region) electrically separated by impurity regions of another conductivity type. A plurality of well regions may be formed in one semiconductor substrate 100, and the well regions may be formed of a pocket well structure or a triple well structure. In addition, the device isolation layer 105 may be formed on the semiconductor substrate 100 to define electrical devices.

The string select transistor SST using the string select line SSL as the gate electrode and the ground select transistor GST using the ground select line GSL as the gate electrode are disposed to be spaced apart from each other on the semiconductor substrate 100. . The ground select transistors GST and the string select transistors SST may be metal-oxide-semiconductor field-effect transistors (MOSFETs) using the semiconductor substrate 100 as a channel region. . Accordingly, the source and drain electrodes of the select transistors SST and GST are used in the semiconductor substrate 100 on both sides of the ground select line GSL and in the semiconductor substrate 100 on both sides of the string select transistor SST. Impurity regions 110 may be formed. In example embodiments, the impurity regions 110 may be formed to have a different conductivity type from that of the semiconductor substrate 100. In addition, the source electrodes of the ground select transistors GST may be commonly connected to a common source line CSL parallel to the word line WL, and each of the drain electrodes of the ground select transistors GST may be a memory layer. One end of each of the semiconductor patterns 265 of L2 may be connected. In addition, the drain electrodes of the string select transistors SST are connected to the bit lines BL having long axes in a direction crossing the word line WL, and the source electrodes of the string select transistors SST are connected to a semiconductor pattern ( 265 can be connected to the other end.

In example embodiments, the ground select transistors SST and GST may be disposed under the semiconductor pattern 265 and the word line structures 300. In addition, the bit line BL and the common source line CSL may be disposed under the semiconductor pattern 265 and the word line structures 300. That is, since the selection transistors SST and GST are disposed under the cell array region CAR, the horizontal area occupied by the selection transistors SST and GST may be reduced. Therefore, the three-dimensional semiconductor memory device can be more integrated.

In addition, in the non-memory layer L1, non-memory circuits may be integrated on the semiconductor substrate 100. The non-memory circuit may include the row and column decoders 20 and 50, the word line driver 30, and the sense amplifier 40 described in FIG. 1. In addition, the non-memory circuit may include a high voltage generation circuit, a level shifter, a read verify circuit, an input / output interface circuit, and the like.

According to an embodiment, the non-memory circuit may be integrated on the semiconductor substrate 100 between the string select transistor SST and the ground select transistor GST. For example, sense amplifiers 40 connected to the bit line BL may be disposed on the semiconductor substrate 100 between the string select transistor SST and the ground select transistor GST. The sense amplifier 40 may include n-type and p-type MOSFETs using the semiconductor substrate 100 as a channel region. In addition, the sensor amplifier 40 may be disposed under the semiconductor pattern 265 and the word line structures 300. That is, the sense amplifier 40 is disposed in the horizontal area occupied by the cell array region CAR. An arrangement structure of non-memory circuits in the non-memory layer L1 will be described in more detail with reference to FIGS. 8 through 12.

In example embodiments, the non-memory circuits disposed in the non-memory layer L1 may be covered by the insulating layer 200. The insulating layer 200 may include a boron-phosphor silicate glass (BPSG) film, an HDP (High Density Plasma) oxide film, a Tetra Ethyl Ortho Silicate (TEOS) film, an Undoped Silicate Glass (USG), or TOSZ having excellent gap fill characteristics. (Tonen SilaZene) material. According to another embodiment, a semiconductor layer or a semiconductor substrate may be disposed on the insulating layer 200. In addition, although one insulating layer 200 is illustrated in the drawing, wires having a multi-layer structure may be formed between the semiconductor substrate 100 and the insulating layer 200, and thus a plurality of interlayer insulating layers may be stacked.

A plurality of unit memory cells (UC of FIG. 2) may be formed on the insulating layer 200 of the memory layer L2. In detail, at least one word line structure 300 and at least one semiconductor pattern 265 are disposed on the insulating layer 200. An information storage pattern 255 is disposed between the word line structure 300 and the semiconductor pattern 265. The word line structure 300 includes a plurality of word lines WL1 to WL6 stacked as described with reference to FIGS. 6 and 7. The memory cells three-dimensionally arranged on the insulating layer 200 may be MOS field effect transistors using word lines WL1 to WL6 as gate electrodes and a semiconductor pattern 265 as a channel. .

According to an embodiment, the semiconductor pattern 265 may be disposed across the plurality of word line structures 300. That is, as illustrated, the semiconductor pattern 265 may extend from one side of the word line structure 300 and be connected to another semiconductor pattern 265 disposed on the other side of the word line structure 300. In this case, the semiconductor pattern 265 may also be disposed on the top surface of the word line structure 300. In addition, the upper surfaces of the insulating layers 200 between the word line structures 300 may be connected to each other. That is, as illustrated, the semiconductor patterns 265 may be formed in a line shape covering the side and top surfaces of the word line structures 300 while crossing the plurality of word line structures 300.

In addition, an impurity region may be formed at both ends of the semiconductor pattern 265 crossing the plurality of word line structures 300 for electrical connection with the selection transistors SST and GST. In addition, the impurity region may be formed in the semiconductor pattern 265 between the word line structures 300, so that an electric path crossing the word line structures 300 may be formed during a program and read operation of the memory device. In addition, one end of the semiconductor pattern 265 may be disposed above the source electrode of the string select transistor SST, and the other end may be disposed above the drain electrode of the ground select transistor GST.

In example embodiments, the semiconductor pattern 265 may be electrically connected to the select transistors SST and GST disposed in the non-memory layer L1 through the string connection structure 150 passing through the insulating layer 200. have. The string connection structure 150 may be directly connected to one end of the semiconductor pattern 265 doped with impurities and the source electrode of the string select transistor SST. The string connection structure 150 may be directly connected to the other end of the semiconductor pattern 265 doped with impurities and the drain electrode of the ground select transistor GST. The string connection structure 150 may include at least one of doped semiconductors, metals, metal nitrides, and metal silicides. A current path may be formed between the bit line BL and the common source line CSL by the semiconductor pattern 265 crossing the string connection structure 150 and the plurality of word line structures 300. The string connection structure 150 may be formed before forming the word line structures 300. In this case, the string connection structure 150 may be in direct contact with the bottom surface of the semiconductor pattern 265. According to another embodiment, the string connection structure 150 may be formed after forming the word line structures 300 and the semiconductor patterns 265. In this case, the string connection structure 150 may pass through the semiconductor patterns 265.

5 is a cross-sectional view of a three-dimensional semiconductor memory device according to a modification of the present invention.

Referring to FIG. 5, the area of the cell array region CAR may vary depending on the number of word line structures 300 and the length of the semiconductor pattern 265. When the number of word line structures 300 constituting the cell string STR of FIG. 2 is small, the area of the cell array region CAR may be reduced. Accordingly, the cell array region CAR may be disposed between the string and the ground select transistors SST and GST in plan view. That is, the common source line CSL and the bit line BL may not be disposed under the word line structures 300.

6 and 7, the structure of the unit memory cells (UC of FIG. 2) disposed three-dimensionally on the insulating layer 200 will be described in more detail. 6 is a perspective view illustrating a portion of a cell array according to an embodiment of the present invention. 7 is a cross-sectional view illustrating an information storage pattern according to an embodiment of the present invention.

Referring to FIG. 6, a word line structure 300 is disposed on the insulating layer 200. The word line structure 300 includes insulating film patterns 231, 232, 233, 234, 235, 236, and 237 and word lines WL1, WL2, WL3, WL4, WL5, and WL6, which are sequentially and repeatedly stacked. can do. The word line structure 300 may be formed to have a long axis parallel to the ground select line GSL and the string select line SSL. The word lines WL1 to WL6 may be at least one of the conductive materials. For example, the word lines WL1 to WL6 may include at least one of doped semiconductors, metals, metal nitrides, and metal silicides.

At least one semiconductor pattern 265 may be disposed on sidewalls of the word line structure 300, and an information storage pattern 255 may be disposed between the semiconductor pattern 265 and the word line structure 300. The semiconductor pattern 265 may be a single crystal semiconductor or a polycrystalline semiconductor. According to an embodiment, the semiconductor pattern 265 may be an intrinsic semiconductor.

According to an aspect of the present invention, the word lines WL1 to WL6 may control electrical connection of the unit memory cells by controlling the potential of the semiconductor pattern 265. More specifically, the semiconductor pattern 265 may be capacitively coupled to the word lines WL1 to WL6 to form a MOS capacitor. In this case, the voltage applied to the word lines WL1 to WL6 can variably control the potential of the semiconductor pattern 265 adjacent thereto, and the energy band of the semiconductor pattern 265 is applied to the word lines WL1 to WL6. It may be inverted depending on the voltage applied. Therefore, the electrical connection of the unit memory cells may be controlled by voltages applied to the word lines WL1 to WL6 constituting the word line structure 300.

On the other hand, such electrical connection is possible when regions inverted in the side of each of the word lines WL1 to WL6 overlap each other. The interlayer insulating layers 231 to 237 between the word lines WL1 to WL6 may be formed to have a thickness smaller than twice the maximum width of the inverted region to allow the inversion regions to overlap each other. The interlayer insulating films 231 to 237 may be at least one of insulating materials, and may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. However, since the uppermost interlayer insulating layer 237 may be used as an etching mask in a subsequent patterning process, the upper interlayer insulating layer 237 may be formed to have a thickness thicker than those of other interlayer insulating layers 231 to 237.

According to an aspect of the present invention, the information storage pattern 255, together with the semiconductor pattern 265 and the word lines WL1 to WL6, may be used as a capacitor dielectric film constituting a MOS capacitor. To this end, the information storage pattern 255 includes at least one of insulating materials.

According to another aspect of the present invention, the information storage pattern 255 may form a MOS transistor together with the semiconductor pattern 265 and the word lines WL1 to WL6. In this case, the semiconductor pattern 265 is used as a channel region, the word lines WL1 to WL6 are used as gate electrodes, and the information storage pattern 255 is used as a gate insulating film. In this case, a portion of the semiconductor pattern 265 on the side of the information storage pattern 255 is inverted by the voltage applied to the word lines WL1 to WL6, and thus may be used as source / drain electrodes of the MOS transistor. In addition, since the semiconductor pattern 265 is disposed on the sidewalls of the word lines WL1 to WL6, the current direction of the MOS transistor using this as the channel region is perpendicular to the upper surface of the insulating layer.

The information storage pattern 255 may include an insulating material, and may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film. In this case, the high dielectric film refers to insulating materials having a dielectric constant higher than that of silicon oxide film, and include tantalum oxide film, titanium oxide film, hafnium oxide film, zirconium oxide film, aluminum oxide film, yttrium oxide film, niobium oxide film, cesium oxide film, indium oxide film, iridium oxide film, and BST. Film and PZT film. The information storage pattern 255 will be described in more detail with reference to FIG. 7.

Referring to FIG. 7, the information storage pattern 255 may include a tunnel insulating film 255a adjacent to the semiconductor pattern 265, a blocking insulating film 255c adjacent to the word line structure 300, and a tunnel insulating film 255a and a blocking insulating film. The charge storage layer 255b may be interposed between 255c. In this case, the blocking insulating layer 255c may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film. According to an embodiment, the blocking insulating film 255c may be a multilayer thin film including a high dielectric film. The tunnel insulating film 255a may be formed of a material having a lower dielectric constant than the blocking insulating film 255c, and the charge storage film 255b may be an insulating thin film (eg, silicon nitride film) rich in charge trap sites, or conductive particles. It may be an insulating thin film including the. In example embodiments, the tunnel insulation layer 255a may be a silicon oxide layer, the charge storage layer 255b may be a silicon nitride layer, and the blocking insulation layer 255c may be an insulation layer including an aluminum oxide layer. In this case, the word lines WL1 to WL6 may include tantalum nitride layers.

8 to 12 are diagrams for describing an arrangement structure of non-memory circuits in a 3D semiconductor memory device according to an embodiment of the present invention.

8 to 12,

The semiconductor substrate 100 includes at least one memory region MR and a peripheral region PR surrounding the memory region MR. The string and ground select transistors SST and GST may be integrated in the semiconductor substrate 100 of the memory region MR, and the non-memory circuits may be formed in the semiconductor substrate 100 of the peripheral region PR. Can be integrated into the device. As described above, the non-memory layer L1 may include row and column decoders 20 and 50, a word line driver 30, a sense amplifier 40, a control circuit 60, and the like. 8 through 12, the string select transistor SST and the ground select transistor GST connected to the memory cells of the cell array region CAR may be spaced apart from each other on the semiconductor substrate 100.

According to the embodiment illustrated in FIG. 8, sense amplifiers 40 and a column decoder 50 connected to the bit line BL may be disposed between the string select transistor SST and the ground select transistor GST. . In addition, the selection transistors SST and GST, the sense amplifiers 40, and the column decoder 50 may be disposed in the memory region MR under the cell array region CAR. The cell array region CAR includes unit memory cells three-dimensionally arranged as described with reference to FIG. 3. According to another embodiment, the row decoder 20, the word line driver 30, and the control circuit 60 may be disposed under the cell array region CAR.

According to the embodiment illustrated in FIG. 9, the cell array region CAR may be disposed between the string select transistor SST and the ground select transistor GST in plan view. Also, the non-memory circuits 20, 30, 40, 50, and 60 may be disposed around the cell array region CAR. According to another embodiment, the cell array region CAR is planarly disposed between the string select transistor SST and the ground select transistor GST, and the sense amplifiers 40 and the column decoder below the cell array region CAR. 50 may be disposed. The string select transistor SST and the ground select transistor GST may be disposed over the memory region MR and the peripheral region PR.

In addition, according to the exemplary embodiment illustrated in FIGS. 10 and 11, at least two memory regions MR may be arranged in the x-axis direction of the semiconductor substrate 100. Likewise, at least two cell array regions CAR may be arranged in the x-axis direction. Each cell array region CAR may be disposed above the memory region MR. 10 and 11, adjacent cell array regions CAR may share sense amplifiers 40 and column decoder 50. That is, the sense amplifiers 40 and the column decoder 50 may be disposed on the semiconductor substrate 100 between adjacent memory regions MR, that is, between adjacent string select transistors SST. Also, referring to FIG. 10, each cell array region CAR may be disposed between the string and the ground select transistors SST and GST in a planar manner. The string and ground select transistors SST and GST may extend from the memory region MR to the peripheral region PR. As illustrated in FIG. 11, string and ground select transistors SST and GST spaced apart from each other may be disposed in each memory region MR.

In addition, according to the exemplary embodiment shown in FIG. 12, at least two or more memory regions MR may be arranged in the x-axis and y-axis directions, and the semiconductor substrate 100 may be disposed on each of the memory regions MR. Cell array regions CAR may be disposed. That is, at least two memory regions MR may be arranged in the x-axis and y-axis directions. Each cell array region CAR may be disposed between the string and the ground select transistors SST and GST in a planar manner. In addition, as described with reference to FIGS. 9 and 10, string and ground select transistors SST and GST may be disposed under each cell array region CAR. According to this embodiment, the cell array regions CAR adjacent in the x-axis direction may share the sense amplifier 40 and the column decoder 50. In addition, the cell array regions CAR adjacent in the y-axis direction may share the row decoder 20 and the word line driver 30. That is, the row decoder 20 and the word line driver 30 may be disposed between the cell array regions CAR adjacent in the y-axis direction.

The arrangement structure of the non-memory circuits in the non-memory layer L1 is not limited to the embodiments shown in FIGS. 8 to 12, and may be variously modified.

13 is a perspective view illustrating a 3D semiconductor memory device according to another exemplary embodiment of the present invention. 14 and 15 are views for explaining an arrangement structure of a wiring structure that connects a word line and a word line driver in another embodiment of the present invention.

Referring to FIG. 13, as described in an embodiment, a 3D semiconductor memory device includes a non-memory region L1 and a memory region L2 stacked vertically, and includes a memory layer ( L2) may be disposed on the non-memory layer L1. The non-memory layer L1 includes the semiconductor substrate 100, a string constituting the cell string STR, ground select transistors SST and GST, and non-memory circuits. The memory layer L2 includes unit memory cells (UC of FIG. 2) connected in series with the insulating layer 200 and the string and ground select transistors SST and GST. The unit memory cells (UC of FIG. 2) are three-dimensionally disposed on the insulating layer 200. The unit memory cells UC of FIG. 2 are electrically connected to the selection transistors SST and GST of the non-memory layer L2 to form a cell string STR of FIG. 2.

According to this embodiment, as shown in FIGS. 13 to 15, the memory layer L2 includes first and second word line contact regions WCTR1 and WCTR2 and a cell array region CAR therebetween. do.

13 to 15, the top surface of the insulating layer 200 in the cell array region CAR is formed to be lower than the top surfaces of the first and second word line contact regions WCTR1 and WCTR2. According to an embodiment, the structure may be formed through a patterning step of recessing the insulating layer 200 in the cell array region CAR. The insulating layer 200 formed as described above may have a recess 210 in the cell array region CAR and a protrusion 220 in the first and second word line contact regions WCTR1 and WCTR2. . The sidewalls of the protrusion 220 formed through the patterning step may have a predetermined inclination (angle of about 90 degrees to about 130 degrees) with respect to the semiconductor substrate 100. According to another exemplary embodiment, the structure may include forming a predetermined thin film having a thickness corresponding to a step between the two layers of the insulating layer 200, and then etching the thin film in the cell array region CAR. It may be formed.

The word line structure 300 in which the interlayer insulating layers 231 to 237 and the plurality of word lines WL1 to WL6 are alternately stacked is disposed in the recess 210 of the insulating layer 200. The word line structure 300 may be conformally formed in the recess 210 of the insulating layer 200. The total thickness of the word line structure 300 in the cell array region CAR may be smaller than the step between the recess 210 and the protrusion 220.

In more detail, each of the word lines WL1 to WL6 may include a wiring unit disposed in the cell array region CAR in parallel with the semiconductor substrate 100, and first and second word line contact regions WCTR1 and WCTR2. And a contact portion inclined with respect to the semiconductor substrate 100.

The wiring portions of the word lines WL1 to WL6 may be shorter as the distance from the surface of the insulating layer 200 increases. The spacing of the wiring portions of the word lines WL1 to WL6 is determined by the thicknesses of the interlayer insulating layers 231 to 237. The thicknesses of the interlayer insulating films 231 to 237 may be selected in a range that satisfies technical characteristics for overlap of inversion regions described in FIG. 5. However, since the uppermost insulating layer 237 may be used as an etching mask in a subsequent patterning process, the uppermost insulating layer 237 may be formed to have a thicker thickness than the other insulating layers 231 to 236.

In addition, as the wiring portions of the word lines WL1 to WL6 are farther from the surface of the insulating layer 200, the contact portions of the word lines WL1 to WL6 are protruding portions 220 of the insulating layer 200. Away from you. The contact portions of the word lines WL1 ˜ WL6 may be shorter as the contact portions are separated from the sidewall of the protrusion 220 of the insulating layer 200.

According to this embodiment, as described with reference to FIG. 3, the semiconductor patterns 265 disposed in the memory layer L2 are selected transistors SST and GST of the non-memory layer L1 through the string connection structure 150. ) Is electrically connected. In addition, as described with reference to FIGS. 7 to 9, the string select transistor SST and the ground select transistor GST may be disposed to be spaced apart from each other in the non-memory layer L1. The sense amplifier 40 and the column decoder 50 may be disposed on the semiconductor substrate 100 between the selection transistors SST and GST in the non-memory layer L1.

According to this embodiment, a word line driver 30, which is a non-memory circuit, may be disposed under the first and second word line contact regions WCTR1 and WCTR2. An arrangement structure of the non-memory circuits in the non-memory layer L1 will be described in more detail with reference to FIGS. 18 through 23.

13 to 15, the word line driver 30 of the non-memory layer L1 contacts the word lines WL1 to WL6 of the memory layer L2 through the word line connection structure 350. Can be connected to the unit. The word line connection structure 350 includes first and second contact plugs CTP1 and CTP2 and wires ICL. The first contact plug CTP1 may be directly connected to the contact portion of the word line, and the second contact plug CTP2 may be connected to the word line driver 30 of the non-memory layer L2. The first and second contact plugs CTP1 and CTP2 may be electrically connected to each other through the wiring ICL. The second contact plugs CTP2 connected to the wordline driver 30 may pass through the insulating layer 200. In addition, the second contact plugs CTP2 may be formed between the word line structures 300, as shown in FIGS. 14 and 15. According to another embodiment, the second contact plugs CTP2 may be connected to the word line driver 30 through the protrusion 220 of the insulating layer 200.

Meanwhile, in the first and second word line contact regions WCTR1 and WCTR2, the spacing between the contact portions of the word lines WL1 to WL6 is determined by the spacing between the wiring portions, so that the contact portions may be disposed adjacent to each other. Can be. Accordingly, the process margin may be reduced in forming the contact plugs CTP1 and CTP2 connected to the respective word lines WL1 to WL6. Accordingly, as shown in FIGS. 14 and 15, the first contact plugs CTP1 connected to the word lines WL1, WL3, and WL5 disposed in the odd layer are disposed in the first wordline contact region WCTR1. Is placed. In addition, first contact plugs CTP1 connected to word lines WL2, WL4, and WL6 disposed on even-numbered layers may be disposed in the second wordline contact region WCTR2.

16 and 17 are perspective views illustrating a structure of contact portions of word lines according to another exemplary embodiment of the present invention.

16 and 17, in the first word line contact region CTR1, upper surfaces of the contact portions of the word lines WL2, WL4, and WL6 disposed on even-numbered layers may have a structure filled with a dummy insulating pattern. Can be. Correspondingly, in the second word line contact region CTR2, upper surfaces of the contact portions of the word lines WL1, WL3, and WL5 disposed in the odd layer may be filled with a dummy insulating pattern. In other words, the top surfaces of the contact portions of the word lines WL2, WL4, and WL6 disposed in the even layers in the first word line contact region CTR1 may be formed in the word lines WL1, WL3, and WL5 disposed in the odd layer. It may be disposed below the upper surface of the contact portion. Correspondingly, in the second word line contact region CTR2, the upper surfaces of the contact portions of the word lines WL1, WL3, and WL5 disposed in the odd layer are the word lines WL2, WL4, and WL6 disposed in the even layer. It may be disposed below the upper surface of the contact portions of the. That is, the contact portion of the word line is disposed in the first and second word line contact regions CTR1 and CTR2, and the length extending from the wiring portion of the word line has the first and second word line contact regions CTR1 and CTR2. ) May differ from each other.

In addition, the angle between the contact portion and the wiring portion of the word lines WL1 to WL6 may be equal to the angle formed between the cell array region CAR and the boundary lines between the word line contact regions WCTR1 and WCTR2 with the upper surface of the substrate 100. May be substantially the same. For example, as shown in FIG. 11, when the interface between the cell array region CAR and the word line contact regions WCTR1 and WCTR2 is perpendicular to the upper surface of the semiconductor substrate 100, the word lines WL1 to WL6. The contact portions of) are also formed perpendicular to the upper surface of the semiconductor substrate 100.

Further, according to another embodiment, as shown in FIG. 17, at the protrusion 220 of the insulating layer 200. Sidewalls adjacent to the cell array region CAR may have an angle smaller than 90 degrees with respect to the upper surface of the semiconductor substrate 100. In this case, the area of the upper surfaces of the word lines WL1 to WL6 exposed by the above-described planarization etching is increased as compared with the previous embodiment. Specifically, if the angle of the sidewall with respect to the top surface of the semiconductor substrate 100 is θ, and the thickness and width of the word line are a and b, respectively, the exposed area of such word line is ab for the preceding embodiments, and this embodiment For example, ab / sinθ. Therefore, as the angle decreases, the exposed area of the word lines WL1 to WL6 increases. According to one embodiment, the angle may be between 30 degrees and 90 degrees.

18 to 23 are diagrams for describing an arrangement structure of non-memory circuits in a 3D semiconductor memory device according to another exemplary embodiment.

18 to 23, the semiconductor substrate 100 may include at least one memory region MR and a peripheral region PR surrounding the memory region MR. The string and ground select transistors SST and GST may be integrated in the semiconductor substrate 100 in the memory region MR, and the non-memory circuits may be integrated in the semiconductor substrate 100 in the peripheral region PR. As described with reference to FIGS. 8 through 12, the string and ground select transistors SST and GST and the non-memory circuits 20 and 30 are connected to the memory cells of the cell array region CAR in the non-memory layer L1. 40. 50. 60) may be arranged. In addition, as described with reference to FIGS. 13 to 15, the memory layer L2 on the non-memory layer L1 may include the first and second word line contact regions WCTR1 and WCTR2 and a cell array region therebetween. CAR).

18 and 19, the string and ground select transistors SST and GST spaced apart from each other may be disposed in the memory region MR of the semiconductor substrate 100 as described with reference to FIG. 8. Can be. According to an embodiment, as illustrated in FIG. 18, the sense amplifier 40 and the column decoder 50 may be disposed between the string and ground select transistors SST and GST. According to another embodiment, as shown in FIG. 19, the cell array region CAR may be disposed between the string and the ground select transistors SST and GST in plan view. In addition, according to an embodiment, a word line driver 30 may be disposed under the first word line contact region WCTR1. According to another embodiment, the word line driver 30 and the row decoder 20 may be disposed under the first word line contact region WCTR1.

In addition, according to the exemplary embodiment illustrated in FIG. 20, as described with reference to FIG. 10, at least two memory regions MR may be arranged in the x-axis direction. The string and ground select transistors SST and GST spaced apart from each other are disposed in the memory regions MR, or the string and ground select transistors SST and GST are planarized in the respective memory regions MR. ) May be arranged. In addition, adjacent cell array regions CAR may share the sense amplifiers 40 and the column decoder 50. In addition, the word line driver 30 may be disposed under the first word line contact region WCTR1 adjacent to each of the cell array regions CAR.

According to the embodiment illustrated in FIG. 21, as described with reference to FIG. 12, at least two or more memory regions MR may be arranged in the x-axis and y-axis directions. The string and ground select transistors SST and GST spaced apart from each other are disposed in the memory regions MR, or the cell array regions CAR are planarized in the string and ground select transistors SST, respectively. GST). In addition, according to this embodiment, the cell array regions CAR adjacent in the x-axis direction may share the sense amplifier 40 and the column decoder 50. In addition, the cell array regions CAR adjacent in the y-axis direction may share the row decoder 20 and the word line driver 30. In addition, according to an embodiment, the word line driver 30 may be disposed under the first word line contact region WCTR1, and the row decoder 20 may be disposed under the second word line contact region WCTR2. . According to another exemplary embodiment, the row decoder 20 and the word line driver 30 may be disposed under the first word line contact region WCTR1.

In addition, according to the embodiment shown in FIG. 22, as described with reference to FIGS. 14 and 15, Word line connection structures 350 may be disposed in the first word line contact region WCTR1 to connect the word lines WL1, WL3, and WL5 disposed in the odd layer. In addition, word line connection structures 350 may be disposed in the second word line contact region WCTR2 to connect the word lines WL2, WL4, and WL6 disposed in the even layer. Accordingly, the non-memory layer L1 includes an odd word line driver 30a for driving the word lines WL1, WL3, and WL5 disposed in the odd layer, and the word lines disposed in the even layer. An even word line driver 30b for driving the WL2, WL4, and WL6 may be included. Odd and even word line drivers 30a and 30b may be disposed in the memory region MR or the peripheral region of the semiconductor substrate 100. The odd word line driver 30a and the even word line driver 30b may be spaced apart from each other in the y-axis direction perpendicular to the x-axis that is the array direction of the selection transistors SST and GST. The odd word line driver 30a may be disposed under the first word line contact region WCTR1, and the even word line driver 30b may be disposed under the second word line contact region WCTR2.

According to the embodiment illustrated in FIG. 23, at least two cell array regions CAR may be arranged in the x-axis direction. Each of the first word line contact region WCTR1 and the second word line contact region WCTR2 may be disposed on both sides of each cell array region CAR. Also, The row decoder 20 may be disposed between the adjacent odd wordline driver 30a and the even wordline driver 30b. In this case, adjacent cell array regions CAR may share the row decoder 20.

The arrangement structure of the non-memory circuits in the non-memory layer L1 is not limited thereto and may be variously modified.

24 is a cross-sectional view of a three-dimensional semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 24, some of the non-memory circuits may be disposed above the memory cells. According to this embodiment, the three-dimensional semiconductor device may include a first non-memory layer L1, a memory layer L2, and a second non-memory layer L3 that are sequentially stacked. That is, three-dimensionally arranged memory cells may be disposed between vertically arranged non-memory circuits.

In detail, as described with reference to FIG. 13, the semiconductor pattern 265 disposed in the cell array region CAR in the memory layer L2 is formed through the string connection structure 150 of the first non-memory layer L1. It is electrically connected to the selection transistors SST and GST. In addition, a sense amplifier 40 of FIG. 1 may be disposed on the semiconductor substrate 100 between the selection transistors SST and GST. That is, the sense amplifier 40 of FIG. 1 may be disposed under the recess 210 of the insulating layer 200.

In addition, according to this embodiment, the word line driver 30 connected to the word lines WL1 to WL6 may be formed on the protrusion 220 of the insulating layer 200. The word line driver 30 may include a MOS-pet consisting of a gate electrode formed on the protrusion 220 of the insulating layer 200 and a source / drain electrode formed in the protrusion 220. To this end, the protrusion 220 may be formed of a semiconductor material or may include a semiconductor layer on the protrusion 220. The word line driver 30 on the protrusion 220 may be connected to the word lines WL1 ˜ WL6 through a word line connection structure 350 formed on the insulating layer 200.

25 is a schematic block diagram illustrating an example of a memory system including a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 25, the memory system 1100 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, It can be applied to a memory card or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions performed by the controller. The input / output device 1120 may receive data or a signal from the outside of the system 1100 or output data or a signal to the outside of the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

The memory 1130 includes a nonvolatile memory device according to embodiments of the present invention. The memory 1130 may also further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The interface 1140 transmits data to the communication network or receives data from the network.

FIG. 26 is a schematic block diagram illustrating an example of a memory card including a 3D semiconductor memory device according to example embodiments. FIG.

Referring to FIG. 26, a memory card 1200 for supporting a high capacity of data storage capability includes a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

SRAM 1221 is used as an operating memory of the processing unit 1222. The host interface 1223 includes a data exchange protocol of a host that is connected to the memory card 1200. The error correction block 1224 detects and corrects an error included in data read from the multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for exchanging data of the memory controller 1220. Although not shown in the drawings, the memory card 1200 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host. Self-explanatory to those who have learned.

27 is a schematic block diagram illustrating an example of an information processing system having a three-dimensional semiconductor memory device according to the present invention.

Referring to FIG. 27, the flash memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to a system bus 1360, respectively. It includes. The flash memory system 1310 may be configured substantially the same as the above-described memory system or flash memory system. The flash memory system 1310 stores data processed by the CPU 1330 or data externally input. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.

In addition, the flash memory device or the memory system according to the present invention may be mounted in various types of packages. For example, a flash memory device or a memory system according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged and mounted in the same manner as Level Processed Stack Package (WSP).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims (10)

A control structure and at least one memory structure stacked on a substrate,
The memory structure includes a plurality of wordlines stacked in turn and at least one semiconductor pattern opposite the sidewalls of the wordlines across the wordlines,
And the control structure includes a string and ground select transistors respectively connected to both ends of the semiconductor pattern. The method of claim 1,
The substrate includes at least one memory region and a peripheral region surrounding the memory region,
And the control structure is integrated on at least the substrate in the memory region. The method of claim 2,
Further comprising a sense amplifier integrated on the substrate and formed between the substrate and the memory structure,
And the sense amplifier is integrated in a substrate of the memory region and the peripheral region adjacent thereto. The method of claim 2,
Further comprising a sense amplifier integrated on the substrate and formed between the substrate and the memory structure,
And the sense amplifier is disposed locally in the memory area. The method of claim 2,
The memory structure may include a cell array region disposed over the memory region and a word line contact region adjacent to the cell array region.
The semiconductor pattern is locally disposed in the cell array region,
And the word lines extend from the cell array area to the word line contact area. The method of claim 2,
The control structure further comprises a wordline driver connecting to the wordline,
And the wordline driver is locally integrated on a substrate of the memory region below the wordline contact region or integrated on a substrate of the peripheral region. The method according to claim 6,
And a word line connection structure directly connecting the word lines to the word line driver. The method of claim 1,
And a string connection structure directly connecting the ground select transistor and the string select transistor to the semiconductor pattern. The method of claim 1,
The memory structure is a three-dimensional semiconductor memory device in which MOS field effect transistors using the semiconductor pattern as a channel are sequentially stacked. The method of claim 1,
And a data storage layer pattern interposed between the semiconductor pattern and the word lines.

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