TWI805420B - Memory array - Google Patents

Abstract

A memory array is provided. The memory array comprises memory blocks, each comprising multiple data storage regions; and groups of word lines. Each group of the word lines run across one of the memory blocks, and the groups of the word lines are connected to overlying signal lines via groups of first word line pick-up regions in the memory blocks and second word line pick-up regions between the memory blocks.

Description

memory array

The present disclosure relates to a memory array, and more particularly to a flash memory array.

Memory is used to store data in digital systems, and is widely used in various electronic products. During the operation of the system, the data stored in the memory can be damaged due to various reasons, and this abnormal situation can be called the reduction of data retention reliability. For flash memory, larger floating gate transistors help improve data storage reliability. However, with the evolution of flash memory generations, the size of the floating gate transistor becomes smaller. Therefore, the problem of data storage reliability gradually emerges.

An aspect of the present disclosure provides a memory array, including: a plurality of memory blocks, each memory block includes a plurality of data storage areas; and a plurality of word lines, wherein each group of word lines traverses the plurality of One of the memory blocks, and the multiple sets of word lines are composed of multiple sets of first word line contact areas in the multiple memory blocks and multiple first word line contact areas between the multiple memory blocks The two-character line contact area is connected to multiple signal lines above.

Another aspect of the present disclosure provides a memory array, including: a plurality of memory blocks defined by a plurality of wells disposed in a substrate side by side, wherein each memory block includes a plurality of data storage areas; and a plurality of The well wiring is located on the base and extends along a single outer contour surrounding the plurality of wells, and is electrically connected to the plurality of wells.

FIG. 1 is a schematic plan view of a memory array 10 according to some embodiments of the present disclosure. The memory array 10 can be a flash memory array. The memory array 10 includes a plurality of memory blocks (blocks) 100 . Although not shown in FIG. 1 , each memory block 100 has a plurality of memory cells, and each memory cell can be formed by a floating gate transistor.

Several memory blocks 100 arranged along the direction X can constitute a repeating unit RU of the memory array 10 . A plurality of repeating units RU can be arranged in an array along the direction X and the direction Y intersecting the direction X. In addition, one of the memory blocks 100 in each repeating unit RU is provided with an ECC circuit area 102 . The ECC circuit is disposed in the ECC circuit area 102 to perform error checking and error correction on other memory cells in the same repeating unit RU. In other words, the multiple memory blocks 100 in each repeating unit RU share the ECC circuit disposed in one of them. In some embodiments, each repeating unit RU includes four memory blocks 100, wherein one edge memory block 100 (also referred to as memory block 100e) is provided with an ECC circuit area 102, and the other edge memory block 100e and The central memory block 100 (also referred to as the memory block 100c ) located between the two edge memory blocks 100e is not provided with the ECC circuit area 102 .

In some embodiments, a decoder 104 may be arranged around each repetition unit RU. The decoder 104 is configured to select a specified memory cell for access according to an input signal. For example, a plurality of decoders 104 are respectively arranged on opposite sides extending along the direction Y of each repeating unit RU (for example, two rows of decoders 104 respectively used by adjacent repeating units RU in the direction X). In addition, decoders may also be provided on opposite sides of each repeating unit RU extending along the direction X, and adjacent repeating units RU in the direction Y may share a decoder (not shown) between them.

The memory blocks 100 respectively include a well region 106 in the semiconductor substrate. The memory cells in each memory block 100 can be constructed on the corresponding well 106 . The well area 106 of the edge block 100e in the repeat unit RU is also referred to as the well area 106e hereinafter, and the well area 106 of the central block 100c in the repeat unit RU is also referred to as the well area 106c below. For the edge memory block 100e including the ECC circuit area 102, the ECC circuit in the ECC circuit area 102 is also constructed on the well area 106e of these edge memory blocks 100e. For example, the well area 106e of the edge memory block 100e that includes the ECC circuit area 102 may be larger than the well area 106c of the central memory block 100c that does not include the ECC circuit area 102, and is greater than or equal to that that does not include the ECC circuit. The edge memory block 100e of the region 102 is the well region 106e. Each well region 106 can be a P-type doped region or an N-type doped region in the semiconductor substrate, and extends from the front surface of the semiconductor substrate into the semiconductor substrate. Furthermore, the plurality of well regions 106 are laterally spaced from one another. In some embodiments, the plurality of well regions 106 are separated by isolation structures (not shown) disposed in the semiconductor substrate.

In some embodiments, a plurality of well taps 108 are disposed above the semiconductor substrate. The well connection 108 is configured to be electrically connected to the well 106 for biasing the well 106 . Each well wire 108 extends along the contour of the underlying well 106 . In some embodiments, the well wiring 108 (also referred to as the well wiring 108e) on the well 106e at both ends of each repeating unit RU respectively surrounds the corresponding well 106e on three sides, and respectively faces the other wells in the same repeating unit RU. The lateral opening of the well area 106 . On the other hand, the well wiring 108 (also referred to as the well wiring 108c) on the well 106c between the two ends of each repeating unit RU respectively extends along two opposite sides of the lower well 106c in the direction X, and respectively There are two line segments separated from each other and extending in direction X. In this way, a single outer contour of all the wells 106 of each repeating unit RU can be surrounded by a set of well lines 108 . And the well connection 108 does not extend to the area between adjacent wells 106 in each repeating unit RU. In some embodiments, each well wire 108 extends inside the outline of the underlying well 106 (as shown in FIG. 2 ). In some embodiments, adjacent well wires 108 are laterally spaced apart from each other.

FIG. 2 is an enlarged schematic plan view of the area A1 in FIG. 1 . The detailed structures within each memory block 100 and between adjacent memory blocks 100 will be described below with reference to FIG. 2 . Each memory block 100 includes a plurality of active areas AA. The channel region of the floating gate transistor constituting the memory cell MC may be formed in the active region AA. The active region AA is a doped region located in the well region 106 , and generally the conductivity type of the active region AA is complementary to that of the well region 106 . For example, when the well region 106 is an N-type doped region, the active region AA may be a P-type doped region. In some embodiments, the active areas AA respectively extend along the direction Y, and are laterally spaced apart from each other in the direction X.

In some embodiments, each memory block 100 is further provided with a dummy active area AA1. Similar to the active region AA, the dummy active region AA1 is also a doped region in the well region 106 . The dummy active area AA1 may surround the active area AA, and may have the same conductivity type as the active area AA. In some embodiments, the dummy active area AA1 may include two sides extending along the direction X on both sides of the active area AA, and may optionally include the other two extending along the direction Y on the other sides of the active area AA. . In these embodiments, the dummy active areas AA1 may be spaced apart from each other. In addition, in some embodiments, a dummy active area AA2 may also be set between adjacent memory blocks 100 . The dummy active area AA2 is also a doped area disposed in the semiconductor substrate, and has the same conductivity type as the active area AA. In the embodiment where the active area AA extends along the direction Y and is arranged along the direction X, the dummy active area AA2 may also extend along the direction Y and is arranged along the direction X. Different from the active area AA and the dummy active area AA2 , the dummy active area AA2 is located between adjacent well areas 106 instead of within the well area 106 .

Word lines WL intersecting with the active area AA may be disposed on the semiconductor substrate. The word line WL can cross the well area 106 and intersect with the active area AA, and can be used as the control gate of the floating gate transistor constituting the memory cell MC. In addition, the word line WL can also intersect with the dummy active area AA1 and the dummy active area AA2 parallel to the active area AA. A tunneling dielectric layer, a floating gate, and an inter-gate dielectric layer (not shown) may also be disposed between the word line WL and the active area AA. Similarly, a tunnel dielectric layer, a floating gate, and an inter-gate dielectric layer (not shown) may also be disposed between the word line WL and the staggered dummy active areas AA1 and AA2 . In an embodiment where the active area AA extends along the Y direction, the word line WL may extend along the X direction. Word lines WL extending over adjacent well regions 106 are spaced apart from each other. In some embodiments, the discontinuities B between two sets of word lines WL of two adjacent well regions 106 in the crossing direction X are alternately located in the dummy active area AA2 between the two adjacent well regions 106 along the direction Y. opposite sides of the two adjacent well regions 106 so that two sets of word lines WL alternately intersect the dummy active area AA2 between the two adjacent well regions 106 .

A plurality of first drain/source contact structures 110 and second drain/source contact structures 112 can also be disposed in each memory block 100 . The first and second drain/source contact structures 110 and 112 are disposed on the semiconductor substrate and electrically connected to portions of the active area AA located on opposite sides of each word line WL. The first drain/source contact structures 110 can be columnar structures respectively, and respectively overlap a single active area AA. On the other hand, the second drain/source contact structures 112 can be respectively formed as conductive walls, and respectively overlap a plurality of active areas AA. A row of first drain/source contact structures 110 and a second drain/source contact structure 112 may be disposed on opposite sides of each word line WL. A floating gate transistor as a memory cell MC can be defined at the intersection of a word line WL and an active area AA, so that the word line WL serves as the control gate of the floating gate transistor , and a first drain/source contact structure 110 and a second drain/source contact structure 112 on opposite sides of the word line WL in the active area AA serve as the floating gate electrode Crystal drain and source. Each word line WL and each second drain/source contact structure 112 can be shared by a row of memory cells MC, and each active area AA can be shared by a row of memory cells MC. In some embodiments, each of the first drain/source contact structure 110 or the second drain/source contact structure 112 can be shared by adjacent memory cells MC in the same row.

On the other hand, each memory block 100 may further include a dummy memory cell DC. Unlike the memory cell MC, the dummy memory cell DC is not used to access data. The dummy memory cell DC can be located around the memory cell MC and is similar in structure to the memory cell MC. As a difference from memory cells MC, some dummy memory cells DC may have a pair of first and second drain/source contact structures 110, 112, respectively, while other dummy memory cells DC may have a pair of first and second drain/source contact structures, respectively. Two drain/source contact structures 112, and some dummy memory cells DC may have only a single second drain/source contact structure 112 respectively.

In some embodiments, a dummy word line DWL is further disposed on the semiconductor substrate. The dummy word lines DWL may be parallel to the word lines WL, and may be staggered at the end of the active area AA. In addition, similar to the word line WL, the dummy word line DWL can also extend to the area between adjacent memory blocks 100 and can be interrupted in this area.

1 and 2, each memory block 100 is designed with a plurality of word line contact areas ST0 spaced apart from each other, and each memory block 100 is divided into a plurality of data storage areas 100'. The memory cells MC in the data storage area 100' are configured to access data. On the other hand, the word line WL runs through the data storage area 100' and the word line contact area ST0, and can be connected to the upper signal line (not shown) through the word line contact area ST0, and can receive control signal. A plurality of word line contact structures 114 can be disposed in the word line contact area ST0 to wind the word line WL up. The word line contact structures 114 can be columnar structures, and stand on a word line WL respectively. The word line contact structures 114 in each word line contact area ST0 may be spaced apart from the adjacent word line contact structures 114 in both directions X and Y, respectively. In some embodiments, the word line contact structures 114 in each word line contact area ST0 are arranged in two rows along the direction X, wherein the word line contact structures 114 of one row are opposite to the word line contact structures of the other row. 114 and offset along direction Y. In these embodiments, the word line contact structures 114 in each word line contact area ST0 may be alternately disposed on opposite sides of an active area AA along the direction Y. For example, three active areas AA can be disposed in each word line contact area ST0, and the word line contact structures 114 can be alternately disposed on opposite sides of the middle active area AA along the direction Y.

In some embodiments, the first drain/source contact structure 110 and the second drain/source contact structure 112 are not disposed in each word line contact area ST0. In some embodiments, the first drain/source contact structure 110 is distributed in the data storage area 100' outside the word line contact area ST0, and the second drain/source contact structure 112 is located at the word line contact. Interrupt at zone ST0. In this way, the word line WL still intersects with the active area AA in each word line contact area ST0, and forms a floating transistor, but because the first and second drain/source contacts are not Structures 110 and 112 are used to control the floating transistors in the word line contact area ST0, so the floating transistors in the word line contact area ST0 may not be used as memory cells. In other words, the memory cells MC in each memory block 100 can be distributed in the data storage area 100' other than the word line contact area ST0. Similarly, the dummy memory cells DC in each memory block 100 can also be distributed in the data storage area 100' outside the word line contact area ST0.

In addition to the word line contact area ST0 , a word line contact area ST1 is further provided between adjacent memory blocks 100 . The word line WL running through each memory block 100 can enter the adjacent word line contact area ST1 and be interrupted at the discontinuity B. The word line WL can be connected to an upper signal line (not shown) from the word line contact area ST1 to receive a control signal. A plurality of word line contact structures 116 can be disposed in the word line contact area ST1 to wind up the word line WL. The word line contact structures 116 can be columnar structures, and stand on a word line WL respectively. In addition, the word line contact structures 116 in each word line contact area ST1 may also be spaced apart from the adjacent word line contact structures 116 in both the direction X and the direction Y. In some embodiments, the word line contact structures 116 in each word line contact area ST1 are arranged in two rows along the direction X, wherein the word line contact structures 116 of one row are opposite to the word line contact structures of the other row. 116 and offset along direction Y. In these embodiments, the word line contact structures 116 in each word line contact area ST1 may be alternately disposed on opposite sides of a dummy active area AA2 along the direction Y. For example, three dummy active areas AA2 can be disposed in each word line contact area ST1, and the word line contact structures 116 can be alternately disposed on opposite sides of the middle dummy active area AA2 along the direction Y. In addition, in these embodiments, the word line WL extending from each memory block 100 to the word line contact area ST1 may have a long line segment LS1 and a short line segment LS2 located in the word line contact area ST1, and the long line segment The segments LS1 and short line segments LS2 may be arranged alternately along the direction Y. Furthermore, each word line discontinuity B can be located between a long line segment LS1 and a short line segment LS2.

Regarding the difference, the word line contact area ST0 is located in each memory block 100 , and the word line contact area ST1 is located between adjacent memory blocks 100 . In other words, the word line contact area ST0 is located within the well area 106 defining each memory block 100 , and the word line contact area ST1 is located between adjacent well areas 106 . In some embodiments, except the word line WL extending to the word line contact area ST1, the active area AA, the dummy active area AA1, the first drain/source contact structure 110, Components such as the second drain/source contact structure 112 , the word line contact structure 114 , and the well line 108 are not distributed or extended to the word line contact region ST1 . Additionally, in embodiments where dummy wordlines DWL are provided, dummy wordlines DWL may extend through wordline contact region ST0 to adjacent wordline contact region ST1, but may not be contacted by the wordline The structures 114, 116 are connected to the upper signal lines (not shown).

FIG. 3 is an enlarged schematic plan view of the area A2 in FIG. 1 . The detailed structure of the edge memory block 100e including the ECC circuit area 102 will be described with reference to FIG. 3 .

Referring to FIG. 1 and FIG. 3 , in some embodiments, the layout of the ECC circuit area 102 is the same as the layout of a plurality of data storage areas 100' separated by the word line contact area ST0 in each memory block 100 . In these embodiments, the ECC circuit area 102 is provided with a plurality of active areas AA, word lines WL intersecting the active areas AA, and word lines WL disposed on the active area AA on opposite sides of each word line WL. The first and second drain/source contact structures 110, 112 can form a plurality of memory cells MC and a plurality of dummy memory cells DC. However, the memory cells MC located in the ECC circuit area 102 are particularly configured to perform error checking and error correction on the data stored in the memory cells MC in each data storage area 100'. In addition, in the embodiment provided with dummy word lines DWL, the dummy word lines DWL may extend into the ECC circuit area 102 and intersect the active area AA in the ECC circuit area 102 . Furthermore, in some embodiments, the dummy active area AA1 in the edge memory block 100e extends along the direction X on opposite sides of the active area AA.

As shown in FIG. 1 , the ECC circuit areas 102 are respectively located on the side of an edge memory block 100 e farthest from the adjacent central memory block 100 c. In these embodiments, each ECC circuit area 102 is adjacent to the adjacent data storage area 100' in the edge memory block 100e via the extra word line contact area ST0'. Therefore, compared with the central memory block 100c and the edge memory block 100e not including the ECC circuit area 102, the edge memory block 100e including the ECC circuit area 102 has more features besides having a plurality of word line contact areas ST0 The word line contact area ST0'.

Referring to FIG. 3 , the layout of the word line contact area ST0' is the same as that of the other word line contact area ST0 described with reference to FIG. 2 . In other words, the word line WL running through the ECC circuit area 102 and the data storage area 100' also runs through the word line contact area ST0', and can intersect with the active area AA disposed in the word line contact area ST0'. In addition, the word line WL is connected to the upper signal line (not shown) through the word line contact structure 114 in the word line contact area ST0'. In an embodiment provided with a dummy word line DWL, the dummy word line DWL also runs through the word line contact region ST0', but may not be wound up through the word line contact structure 114.

Furthermore, the ECC circuit area 102 can also be adjacent to the word line contact area ST2. The word line contact area ST2 can be located at the edge of the edge memory block 100e, so that the ECC circuit area 102 is located between the word line contact areas ST0', ST2. The word line WL can extend from above the ECC circuit area 102 to the range of the word line contact area ST2, and can be connected to an upper signal line (not shown) from the word line contact area ST2 to receive control signals. A plurality of word line contact structures 118 can be disposed in the word line contact area ST2 to wind up the word line WL. The word line contact structures 118 can be columnar structures standing on the ends of a word line WL respectively. In some embodiments, the word line contact structure 118 may be larger than the word line contact structure 114 and the word line contact structure 116 in size (eg, length, width). In an embodiment provided with a dummy word line DWL, the dummy word line DWL may extend from the ECC circuit area 102 to the word line contact area ST2. Furthermore, the dummy word line DWL can be connected to several adjacent word lines WL in the word line contact area ST2 to receive the same signal.

In some embodiments, the word line WL extending into the word line contact area ST2 has a long line segment LS3 and a short line segment LS4 located in the word line contact area ST2, and the long line segment LS3 and the short line segment LS4 can be along the The directions Y are arranged alternately. In these embodiments, the word line contact structures 118 standing at the end of each word line WL can be arranged in two rows, wherein the word line contact structures 118 of one row can be aligned along the direction relative to the word line contact structures 118 of the other row. Y displacement. In addition, in the embodiment provided with a dummy word line DWL, the line segment of the dummy word line DWL located in the word line contact area ST2 can be connected with the segment of the adjacent word line WL in the word line contact area ST2. Line segments are of equal length.

In some embodiments, the active area AA, the first drain/source contact structure 110 and the second drain/source contact structure 112 in the edge memory block 100e are not distributed or extended to the word line. In point zone ST2. In the embodiment provided with the dummy active area AA1, the dummy active area AA1 may not extend into the word line contact area ST2.

As described with reference to FIG. 2 and FIG. 3 , each word line WL can be connected to the upper signal line through the word line contact areas ST0, ST0', ST1, ST2. FIG. 4 illustrates one of the signal lines MX.

Referring to FIG. 4 , the signal line MX can extend along the direction X and overlap a plurality of word lines WL that cross the plurality of memory blocks 100 below. Such word lines WL may be contacted via word line contact structures 114, 116 in word line contact areas ST0, ST1 and word line contact structures in word line contact areas ST0', ST2 described with reference to FIG. Structures 114, 118 are connected to the signal line MX. In other words, these word lines WL can be interconnected with each other and receive the same signal. In addition, the data storage area 100' and the ECC circuit area 102 can be interconnected by the signal line MX, so that the ECC circuit area 102 can perform error detection and error correction on the data storage area 100'. Although only one signal line MX is shown in FIG. 4 , a plurality of signal lines MX parallel to the word lines WL may be arranged to interconnect the plurality of word lines WL arranged along the direction X respectively.

FIG. 5 illustrates a signal line MY connected to the first drain/source contact structure 110 and the second drain/source contact structure 112 according to some embodiments.

Referring to FIG. 5 , a plurality of signal lines MY extend above the active area AA and may be substantially parallel to the active area AA. In addition, the signal line MY can be connected to the first drain/source contact structure 110 and the second drain/source contact structure 112 on the active area AA. The signal line MY connected to the first drain/source contact structure 110 may also be called a bit line, and the signal line MY connected to the second drain/source contact structure 112 may also be called a source line. The bit lines and the source lines may be arranged along a direction (for example, direction X) intersecting with the active area AA. In some embodiments, a plurality of bit lines may be arranged between adjacent source lines. For example, 2048 bit lines cross each memory block 100, and 256 bit lines can be arranged between adjacent source lines.

Although not shown, signal lines MY including bit lines and source lines are also distributed on the ECC circuit area 102 described with reference to FIG. 3 to provide signals to the first drain/source in the ECC circuit area 102 The contact structure 110 and the second drain/source contact structure 112 . In addition, the arrangement period of the bit lines and the source lines on the ECC circuit area 102 may be the same as the arrangement period of the bit lines and the source lines on the data storage area 100'.

In some embodiments, the signal line MY extends below or above the signal line MX described with reference to FIG. 4 . For example, the signal line MY and the well wiring 108 may extend below the signal line MX.

Fig. 6 illustrates a repeating unit RU' in a memory array according to other embodiments. Fig. 7 shows the detailed structure of the edge portion of the repeating unit RU'. It should be noted that the memory array including multiple repeating units RU' is similar to the memory array 10 including multiple repeating units RU described with reference to FIG. Note, the same or similar points will not be repeated.

Referring to FIG. 6 and FIG. 7, the edge memory block 100e in each repeating unit RU' may further include a redundant cell area RC. The layout in the redundant cell area RC can be the same as that in the data storage area 100', but the memory cell MC in the redundant cell area RC is specially used to replace all the data storage areas 100' in the same repeating unit RU' damaged memory cells (if any) within.

The redundant cell region RC may be located between the ECC circuit region 102 and the word line contact region ST2. The word line WL crossing the ECC circuit area 102 can further extend through the redundant cell area RC and enter the word line contact area ST2. In some embodiments, no word line contact area is provided between the ECC circuit area 102 and the redundant cell area RC. In these embodiments, memory cells MC and dummy memory cells DC can be arranged continuously across the boundary between the ECC circuit area 102 and the redundant cell area RC. In addition, in some embodiments, the dummy active area AA1 disposed in the edge memory block 100e further extends along opposite sides of the redundant cell area RC.

On the other hand, as shown in FIG. 6 , the central memory block 100c and the edge memory block 100e not provided with the ECC circuit area 102 may not be provided with the redundant cell area RC. In other words, the ECC circuit area 102 and the redundant cell area RC can only be disposed in a single edge block 100e in each repeating unit RU', so as to avoid greatly increasing the occupied area of each repeating unit RU'.

To sum up, according to various embodiments, a plurality of memory blocks arranged along the column direction constitute a repeating unit of the flash memory array. The word lines of all memory blocks in each repeat unit can be connected upwardly to traverse the repeat unit through the word line contact areas in each memory block and the word line contact areas between adjacent memory blocks. signal line. With this design, multiple memory blocks in the same repeating unit can share the ECC circuit for improving the reliability of data storage through the signal line. In this way, compared with setting ECC circuits in each memory block, the disclosed embodiment can enable multiple memory blocks in the same repeating unit to share the ECC circuit in a single ECC circuit area, which can effectively save flash memory. The footprint of the memory array. Not only that, based on using less ECC circuit area to perform error checking and error correction, the required word line contact area between the ECC circuit area and the data storage area (that is, the aforementioned word line contact area) can also be reduced. area ST0'). In this way, the limited wafer area can be optimally utilized.

10: Memory array 100, 100c, 100e: memory block 100': data storage area 102:ECC circuit area 104: decoder 106, 106c, 106e: well area 108, 108c, 108e: well area wiring 110, 112: drain/source contact structure 114, 116, 118: word line contact structure A1, A2: area AA: active area AA1, AA2: false active area B: Discontinuity DC: dummy memory cell DWL: dummy word line LS1, LS3: long line segment LS2, LS4: short line segments MC: memory cell MX, MY: signal line RC: redundant cell region RU, RU': repeating unit ST0, ST0', ST1, ST2: word line contact area WL: character line X, Y: direction

FIG. 1 is a schematic plan view of a memory array of some embodiments of the present disclosure. FIG. 2 is an enlarged schematic plan view of the area A1 in FIG. 1 . FIG. 3 is an enlarged schematic plan view of the area A2 in FIG. 1 . FIG. 4 schematically illustrates a signal line connecting adjacent word lines according to some embodiments. 5 illustrates a plurality of signal lines connected to a first drain/source contact structure and a second drain/source contact structure, according to some embodiments. FIG. 6 illustrates a repeat unit in a memory array according to other embodiments. FIG. 7 illustrates the detailed structure of the edge portion of the repeating unit in FIG. 6 .

10: Memory array

100, 100c, 100e: memory block

102:ECC circuit area

104: decoder

106, 106c, 106e: well area

108, 108c, 108e: well area wiring

A1, A2: area

RU: repeating unit

ST0, ST0', ST1, ST2: word line contact area

X, Y: direction

Claims (18)

A memory array, comprising: a plurality of memory blocks, wherein each memory block includes a plurality of data storage areas; and a plurality of groups of word lines, wherein each group of word lines traverses one of the plurality of memory blocks or, and the multiple groups of word lines are composed of multiple groups of first word line contact areas in the plurality of memory blocks and a plurality of second word line contact points between the plurality of memory blocks area connects to multiple signal lines above. The memory array as claimed in claim 1, wherein one of the edges of the plurality of memory blocks further includes an error checking and correction (ECC) circuit area, and the ECC circuit in the ECC circuit area configured to perform error detection and error correction on the plurality of data storage areas of each of the plurality of memory blocks. The memory array according to claim 1, wherein each group of word lines extends continuously through a group of first word line contact areas in the plurality of groups of first word line contact areas, and the Adjacent two groups of word lines in the plurality of groups of word lines are spaced apart from each other at one of the plurality of second word line contact areas. The memory array as described in claim 1, wherein the plurality of data storage areas in each memory block are composed of a group of first word line contact areas in the plurality of groups of first word line contact areas spaced apart from each other, and wherein a plurality of active areas in each memory block are distributed in the plurality of data storage areas in each memory block and a group of characters in the plurality of first word line contact areas within the line contact area. The memory array according to claim 4, wherein a plurality of word line contact structures provide electrical connections between the plurality of groups of word lines and the plurality of signal lines, and the plurality of word line contact structures The first group of word line contact structures in the first group of word line contact areas is located in a word line contact area of the plurality of first word line contact areas and along a direction staggered with the extension direction of the plurality of groups of word line contact areas Alternately arranged on both sides of one of the plurality of active regions. The memory array according to claim 5, wherein adjacent two of the first group of word line contact structures are spaced apart from each other in a first direction and a second direction, and the first direction is staggered between the second direction. The memory array of claim 5, wherein a second set of word line contact structures of the plurality of word line contact structures is located within one of the second plurality of word line contact areas, Two adjacent word line contact structures in the second group are spaced apart from each other in a first direction and a second direction, and the first direction is intersected with the second direction. The memory array according to claim 1, wherein a plurality of drain/source contact structures are arranged in the plurality of memory blocks, and the plurality of drain/source contact structures are not distributed to the plurality of In the first word line contact area of the set, and the memory array further includes a plurality of active areas connected to the plurality of drain/source contact structures and parallel to the plurality of memory blocks. additional signal lines. The memory array according to claim 2, wherein one of the edges of the plurality of memory blocks further includes a third word line between the ECC circuit region and the plurality of data storage regions contact area, and one of the multiple sets of word lines The word lines are further connected to the plurality of signal lines above by the plurality of word line contact structures in the third word line contact area. The memory array according to claim 9, wherein a plurality of active areas in one of the edges of the plurality of memory blocks are further distributed in the third word line contact area, and the Drain/source contact structures in one of the edges of the memory blocks are not distributed into the third word line contact area. The memory array as described in claim 9, further comprising a fourth word line contact area adjacent to the ECC circuit area of one of the edges of the plurality of memory blocks, the plurality of groups of words The group of word lines in the line is connected to the plurality of signal lines through the plurality of word line contact structures in the fourth word line contact area, and the ECC circuit area is located in the fourth word line contact area. Between the contact area of the three word lines and the contact area of the fourth word line. The memory array according to claim 11, wherein said group of word lines in said plurality of groups of word lines has a plurality of long end line segments located in said fourth word line contact area and a plurality of Short end line segments, the plurality of long end line segments and the plurality of short end line segments are arranged alternately along another direction intersecting with the extension direction of the plurality of sets of word lines. The memory array as described in claim 1, wherein a plurality of dummy active areas are arranged in each second word line contact area, and the conductivity type and extension direction of the plurality of dummy active areas are respectively the same as those in each memory block The conductivity type of the plurality of active regions is the same as the extension direction. The memory array as claimed in claim 1, wherein one of the edges of the plurality of memory blocks further includes a redundant cell area, wherein the redundant cell area has a memory area for replacing the plurality of memory areas redundant cells of damaged memory cells in a block, and wherein the plurality of memory blocks other than one of the edges does not include a redundant cell area for replacing damaged memory cells . The memory array of claim 1, wherein the plurality of signal lines traverse the plurality of memory blocks, and wherein the plurality of signal lines are parallel to the plurality of sets of word lines. A memory array, comprising: a plurality of memory blocks, defined by a plurality of wells arranged in a base and arranged side by side, wherein each memory block includes a plurality of data storage areas; a plurality of groups of character lines, wherein each group of characters A line crosses one of the plurality of memory blocks, and the plurality of sets of word lines are composed of a plurality of sets of first word line contact areas in the plurality of memory blocks and the plurality of memory areas a plurality of second word line contact areas between the blocks are connected to a plurality of signal lines above; and a plurality of well lines are located on the substrate and extend along a single outer contour surrounding the plurality of well areas , and electrically connected to the plurality of well regions. The memory array of claim 16, wherein the plurality of well lines do not extend to areas between the plurality of wells. The memory array according to claim 16, wherein the plurality of well wirings include: two first well wirings, respectively surrounding two edges of the plurality of wells on three sides a well area; and a plurality of second well area lines, respectively having two line segments separated from each other, and extending along opposite sides of a plurality of central well areas in the plurality of well areas.

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