KR20160118118A - Semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

Vertical channel structures are two-dimensionally arranged on a substrate and vertically extended from the substrate. Bit lines are provided onto the vertical channel structures and connect the vertical channel structures arranged along a first direction. A plurality of common source lines are extended between the vertical channel structures along a second direction crossing the first direction. A source strapping line is located on the same vertical level as the bit lines and electrically connects the plurality of common source lines.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a manufacturing method thereof,

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same.

It is required to increase the degree of integration of semiconductor devices to satisfy excellent performance and low cost. In particular, the degree of integration of the memory device is an important factor in determining the price of the product. Since the degree of integration of the conventional two-dimensional memory device is mainly determined by the area occupied by the unit memory cell, the degree of integration of the fine pattern formation technology is greatly affected. However, the integration of the two-dimensional semiconductor memory device is increasing, but is still limited, because of the need for expensive equipment to miniaturize the pattern.

In order to overcome such a limitation, three-dimensional memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce the three-dimensional memory device, a process technology capable of realizing reliable product characteristics while reducing the manufacturing cost per bit of the two-dimensional memory device is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device with improved integration. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor memory device that can simplify a process. The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to the concept of the present invention, a semiconductor memory device includes vertical channel structures arranged two-dimensionally on a substrate and extending vertically from the substrate; Bit lines connecting the vertical channel structures provided on the vertical channel structures and arranged along a first direction; A plurality of common source lines extending between the vertical channel structures along a second direction intersecting the first direction; And a source strapping line located at the same vertical level as the bit lines and electrically connecting the plurality of common source lines.

The width of the source strapping line may be greater than the width of the bit lines.

Further comprising: contacts overlapping the common source lines and electrically connecting the bit lines to the vertical channel structures, wherein at least two of the contacts at intersections of one of the common source lines and the source strapping line May be provided.

And a source stud connected to an upper portion of the common source lines and connected in common with the at least two contacts.

And conductive lines connected to a bottom surface of the contacts and extending over the vertical channel structures across the common source lines.

And channel studs connecting the top of the vertical channel structures and the conductive lines.

The channel studs may not be provided on the vertical channel structures overlapping the source strapping line.

The conductive lines may have an asymmetrical length with respect to the common source lines.

The conductive lines may have offset regions at portions overlapping the common source lines.

Wherein the common source lines include a first common source line and a second common source line adjacent thereto and wherein the conductive lines are offset in the second direction at a portion overlapping the first common source lines, And may be offset in a direction antiparallel to the second direction at a portion overlapping the lines.

Wherein the common source lines comprise a first common source line and a second common source line closest to the first common source line and the odd bit lines of the bit lines are connected to the contacts on the first common source line And even-numbered bit lines of the bit lines may connect with the contacts on the second common source line.

The common source lines may have a planar shape across the vertical channel structures.

An electrode structure provided on the substrate and including vertically stacked electrodes; Vertical channel structures that are connected to the substrate through the stacked structure; First and second common source lines located on both sides of the electrode structure to define the electrode structure; Contacts arranged along the extension direction of the first and second common source lines on the first and second common source lines; Bit lines extending in an intersection with the first and second common source lines and electrically connected to the vertical channel structures; And a source strapping line electrically connecting the first and second common source lines, wherein the number of contacts connecting the first common source line and the source strapping line is greater than the number of the second common source line and the source May be different from the number of contacts connecting the strapping lines.

Further comprising conductive lines extending over one of the first and second common source lines from the vertical channel structures, wherein the source strapping line may overlap a plurality of conductive lines.

Odd contacts of the contacts may be connected to the bit lines on the first common source line and even ones of the contacts may be connected to the bit lines on the second common source line.

The source strapping line may be connected to a plurality of contacts at a point overlapping each of the first and second common source lines.

Further comprising a source stud between the source strapping line and the conductive lines, the source stud being commonly connected to the plurality of conductive lines overlapping the source strapping line.

The substrate may include a cell region and a peripheral circuit region, and a plurality of source strapping lines may be provided on the cell region.

The source strapping line and the bit lines may be located at the same vertical level.

Further comprising conductive lines extending over one of the first and second common source lines from the vertical channel structures, wherein the conductive lines have offset regions at portions overlapping the common source lines have.

The semiconductor memory device according to the present invention is capable of forming a source strapping line electrically connected to a plurality of common source lines and capable of applying the same voltage at the same level as the bit lines, A voltage can be applied to the source region. Also, the placement of the bit lines connecting the vertical channel structures by the offset conductive lines can be optimized.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.
2 is a conceptual diagram for explaining a schematic configuration of a semiconductor memory device according to embodiments of the present invention.
3 is a plan view of a cell array region of a semiconductor memory device according to embodiments of the present invention.
4A is a cross-sectional view taken along the line A-A 'in FIG.
And FIG. 4B is a cross-sectional view taken along lines B-B 'and C-C' in FIG.
4C is a cross-sectional view of a peripheral circuit region of a semiconductor memory device according to embodiments of the present invention.
5 is an enlarged view of the area M in Fig.
6, 8, 10, 12, 14, and 16 are plan views illustrating a method of manufacturing a semiconductor memory device according to embodiments of the present invention.
Figs. 7A, 9A, 11A, 13A, 15A and 17A are cross-sectional views taken along line A-A 'in Figs. 6, 8, 10, 12, 14 and 16, respectively.
7B, 9B, 11B, 13B, 15B and 17B are cross-sectional views taken along lines B-B 'and C-C' of FIGS. 6, 8, 10, 12, Fig.
18 is a schematic block diagram illustrating an example of a memory system including semiconductor devices formed in accordance with embodiments of the inventive concept.
19 is a schematic block diagram showing an example of a memory card having semiconductor elements formed according to embodiments of the concept of the present invention.
20 is a schematic block diagram showing an example of an information processing system equipped with semiconductor devices formed according to embodiments of the concept of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

In the present specification, when a material film such as a conductive film, a semiconductor film, or an insulating film is referred to as being on another material film or substrate, any material film may be formed directly on the other material film or substrate, Which means that another material film may be interposed between them. Also, while the terms first, second, third, etc. have been used in the various embodiments herein to describe a material film or process step, it should be understood that it is merely intended to refer to a particular material film or process step, , And should not be limited by such terms.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.

1, a semiconductor memory device according to an embodiment includes a plurality of common source regions CSR1 to CSRn, a plurality of bit lines BL0 to BLn, and common source regions CSR1 to CSRn, And a plurality of cell strings CSTR disposed between the lines BL0-BLn.

The common source regions CSR1 to CSRn may be an electrically conductive thin film disposed on the semiconductor substrate or an impurity region formed in the substrate. The bit lines BL0-BLn may be conductive patterns (e.g., metal lines) spaced from and disposed above the semiconductor substrate. A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0-BLn. Accordingly, the cell strings CSTR are two-dimensionally arranged on the substrate.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source regions CSR1-CSRn, a string selection transistor SST connected to the bit lines BL0-BLn, And a plurality of memory cell transistors MCT disposed between the selection transistors GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series. In addition, a ground selection line (GSL), a plurality of word lines (WL0-WLk) and a plurality of word lines (WL0-WLk), which are disposed between the common source regions (CSR1-CSRn) and the bit lines The lines SSL0-SSLm may be used as the gate electrode layers of the ground selection transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively.

The ground selection transistors GST may be disposed at substantially the same distance from the substrate, and their gate electrode layers may be connected in common to the ground selection line GSL to be in an equipotential state. To this end, the ground selection line GSL is connected between the common source regions CSR1-CSRn and the memory cell transistor MCT closest to the common source regions CSR1-CSRn in a plate-like or comb- Pattern. Similarly, the gate electrode layers of the plurality of memory cell transistors MCT, which are disposed at substantially the same distance from the common source regions CSR1 to CSRn, are also common to one of the word lines WL0 to WLk Connected and may be in the equipotential state. To this end, each of the word lines WL0-WLk may be a flat or comb-like conductive pattern parallel to the upper surface of the substrate. Since one cell string CSTR is composed of a plurality of memory cell transistors MCT having different distances from the common source regions CSR1 to CSRn, And a plurality of word lines WL0-WLk are arranged between the bit lines BL0-BLn.

Each of the cell strings CSTR may include a semiconductor pillar extending vertically from the common source regions CSR1 to CSRn to connect to the bit lines BL0 to BLn. The semiconductor pillars may be formed to penetrate the ground selection line GSL and the word lines WL0-WLk. In addition, the semiconductor pillars may include impurity regions formed at one or both ends of the body portion and the body portion. For example, a drain region may be formed at the top of the semiconductor column.

Meanwhile, an information storage film may be disposed between the word lines WL0-WLk and the semiconductor columns. According to one embodiment, the information storage film may be a charge storage film. For example, the information storage film may be one of an insulating layer including a trap insulating layer, a floating gate electrode, or conductive nano dots.

The ground selection transistor GST or the string selection transistor SST is used as a gate insulation layer between the ground selection line GSL and the semiconductor column or between the string selection lines SSL0-SSLm and the semiconductor column A dielectric film can be disposed. At least one gate insulating layer of the ground and string select transistors GST and SST may be formed of the same material as the data storage layer of the memory cell transistor MCT, Or may be an insulating layer (for example, a silicon oxide film).

The ground and string select transistors GST and SST and the memory cell transistors MCT may be MOSFETs using a semiconductor column as a channel region. According to another embodiment, the semiconductor column may comprise a MOS capacitor together with the ground selection line GSL, the word lines WL0-WLk and the string selection lines SSL0-SSLm . In this case, the ground selection transistor GST, the memory cell transistors MCT and the string selection transistor SST are connected to the ground selection line GSL, the word lines WL0-WLk, Can be electrically connected by sharing an inversion layer formed by a fringe field from the gate line (SSL0-SSLm).

The common source regions CSR1-CSRn may be electrically connected to the source straining line CSS through the common source lines CSL1-CSLn. That is, the common source regions CSR1-CSRn may be connected in common to the source straining line CSS to be in an equipotential state. As an example, during read or program operation of the semiconductor memory device, a ground voltage may be applied to the common source regions CSR1-CSRn through the source strapping line CSS. Hereinafter, the structure of the semiconductor memory device including the source straining line CSS will be described in more detail.

2 is a conceptual diagram for explaining a schematic configuration of a semiconductor memory device according to embodiments of the present invention. Referring to FIG. 2, the semiconductor memory device includes a cell array region CAR, and a peripheral circuit region. The peripheral circuit region includes row decoder regions (ROW DCR), a page buffer region (PBR), and a column decoder region (COL DCR). In the cell array area CAR, a memory cell array composed of a plurality of memory cells is arranged. The memory cell array includes a plurality of memory cells and a plurality of word lines and bit lines electrically coupled to the memory cells. In one embodiment, the memory cell array may include a plurality of memory blocks that are data erase units.

A row decoder for selecting the word lines of the memory cell array is arranged in the row decoder region (ROW DCR). The row decoder selects one of the memory blocks of the memory cell array and selects one of the word lines of the selected memory block according to the address information. The row decoder may provide a word line voltage generated from a voltage generating circuit (not shown) to selected word lines and unselected word lines, respectively, in response to control of a control circuit (not shown).

A page buffer area (PBR) may be provided with a page buffer for reading information stored in the memory cells. The page buffer may temporarily store data to be stored in the memory cells or sense data stored in the memory cells, depending on the operation mode. The page buffer operates as a write driver circuit in the program operation mode and can operate as a sense amplifier circuit in the read operation mode.

A column decoder connected to the bit lines of the memory cell array is disposed in the column decoder region (COL DCR). The column decoder may provide a data transfer path between the page buffer and an external device (e.g., a memory controller).

3 is a plan view of a cell array region CAR of a semiconductor memory device according to embodiments of the present invention. FIG. 4A is a cross-sectional view taken along line A-A 'of FIG. 3, and FIG. 4B is a cross-sectional view taken along line B-B' and C-C 'of FIG. 4C is a cross-sectional view of a peripheral circuit region of a semiconductor memory device according to embodiments of the present invention. 5 is an enlarged view of the area M in Fig.

Referring to FIGS. 3, 4A, 4B, 4C and 5, an electrode structure may be provided on the substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The electrode structure may include first insulating layers 120 and a plurality of electrode layers 145 vertically separated from each other by the first insulating layers 120. The electrode structure may be an area defined by common source lines to be described below, and a plurality of electrode structures may be provided. The lowest layer among the electrode layers 145 may be a lower select gate pattern, and the uppermost layer may be an upper select gate pattern. In one example, the lower selection gate pattern may be a ground selection line, and the upper selection gate pattern may be a string selection line. The gate patterns between the upper and lower selection gate patterns may be cell gate patterns. A buffer insulating layer 105 may be provided between the substrate 100 and the lower select gate pattern to contact the substrate 100. For example, the buffer insulating layer 105 may be a silicon oxide layer. Although the electrode layers 145 are shown to have the same thickness, they may have different thicknesses. For example, the lower selection gate pattern and the upper selection gate pattern may be thicker than the cell gate patterns. The electrode layers 145 may include at least one of doped silicon, metal, metal silicide, or conductive metal nitride.

Although only six electrode layers 145 and the first insulating layers 120 are illustrated, they are omitted for the sake of simplicity. Also, a plurality of upper and lower selection gate patterns may be provided.

Vertical channel structures VP connected to the substrate 100 through the electrode structure may be provided. The vertical channel structures VP may be two-dimensionally arranged on the substrate 100. In this specification, the two-dimensional arrangement may be referred to as being arranged and arranged in a plurality of rows and columns, respectively, along a first direction and a second direction perpendicular to each other in plan view. The vertical channel structures VP may include a plurality of columns extending in a first direction D1 parallel to an upper surface of the substrate 100. The vertical channel structures VP The odd-numbered vertical channel structures VP may be offset from the even-numbered vertical channel structures VP in a second direction D2 intersecting the first direction D1 . That is, the vertical channel structures VP forming one column may be arranged in a zigzag manner along the first direction D1, and the vertical channel structures VP may be arranged from the odd-numbered vertical channel structures VP to adjacent common source lines May be different from the distance from the even vertical channel structures VP to the adjacent common source line.

The vertical channel structures VP include a semiconductor pattern 131 conformally disposed along a side wall and a bottom surface of a through hole passing through the electrode structure, A pattern 115 and a pad pattern 137 provided on the semiconductor pattern 131 to fill the through hole. The semiconductor pattern 131 may be a single layer or a plurality of layers including at least one of silicon, germanium, or silicon-germanium. The buried insulating pattern 115 may include a silicon oxide film or a silicon oxynitride film. The pad pattern 137 may include at least one of a doped semiconductor, a metal, a metal silicide, and a metal nitride.

An information storage layer 143 may be provided between the electrode layers 145 and the semiconductor pattern 131. The information storage layer 143 is formed along the upper and lower surfaces of the electrode layers 145 as well as the sidewalls of the electrode layers 145. Alternatively, And may have a shape that extends. In another embodiment, some of the layers constituting the information storage layer 143 extend along the upper and lower surfaces of the electrode layers 145 as shown in the figure, and the remaining layers extend through the semiconductor pattern 131 Can be vertically extended.

The information storage layer 143 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer sequentially stacked on the electrode layers 145. The blocking insulating layer may include a highly insulating layer such as an aluminum oxide layer or a hafnium oxide layer. The blocking insulating layer may be a multilayer film composed of a plurality of thin films. In this case, as described above, a part of the plurality of thin films constituting the blocking insulating layer may extend along the upper and lower surfaces of the electrode layers 145, and the remaining portions may extend vertically along the semiconductor pattern 131 have. The charge storage film may be an insulating layer including a charge trap film or conductive nanoparticles. In one example, the charge trap film may comprise a silicon nitride film. The tunnel insulating layer may include a silicon oxide layer.

Common source lines CSL1-CSL3 connected to the substrate 100 through the stacked structure may be provided. The common source lines CSL1-CSL3 define the stacked structure and accordingly, a plurality of stacked structures may be provided on the substrate 100 as described above. The common source lines CSL1-CSL3 may have a plate-shaped shape extending along common source regions CSR formed on the substrate 100. In another embodiment, the common source lines CSL1-CSL3 may have a columnar shape. In this case, separate wiring lines for connecting the common source lines having columnar shapes arranged along the first direction D1 can be provided.

The common source regions CSR may be an impurity region of a conductive type different from that of the substrate 100. The common source regions CSR and the common source lines CSL1-CSL3 may extend along the first direction D1. The arrangement and number of the vertical channel structures VP disposed between adjacent common source lines CSL1-CSL3 are not limited to those shown and can be changed.

The common source lines CSL1 to CSL3 may be electrically separated from the electrode layers 145 by the spacer insulating layer 151. [ A barrier film 155 may be provided between the common source lines CSL1 and CSL3 and the spacer insulating film 151. [ The barrier film 155 may extend to the lower surface of the common source lines CSL1 to CSL3.

For example, the common source lines CSL1-CSL3 may include tungsten, but are not limited thereto and include at least one of a conductive material such as copper, titanium, aluminum, doped semiconductor, conductive metal nitride can do. The barrier film 155 may include a metal such as Ti, TiN, and / or a metal nitride film. The spacer insulating layer 151 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

The top surfaces of the common source lines CSL1-CSL3 may be higher than the top surface of the vertical channel structures VP. For example, a first interlayer insulating film 125 is provided to cover the vertical channel structures VP, and the common source lines CSL1-CSL3 pass through the first interlayer insulating film 125, .

Conductive lines ML extending from the vertical channel structures VP onto the common source lines CSL1 to CSL3 may be provided. The conductive lines ML may be electrically connected to the vertical channel structures VP through the channel studs CS. As shown, the channel studs CS may not be provided on some vertical channel structures VP. In this case, the vertical channel structures VP that are not connected to the channel studs CS may constitute part of the dummy cell.

The conductive lines ML may have different lengths extending from the common source lines CSL1-CSL3 depending on the positions of the vertical channel structures VP connected thereto. For example, when the odd-numbered vertical channel structures VP and the even-numbered vertical channel structures VP among the vertical channel structures VP constituting one column are arranged in a zigzag manner, The arrangement of the conductive lines ML extending above the channel structures VP and the conductive lines ML extending above the even vertical channel structures VP may be different from each other. For example, the conductive lines ML extending over the odd-numbered vertical channel structures VP are arranged longer on one side with respect to the second common source line CSL2, and the even- The conductive lines ML extending upward can be arranged longer to the other side opposite to the one side with respect to the second common source line CSL2. That is, the conductive lines ML may have an asymmetrical length with respect to the common source lines CSL1-CSL3.

The conductive lines ML may have an offset region in a portion overlapping the common source lines CSL1-CSL3. That is, the conductive lines ML may include a portion having a center axis spaced from the main center axis passing therethrough. Referring to a pair of common source lines CSL1 and CSL2 adjacent to each other, the conductive lines ML overlapping the first common source line CSL1 are connected to the first common source line CSL1 through the first common source line CSL1, And the conductive lines ML overlapping the second common source line CSL2 have a portion offset in the first direction D1 and antiparallel to the first direction D1 on the second common source line CSL2. And can have offset portions in one direction. The shape of the conductive lines ML is a structure for more easily electrically connecting the vertical channel structures VP adjacent in the second direction D2 to different bit lines to be described below. The conductive lines ML and the channel studs CS may be connected to each other in a dual damascene process in which the conductive lines ML and the channel studs CS overlap each other. So that there is substantially no boundary between the conductive lines ML and the channel studs CS.

The conductive lines ML may extend onto the peripheral circuit region as shown in FIG. 4C. The peripheral circuit region shown in FIG. 4C may be one of the row decoder region (ROW DCR), the page buffer region (PBR), and the column decoder region (COL DCR) in FIG. The conductive lines ML extending over the peripheral circuit region may be connected to the substrate 100 through the peripheral contacts CSP and MP. For example, the peripheral contacts CSP, MP may be connected on the source / drain regions of the transistors on the peripheral circuit region.

Bit lines BL extending in the second direction D2 may be provided on the vertical channel structures VP. Although only the bit lines on the right side of the source strapping line (CSS) will be described below in order to more clearly represent the structure, the bit lines may be arranged in the same manner on the left side of the source strapping line (CSS). Contacts MC may be provided between the bit lines BL and the conductive lines ML. Accordingly, the vertical channel structures VP may be electrically connected to the bit lines BL through the channel studs CS, the conductive lines ML, and the contacts MC. The contacts MC may be arranged along the extending direction of the common source lines CSL1 to CSL3 on the common source lines CSL1 to CSL3. That is, the contacts MC may overlap with the common source lines CSL1-CSL3.

The nearest bit lines (BL) may be connected to the contacts (MC) on different common source lines (CSL1-CSL3). 5, the odd-numbered bit lines BL1 and BL3 are connected to the contacts MC on the first common source line CSL1, and the even-numbered bit lines BL2 and BL3 are connected to the second common source line CSL1. BL4 may be connected to the contacts MC on the second common source line CSL2. As described above, the bit lines BL are electrically connected to the conductive lines ML including portions offset in opposite directions from each other in the first common source line CSL1 and the second common source line CSL2, To the adjacent vertical channel structures (VP). For example, the first vertical channel structure VP1 is electrically connected to the first bit line BL1 through the channel stud CS, the first conductive line ML1, and the contact MC, A second vertical channel structure VP2 spaced apart from the first vertical structure VP1 and the second direction D2 is formed on the channel stud CS, the second conductive line ML2, And may be electrically connected to the first bit line BL1 and the second bit line BL2 closest to the first bit line BL1. Similarly, the third vertical channel structure VP3 is electrically connected to the third bit line BL3 through the channel stud CS, the third conductive line ML3, and the contact MC, The fourth vertical channel structure VP4 spaced apart from the vertical channel structure VP3 in the second direction D2 is connected to the vertical channel structure VP3 through the channel stud CS, the fourth conductive line ML4, And may be electrically connected to the third bit line BL3 and the fourth bit line BL4 closest to the third bit line BL3.

A source strapping line CSS may be provided which is located at the same vertical level as the bit lines BL and electrically connects the common source lines CSL1 to CSL3 to each other. In the present specification, the same vertical level refers to a structure in which the upper surfaces and the lower surfaces are disposed at substantially the same height with respect to the upper surface of the substrate 100. The common source lines CSL1-CSL3 and the common source regions CSR under the common source lines CSL1 and CSL2 may be applied with the same voltage by the source straining line CSS. For example, a ground voltage may be applied to the common source regions CSR.

The source straining line CSS may be provided on one or more cell array areas CAR between adjacent row decoder areas (ROW DCR) (see FIG. 2). In one example, the source straining line (CSS) may be provided on one to five cell array regions.

The width of the source strapping line CSS may be greater than the width of the bit lines BL. In one example, the width of the source strapping line CSS may be about two to about ten times the width of the bit lines BL. The source strapping line CSS may overlap with the plurality of conductive lines ML. Contacts MC of the contacts MC overlapping the source strapping line CSS may be connected to a lower portion of the source strapping line CSS.

The source straining line CSS may be connected to a plurality of contacts MC at a point overlapping with each of the common source lines CSL1-CSL3. The number of the contacts MC connecting the odd-numbered common source lines and the source-strapping line CSS is greater than the number of the even-numbered common source lines and the source strained line CSS May be different from the number of the contacts MC that connect the contacts MC. For example, in the first common source line CSL1 and the second common source line CSL2 disposed on both sides of one electrode structure, the first common source line CSL1 and the source strapping line CSS May be different from the number of the contacts MC connecting the second common source line CSL2 and the source strapping line CSS. For example, the first common source line CSL1 is connected to the source strapping line CSS through two contacts MC while the second common source line CSL2 is connected to three contacts MC, To the source strapping line (CSS).

At the intersection of the common source lines CSL1-CSL3 and the source straining line CSS, source studs CST are provided between the conductive lines ML and the common source lines CSL1-CSL3 . The source studs CST may be connected to a plurality of conductive lines ML overlapping the source strapping line CSS and electrically connect the conductive studs C L to the common source lines CSL 1 to CSL 3. The conductive lines ML and the source studs CST are connected to each other in a dual damascene process, So that there may be substantially no boundary between the conductive lines ML and the source studs CST. The common source regions CSR are connected to the source strapping lines CSL1 through CSL3 via the common source lines CSL1 through CSL3, the source studs CST, the conductive lines ML, 0.0 > CSS). ≪ / RTI >

According to the embodiments of the present invention, a source strapping line CSS, which is electrically connected to a plurality of common source lines CSL1 to CSL3 and capable of applying the same voltage, is horizontally disposed between bit lines BL And vertically on the same level as the bit lines BL, thereby applying a voltage to the common source regions CSR without forming additional conductive lines. The process for manufacturing the semiconductor memory device can be simplified and the vertical height of the semiconductor memory device can be reduced. Also, the placement of the bit lines BL connecting the vertical channel structures VP by the offset conductive lines ML can be optimized. Accordingly, the degree of integration of the semiconductor memory device can be improved.

A method of manufacturing a semiconductor memory device according to embodiments of the present invention is described. 6, 8, 10, 12, 14, and 16 are plan views illustrating a method of manufacturing a semiconductor memory device according to embodiments of the present invention. Figs. 7A, 9A, 11A, 13A, 15A and 17A are cross-sectional views taken along line A-A 'in Figs. 6, 8, 10, 12, 14 and 16, respectively. 7B, 9B, 11B, 13B, 15B and 17B are cross-sectional views taken along lines B-B 'and C-C' in FIGS. 6, 8, 10, 12, Fig.

6, 7A and 7B, a substrate 100 may be provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may have a structure doped with a dopant of the first conductivity type. For example, the first conductivity type may be p-type. A buffer insulating layer 105 may be formed on the substrate 100. The buffer insulating layer 105 may be a silicon oxide layer. The buffer insulating layer 105 may be formed by a thermal oxidation process. The second insulating layers 110 and the first insulating layers 120 may be alternately and repeatedly stacked on the buffer insulating layer 105. The first insulating layers 120 and the second insulating layers 110 may be alternately stacked four or more times. For example, the first insulating layers 120 and the second insulating layers 110 may be alternately stacked 10 or more times. The second insulating layers 110 and the first insulating layers 120 may be selected as mutually etch selectable materials. That is, in the step of etching the second insulating layers 110 using a predetermined etching recipe, the second insulating layers 110 may be etched while minimizing the etching of the first insulating layers 120 Or the like. The etch selectivity may be quantitatively expressed through the ratio of the etching rate of the second insulating layers 110 to the etching rate of the first insulating layers 120. According to one embodiment, the second insulating layers 110 are etched to a thickness of 1: 10 to 1: 200 (more specifically, 1:30 to 1: 100) for the first insulating layers 120 Lt; RTI ID = 0.0 > selectivity. ≪ / RTI > For example, the second insulating layers 110 may be a silicon nitride film, a silicon oxynitride film, or a polysilicon film, and the first insulating layers 120 may be a silicon oxide film. The insulating layers 110 and 120 may be formed by chemical vapor deposition (CVD).

Vertical channel structures VP connected to the substrate 100 through the insulating layers 110 and 120 may be formed. The vertical channel structures VP may be formed two-dimensionally on the substrate 100. For example, the vertical channel structures VP may include a plurality of vertical channel structures VP extending in a first direction D1 parallel to the top surface of the substrate 100 and in a second direction D2 intersecting the first direction. ≪ / RTI > The vertical channel structures VP may be formed in a plurality of regions separated from each other in consideration of positions where common source lines to be described below are arranged. The vertical channel structures VP may include a plurality of columns extending in a first direction D1 parallel to an upper surface of the substrate 100. The vertical channel structures VP The odd-numbered vertical channel structures VP may be offset from the even-numbered vertical channel structures VP in a second direction D2 intersecting the first direction D1 .

The formation of the vertical channel structures VP may include forming through holes passing through the insulating layers 110 and 120 and then forming the semiconductor pattern 131 and the buried insulating pattern 115 in the vertical holes Lt; / RTI > The through holes may be formed by anisotropic etching of the insulating layers 110 and 120. The semiconductor pattern 131 may be conformally formed along sidewalls and bottom surfaces of the through holes, and the buried insulating pattern 115 may be formed to fill the through holes on the semiconductor pattern 131. After the buried insulation pattern 115 and the upper portion of the semiconductor pattern 131 are removed, a pad pattern 137 filling the removed region may be formed. The semiconductor pattern 131 may include at least one of silicon, germanium, or silicon-germanium. In another embodiment, instead of the semiconductor pattern 131, a doped semiconductor, a metal, a conductive metal nitride, a conductive layer such as a silicide, or a nanostructure (such as carbon nanotube or graphene) may be provided. Hereinafter, the semiconductor pattern 131 will be described as a reference for the sake of simplicity. The semiconductor pattern 131 and the buried insulating pattern 115 may be formed by chemical vapor deposition or atomic layer deposition (ALD).

The buried insulating pattern 115 may include a silicon oxide film or a silicon oxynitride film. The pad pattern 137 may include at least one of a doped semiconductor, a metal, a metal silicide, and a metal nitride. After the pad pattern 137 is formed, a first interlayer insulating film 125 may be formed to cover the pad pattern 137. For example, the first interlayer insulating film 125 may include a silicon oxide film or a silicon oxynitride film.

Referring to FIGS. 8, 9A and 9B, a plurality of trenches TR extending in the first direction D1 may be formed between the vertical channel structures VP. The trenches TR may pass through the insulating layers 110 and 120 to expose the upper surface of the substrate 100. [ The second insulation layers 110 where the sidewalls are exposed by the trenches TR may be removed to form the recessed regions 119. That is, the recessed regions 119 may be a region where the second insulating layers 110 are removed. In the case where the second insulating layers 110 include a silicon nitride film or a silicon oxynitride film, the formation of the recessed regions 119 may be performed using an etchant containing phosphoric acid. The recessed regions 119 may expose a part of the sidewall of the semiconductor pattern 131. The second insulating layers 110 may not be entirely removed, and a part of the second insulating layers 110 may remain between the first insulating layers 120.

10, 11A, and 11B, after the information storage layer and the conductive layer are sequentially formed in the recessed regions 119, the information storage layer formed outside the recessed regions 119, A part of the conductive layer may be removed and a plurality of electrode layers 145 and information storage films 143 vertically mutually separated by the first insulating layers 120 may be formed. The electrode layers 145 may completely fill the recessed regions 119 where the data storage layers 143 are formed or may not fill a part of the region adjacent to the trenches TR as shown . The information storage layers 143 may include a tunnel insulating layer, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. In another embodiment, the information storage layers 143 may be a variable resistance pattern. The electrode layers 145 may be formed of at least one of doped silicon, metal, metal silicide, or conductive metal nitride. The blocking insulating layer may include a highly insulating layer such as an aluminum oxide layer or a hafnium oxide layer. The charge storage film may be an insulating layer including a charge trap film or conductive nanoparticles. In one example, the charge trap film may comprise a silicon nitride film. The tunnel insulating layer may include a silicon oxide layer. In the process of forming the information storage layers 143 and the electrode layers 145, the upper portion of the substrate 100 exposed by the trenches TR may be further etched.

Common source regions (CSR) may be formed on top of the substrate 100 exposed by the trenches TR. The common source regions CSR may be regions doped with an impurity of a second conductivity type different from the first conductivity type. In one example, the common source regions (CSR) may be n-type doped regions. The common source regions CSR may be formed after the electrode layers 145 are formed, but are not limited thereto. In another embodiment, the common source regions CSR may be formed after the formation of the trenches TR and before the removal of the second insulating layers 110.

12, 13A and 13B, a spacer insulating film 151 may be formed on the sidewalls of the trenches TR. The spacer insulating layer 151 may be formed to form a conformal insulating layer along the sidewalls and the bottom of the trenches TR and then perform the anisotropic etching process to form the common source regions CSR. The barrier film 155 and the common source lines CSL1 to CSL3 may be formed in the trenches TR partially filled with the spacer insulating film 151. [ The common source lines CSL1-CSL3 may have a flat plate shape extending along the extending direction of the trenches TR. The barrier film 155 may extend to the lower surface of the common source lines CSL1 to CSL3. For example, the common source lines CSL1-CSL3 may include tungsten, but may include at least one of a conductive material such as, but not limited to, a metal such as copper, aluminum, a doped semiconductor, or a conductive metal nitride have. The barrier film 155 may include a metal such as Ti, TiN, and / or a metal nitride film. The spacer insulating layer 151 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Then, a planarization process may be performed to expose the top surfaces of the common source lines CSL1-CSL3.

14, 15A and 15B, second to fourth interlayer insulating films 161 to 163 are sequentially formed on the first interlayer insulating film 125, and then the first to fourth interlayer insulating films 125 , Conductive lines ML, channel studs CS, and source studs CST may be formed in the memory cells 161-163. The channel studs CS may be connected to the top of the vertical channel structures VP and the source studs CST may be connected to the top of the common source lines CSL1 to CSL3. The conductive lines ML may be connected to the channel studs CS or the conductive lines ML and extend on the vertical channel structures VP. For example, the formation of the conductive lines ML, the channel studs CS, and the source studs CST may be performed by a dual damascene process. In this case, the boundary between the conductive lines ML and the channel studs CS and the boundary between the conductive lines ML and the source studs CST may be substantially absent. The channel studs CS may not be formed on some vertical channel structures VP.

16, 17A and 17B, contacts MC may be formed on the common source lines CSL1-CSL3 such that the contacts MC are arranged along the extending direction of the common source lines CSL1-CSL3 have. The contacts MC may be formed so as to penetrate the fifth interlayer insulating film 164 after forming a fifth interlayer insulating film 164 on the fourth interlayer insulating film 163. The contacts MC may be formed to align with the conductive lines ML.

Referring again to FIGS. 3, 4A and 4B, bit lines BL and source strapping lines CSS may be formed on the contacts MC. The bit lines BL and the source strapping lines CSS may be formed by forming a sixth interlayer insulating film 165 on the fifth interlayer insulating film 164 and then passing through the sixth interlayer insulating film 165, And may be formed to connect with the contact MC. The bit lines BL and the source strapping lines CSS may be formed of the same material in the same step.

The interlayer insulating layers 125 and 161-164 may include a silicon oxide layer. The contact MC, the bit lines BL, the conductive lines ML, and the studs CS and CST include a conductive metal nitride film such as a metal such as copper or aluminum and / or a titanium nitride film can do.

According to the embodiments of the present invention, a source strapping line CSS, which is electrically connected to a plurality of common source lines CSL1 to CSL3 and capable of applying the same voltage, is horizontally disposed between bit lines BL And vertically on the same level as the bit lines BL, so that the ground voltage can be commonly applied to the common source regions CSR without a process of forming additional conductive lines. The process for manufacturing the semiconductor memory device can be simplified and the vertical height of the semiconductor memory device can be reduced. Also, the placement of the bit lines BL connecting the vertical channel structures VP by the offset conductive lines ML can be optimized. Accordingly, the degree of integration of the semiconductor memory device can be improved.

18 is a schematic block diagram illustrating an example of a memory system including semiconductor devices formed in accordance with embodiments of the inventive concept.

Referring to Figure 18, an electronic system 1100 according to embodiments of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, (1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved. The memory device 1130 may include a semiconductor device according to embodiments of the present invention.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform functions to transmit data to or receive data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and / or an SLAM device as an operation memory device for improving the operation of the controller 1110. [

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

19 is a schematic block diagram showing an example of a memory card having semiconductor elements formed according to embodiments of the concept of the present invention.

Referring to FIG. 19, the memory card 1200 includes a memory device 1210. The memory device 1210 may include at least one of the semiconductor devices described in the above embodiments. Further, the storage device 1210 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The memory card 1200 may include a memory controller 1220 that controls the exchange of data between the host and the storage device 1210. The storage device 1210 and / or the controller 1220 may comprise semiconductor devices according to embodiments of the present invention.

The memory controller 1220 may include a processing unit 1222 that controls the overall operation of the memory card. In addition, the memory controller 1220 may include an SRAM 1221, which is used as an operation memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225. The host interface 1223 may include a data exchange protocol between the memory card 1200 and a host. The memory interface 1225 can connect the memory controller 1220 and the storage device 1210. Further, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 can detect and correct errors in data read from the storage device 1210. [ Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. The memory card 1200 may be used as a portable data storage card. Alternatively, the memory card 1200 may be implemented as a solid state disk (SSD) capable of replacing a hard disk of a computer system.

20 is a schematic block diagram showing an example of an information processing system equipped with semiconductor devices formed according to embodiments of the concept of the present invention.

Referring to FIG. 20, a flash memory system 1310 according to embodiments of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to embodiments of the present inventive concept includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, , And a user interface (1350). The flash memory system 1310 will be configured substantially the same as the memory system described above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to embodiments of the present invention may be provided with an application chipset, a camera image processor (CIS), an input / output device, It is clear to those who have acquired common knowledge of the field.

In addition, the memory device or memory system according to embodiments of the inventive concept may be implemented in various types of packages. For example, a flash memory device or a memory system according to embodiments of the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Plastic In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP) TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (WFP), a Wafer-Level Processed Stack Package (WSP), and the like.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are illustrative in all aspects and not restrictive.

CSS: Source Strapping Line CS: Channel Stud
CST: Source stud CSR: Common source area
CSL: common source line MC: contact
ML: wiring 145: electrode
143: information storage film 110, 120: insulating film
125, 161-165: Interlayer insulating film VP: Vertical channel structure

Claims (10)

Vertical channel structures arranged two-dimensionally on the substrate and extending vertically from the substrate;
Bit lines connecting the vertical channel structures provided on the vertical channel structures and arranged along a first direction;
A plurality of common source lines extending between the vertical channel structures along a second direction intersecting the first direction; And
And a source strapping line located at the same vertical level as the bit lines and electrically connecting the plurality of common source lines. An electrode structure provided on the substrate and including vertically stacked electrodes;
Vertical channel structures connected to the substrate through the electrode structure;
First and second common source lines located on both sides of the electrode structure to define the electrode structure;
Contacts arranged along the extension direction of the first and second common source lines on the first and second common source lines;
Bit lines extending in an intersection with the first and second common source lines and electrically connected to the vertical channel structures; And
And a source strapping line electrically connecting the first and second common source lines,
Wherein each of the first and second common source lines is connected to the source strapping line via a plurality of the contacts. 3. The method of claim 2,
Wherein the number of contacts connecting the first common source line and the source strapping line is different from the number of contacts connecting the second common source line and the source strapping line. 3. The method of claim 2,
Further comprising conductive lines extending over one of the first and second common source lines from the vertical channel structures,
Wherein the source strapping line is connected to each of the first and second common source lines through a plurality of conductive lines. 3. The method of claim 2,
Odd contacts of the contacts are connected to the bit lines on the first common source line,
And even-numbered contacts of the contacts are connected to the bit lines on the second common source line. 3. The method of claim 2,
And the source strapping line is connected to a plurality of contacts at a point overlapping with each of the first and second common source lines. 3. The method of claim 2,
Further comprising a source stud between the source strapping line and the conductive lines,
And said source stud is commonly connected to said plurality of conductive lines overlapping said source strapping line. 3. The method of claim 2,
Wherein the substrate includes a cell array region and a peripheral circuit region,
And a plurality of source strapping lines are provided on the cell array region. 3. The method of claim 2,
Wherein the source strapping line and the bit lines are located at the same vertical level. 3. The method of claim 2,
Further comprising conductive lines extending over one of the first and second common source lines from the vertical channel structures,
And the conductive lines have offset regions at portions overlapping the common source lines.

Images