CN103326729B - A kind of high-speed coding circuit based on transfer of data - Google Patents
A kind of high-speed coding circuit based on transfer of data Download PDFInfo
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Abstract
The invention discloses a kind of high-speed coding circuit based on transfer of data, mainly solve the problem of existing decoder circuit complexity.Its basic circuit is made up of 16 MOS transistor, S & lt; 1 & gt; With Sv & lt; 1 & gt; , S & lt; 0 & gt; With Sv & lt; 0 & gt; Be two complementary high-low-position address signals, realize correct decoding function by the orderly conducting that controls related transistor with turning off.Basic circuit of the present invention divides upper and lower double-layer structure, wherein introduces NMOS tube M0-M3 in second layer structure, effectively reduces signal voltage swing loss on the transmit path.The present invention has the advantages such as structure is simple, speed is fast, area is little, low in energy consumption, and its advantage can be more obvious along with the increase of decoding address number, can be used for storage address decoding and high-speed data selection circuit.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of decoding circuit, especially a kind of high-speed coding circuit based on transfer of data.
Background technology
Decoder is the important logic module unit of the circuit such as data selection circuit, memory.Along with the progress of integrated circuit (IC) design technology and technology feature size, SOC (system on a chip) scale is increasing, and speed also improves day by day.For multichannel data selection circuit and massive store circuit, the decoder with multidigit address is essential, but traditional multidigit address decoder structure has the shortcomings such as circuit complexity, speed is slow, area is large.Shown in Fig. 1 is traditional 3 line-8 line decoder circuits, and its agent structure is made up of 8 " 3 input nand gates ", comprises 24 NMOS tube and 24 PMOS altogether, and circuit structure more complicated, chip area are comparatively large on the one hand, process costs is high; On the other hand, have 6 (4 PMOS and 2 NMOS tube) with the transistor that each NAND gate output is directly connected, cause output parasitic capacitance comparatively large, circuit speed is not high.
Summary of the invention
The object of the invention is to the shortcoming overcoming above-mentioned prior art, a kind of high-speed coding circuit based on transfer of data is provided, it reduces area by the device count reduced in circuit on the one hand, improve circuit speed by the parasitic capacitance reduced on signal transmission path on the other hand, make chip be issued to more excellent performance at less area.
The object of the invention is to solve by the following technical programs:
This high-speed coding circuit based on transfer of data is specially: this high-speed coding circuit the right and left symmetrically structure, comprise 16 MOS transistor altogether, wherein: nmos pass transistor has N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11, PMOS transistor has P0, P1, P2, P3, P10 and P11; If: S<1> and Sv<1>, S<0> and Sv<0> are two complementary high-low-position address signals, and D<0>, D<1>, D<2> and D<3> are the output signal of decoding circuit;
The grid of the left-half at circuit: PMOS transistor P10 and nmos pass transistor N10 all receives S<1>, and source electrode is connected to VDD-to-VSS respectively, and drain electrode connects the source electrode of PMOS P0 and P1 together; The source ground of NMOS tube N0 and N1; The grid of P0 and N0 and P1 and N1 two pairs of transistors controls by S<0> and Sv<0> respectively, and drain electrode is connected to output D<0> and D<1> respectively; Nmos pass transistor M0 and M1, form transmission gate with PMOS transistor P0 and P1 respectively, the grid of nmos pass transistor M0 and M1 controls by Sv<0> and S<0> respectively;
The grid of the right half part at circuit: PMOS transistor P11 and nmos pass transistor N11 all receives Sv<1>, and source electrode is connected to VDD-to-VSS respectively, and drain electrode connects the source electrode of PMOS P2 and P3 together; The source ground of NMOS tube N2 and N3; The grid of P2 and N2 and P3 and N3 two pairs of transistors controls by S<0> and Sv<0> respectively, and drain electrode is connected to output D<2> and D<3> respectively; Nmos pass transistor M2 and M3, enough becomes transmission gate with PMOS transistor P2 with P3 respectively, and the grid of nmos pass transistor M2 and M3 controls by Sv<0> and S<0> respectively.
Further, above-mentioned nmos pass transistor M0, M1, M2 and M3, enough become transmission gate with PMOS transistor P0, P1, P2 with P3 respectively; Wherein, the source electrode of nmos pass transistor M0, M1, M2 and M3 connects the source electrode of PMOS transistor P0, P1, P2 and P3, and the drain electrode of nmos pass transistor M0, M1, M2 and M3 connects the drain electrode of PMOS transistor P0, P1, P2 and P3.
The above high-speed coding circuit, according to these two complementary address signals of S<1> and Sv<1>, S<0> and Sv<0>, realizes correct decoding function by the orderly conducting controlling related transistor with shutoff.
Further, above-mentioned 16 MOS transistor all take same manufacture craft, and wherein, nmos pass transistor N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11 have same size, PMOS transistor P0, P1, P2, P3, P10 and P11 are made in same N trap, have identical size.
Above-mentioned 16 MOS transistor all take minimum dimension design.
The present invention has following beneficial effect:
Compare existing conventional decoder, circuit structure provided by the invention is simple, and its transistor all can take minimum dimension design, therefore, on whole data transfer path, the parasitic capacitance of each node is less, and not only operating rate is higher, and dynamic power consumption is less.While simplification circuit structure, reduction chip area, reduction production cost, improve circuit performance, the needs that IC industryization is produced can better be met.
Accompanying drawing explanation
Fig. 1 is existing 3 line-8 line tradition decoding circuits;
Fig. 2 is novel decoding circuit structure of the present invention (2 line-4 line);
Fig. 3 is 3 line-8 line decoding circuits expanding acquisition on Fig. 2 basis.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail:
See Fig. 2, the present invention is based on high-speed coding circuit the right and left symmetrically structure of transfer of data, comprise 16 MOS transistor altogether, wherein, nmos pass transistor has N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11, and PMOS transistor has P0, P1, P2, P3, P10 and P11.As figure, if: S<1> and Sv<1>, S<0> and Sv<0> is two complementary high-low-position address signals, D<0>, D<1>, D<2> and D<3> is the output of decoder, below point left-half and right half part are described in detail to circuit connecting relation of the present invention respectively:
The left-half of circuit
The grid of PMOS transistor P10 and NMOS tube N10 all receives S<1>, and source electrode is connected to VDD-to-VSS respectively, and drain electrode connects the source electrode of PMOS P0 and P1 together; The source ground of NMOS tube N0 and N1; The grid of P0 and N0 and P1 and N1 two pairs of transistors controls by S<0> and Sv<0> respectively, and drain electrode is connected to output D<0> and D<1> respectively; Nmos pass transistor M0 and M1, form transmission gate with PMOS transistor P0 and P1 respectively, the grid of nmos pass transistor M0 and M1 controls by Sv<0> and S<0> respectively.
The right half part of circuit
The grid of PMOS transistor P11 and nmos pass transistor N11 all receives Sv<1>, and source electrode is connected to VDD-to-VSS respectively, and drain electrode connects the source electrode of PMOS P2 and P3 together; The source ground of NMOS tube N2 and N3; The grid of P2 and N2 and P3 and N3 two pairs of transistors controls by S<0> and Sv<0> respectively, and drain electrode is connected to output D<2> and D<3> respectively; Nmos pass transistor M2 and M3, enough becomes transmission gate with PMOS transistor P2 with P3 respectively, and the grid of nmos pass transistor M2 and M3 controls by Sv<0> and S<0> respectively.
In order to reduce to export data voltage swing loss on the transmit path, above nmos pass transistor M0, M1, M2 and M3, enough become transmission gate with PMOS transistor P0, P1, P2 with P3 respectively; Wherein, the source electrode of nmos pass transistor M0, M1, M2 and M3 connects the source electrode of PMOS transistor P0, P1, P2 and P3, and the drain electrode of nmos pass transistor M0, M1, M2 and M3 connects the drain electrode of PMOS transistor P0, P1, P2 and P3.
Above-mentioned decoding circuit, according to these two complementary address signals of S<1> and Sv<1>, S<0> and Sv<0>, realizes correct decoding function by the orderly conducting controlling related transistor with shutoff.Such as, when S<1> and S<0> is high level, data transfer path is as shown in signal stray arrow head in Fig. 2, D<3> exports as " 1 ", and D<2:0> exports as " 000 ".The all crystals Guan Jun of decoding circuit takes same manufacture craft, wherein, nmos pass transistor N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11 have same size, PMOS transistor P0, P1, P2, P3, P10 and P11 are made in same N trap, have identical size, all MOS transistor all can take minimum dimension design.
In order to express clearly by the object, technical solutions and advantages of the present invention, below in conjunction with accompanying drawing, the present invention is further described in more detail.At this, embodiments of the invention and explanation are only explanation of the invention, not as a limitation of the invention.
Figure 2 shows that a basic circuit diagram of the present invention, it is 2 line-4 line decoding circuits.Whole circuit comprises two-layer from top to bottom, and left and right two parts symmetrically structure.
Wherein, ground floor is made up of PMOS transistor P10, P11 and nmos pass transistor N10, N11, the grid of P10, N10 controls by high-order decoding address S<1>, and the grid of P11, N11 is controlled by the inversion signal Sv<1> of high-order decoding address.When S<1> is high level " 1 ", when Sv<1> is low level " 0 ", transistor P10, N11 end, and the equal conducting of N10, P11, respectively low level " 0 " and high level " 1 " are delivered to second layer circuit, the two-part input in the left and right respectively as second layer circuit; On the contrary, when S<1> is " 0 ", when Sv<1> is " 1 ", P10, N11 conducting, the two-part input in second layer circuit left and right is respectively " 1 " and " 0 ".
Fig. 2 second layer circuit left and right two parts are identical, for left-half, comprise two PMOS transistor (P0 and P1) and four NMOS tube (N0, N1 and M0, M1).Wherein, when second layer circuit be input as high level " 1 " time, the circuit be made up of P0, P1, N0 and N1 tetra-transistors is all identical in structure with principle with ground floor circuit.When second layer circuit be input as " 0 " time, PMOS P0 or P1 transmit low level time can exist voltage swing loss, for this reason, this part circuit introduces NMOS tube M0 and M1, combines respectively with P0 and P1, forms two transmission gates, efficiently solves above problem.When S<0> is " 1 ", Sv<0> is 0 " time; transistor P0, M0 and N1 end; and the equal conducting of N0, M1 and P1; the low level " 0 " of source electrode is transferred to drain electrode as decoding output D<0> by N0; the input of this part second layer circuit is transferred to output by the transmission gate that M1 and P1 is formed, and exports D<1> as decoding.Connected mode and the operation principle of second layer right half part circuit are identical therewith, are used for producing decoding and export D<2> and D<3>.
To sum up can obtain: as S<1:0>=00, D<3:0>=0001; As S<1:0>=01, D<3:0>=0010; As S<1:0>=10, D<3:0>=0100; As S<1:0>=11, D<3:0>=1000.Release thus: D<0>=Sv<1GreatT. GreaT.GTSv<0>; D<1>=Sv<1GreatT. GreaT.GTS<0>; D<2>=S<1GreatT.G reaT.GTSv<0>; D<3>=S<1GreatT.G reaT.GTS<0>.
Based on the basic circuit of Fig. 2 of the present invention, below provide another kind of embodiment, on the basis of 2 line-4 line decoding circuits, namely expand 3 line-8 line decoding circuit embodiments of acquisition:
This circuit comprises three layers from top to bottom, and left and right two parts symmetrically structure, as shown in Figure 3:
Wherein, ground floor is made up of PMOS transistor P20, P21 and nmos pass transistor N20, N21, the grid of P20 and N20 controls by high-order decoding address S<2>, and the grid of P21 and N21 is controlled by the inversion signal Sv<2> of high-order decoding address.Second layer circuit left and right two parts are identical, for left-half, comprise two PMOS transistor (P10 and P11) and four NMOS tube (N10, N11, M10 and M11).M11, P10 and N10 control by decoding address S<1>, and M10, P11 and N11 are controlled by the inversion signal Sv<1> of S<1>.Circuit two-layer formed above is all identical in structure with principle with 2 line-4 line decoding circuits shown in Fig. 2.The basis of above two-tier circuit is expanded, add third layer structure, the unit module similar to second layer circuit by four is formed, and controls by low level decoding address S<0> and inversion signal Sv<0> thereof.
As S<2:0>=000, D<7:0>=00000001; As S<2:0>=001, D<7:0>=00000010; As S<2:0>=010, D<7:0>=00000100; As S<2:0>=011, D<7:0>=00001000; As S<2:0>=100, D<7:0>=00010000; As S<2:0>=101, D<7:0>=00100000; As S<2:0>=110, D<7:0>=01000000; As S<2:0>=111, D<7:0>=10000000; Release thus: D<0>=Sv<2GreatT. GreaT.GTSv<1>Sv< 0>; D<1>=Sv<2GreatT. GreaT.GTSv<1>S<0 >; D<2>=Sv<2GreatT. GreaT.GTS<1>Sv<0 >; D<3>=Sv<2GreatT. GreaT.GTS<1>S<0G reatT.GreaT.GT; D<4>=S<2GreatT.G reaT.GTSv<1>Sv<0 >; D<5>=S<2GreatT.G reaT.GTSv<1>S<0G reatT.GreaT.GT; D<6>=S<2GreatT.G reaT.GTS<1>Sv<0G reatT.GreaT.GT; D<7>=S<2GreatT.G reaT.GTS<1>S<0Gr eatT.GreaT.GT.
The data transfer path that what in Fig. 3, arrow represented is as S<2:0>=111, D<7> exports as " 1 ", and D<6:0> exports as " 0000000 ".Wherein, signal transmission longest path is the output of D<7> and D<3>, go through 3 MOS transistor, P21, P13 and P7 are gone through in the output of D<7>, and N20, M11 and M3 are gone through in the output of D<3>.
The invention provides the simple decoding circuit of a kind of structure, not only device count is few, and most of metal-oxide-semiconductor all takes minimum dimension design, can reduce chip area, reduce costs.In addition, the parasitic capacitance that circuit exports each node on data transfer path is less, can not only improve operating rate, can also reduce dynamic power consumption.
The above is preferred embodiment of the present invention, and not in order to limit the present invention, every within the spirit and principles in the present invention scope, any equivalent replacement done, retouching and improvement etc., all should be considered as protection scope of the present invention.
Claims (4)
1. the high-speed coding circuit based on transfer of data, it is characterized in that, this high-speed coding circuit the right and left symmetrically structure, comprise 16 MOS transistor altogether, wherein: nmos pass transistor has N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11, PMOS transistor has P0, P1, P2, P3, P10 and P11; If: S<1> and Sv<1>, S<0> and Sv<0> are two complementary high-low-position address signals, and D<0>, D<1>, D<2> and D<3> are the output signal of decoding circuit;
The grid of the left-half at circuit: PMOS transistor P10 and NMOS tube N10 all receives S<1>, and source electrode is connected to VDD-to-VSS respectively, and drain electrode connects the source electrode of PMOS P0 and P1 together; The source ground of NMOS tube N0 and N1; The grid of P0 and N0 and P1 and N1 two pairs of transistors controls by S<0> and Sv<0> respectively, and drain electrode is connected to output D<0> and D<1> respectively; Nmos pass transistor M0 and M1, form transmission gate with PMOS transistor P0 and P1 respectively, the grid of nmos pass transistor M0 and M1 controls by Sv<0> and S<0> respectively;
The grid of the right half part at circuit: PMOS transistor P11 and nmos pass transistor N11 all receives Sv<1>, and source electrode is connected to VDD-to-VSS respectively, and drain electrode connects the source electrode of PMOS P2 and P3 together; The source ground of NMOS tube N2 and N3; The grid of P2 and N2 and P3 and N3 two pairs of transistors controls by S<0> and Sv<0> respectively, and drain electrode is connected to output D<2> and D<3> respectively; Nmos pass transistor M2 and M3, form transmission gate with PMOS transistor P2 and P3 respectively, the grid of nmos pass transistor M2 and M3 controls by Sv<0> and S<0> respectively.
2. the high-speed coding circuit based on transfer of data according to claim 1, is characterized in that, described nmos pass transistor M0, M1, M2 and M3, forms transmission gate respectively with PMOS transistor P0, P1, P2 and P3; Wherein, the source electrode of nmos pass transistor M0, M1, M2 and M3 connects the source electrode of PMOS transistor P0, P1, P2 and P3, and the drain electrode of nmos pass transistor M0, M1, M2 and M3 connects the drain electrode of PMOS transistor P0, P1, P2 and P3.
3. the high-speed coding circuit based on transfer of data according to claim 1, it is characterized in that, this high-speed coding circuit, according to these two complementary address signals of S<1> and Sv<1>, S<0> and Sv<0>, realizes correct decoding function by the orderly conducting controlling related transistor with shutoff.
4. the high-speed coding circuit based on transfer of data according to claim 1, it is characterized in that, described 16 MOS transistor all take same manufacture craft, wherein, nmos pass transistor N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11 have same size, PMOS transistor P0, P1, P2, P3, P10 and P11 are made in same N trap, have identical size.
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| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| CN1983442A (en) * | 2005-12-15 | 2007-06-20 | 松下电器产业株式会社 | Decoder circuit |
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| KR101688598B1 (en) * | 2010-05-25 | 2017-01-02 | 삼성전자주식회사 | Three dimensional semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| CN1983442A (en) * | 2005-12-15 | 2007-06-20 | 松下电器产业株式会社 | Decoder circuit |
Non-Patent Citations (3)
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| 1 模/数转换器结构设计综述;佟星元;《西安邮电大学学报 》;20130310;全文 * |
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