CN103326729A - High-speed decoding circuit based on data transmission - Google Patents
High-speed decoding circuit based on data transmission Download PDFInfo
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- CN103326729A CN103326729A CN2013101827430A CN201310182743A CN103326729A CN 103326729 A CN103326729 A CN 103326729A CN 2013101827430 A CN2013101827430 A CN 2013101827430A CN 201310182743 A CN201310182743 A CN 201310182743A CN 103326729 A CN103326729 A CN 103326729A
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Abstract
The invention discloses a high-speed decoding circuit based on data transmission. The high-speed decoding circuit based mainly solves the problem that a circuit of an existing decoder is complex. A basic circuit of the high-speed decoding circuit is composed of 16 MOS transistors, S (1) and Sv (1), and S (0) and Sv (0) are two complementary high-low phase address selection signals, and the correct decoding function is achieved in a manner that correlated MOS transistors are controlled to be conducted or disconnected sequentially. The basic circuit of the high-speed decoding circuit is divided into an upper structure and a lower structure, M0-M3 NMOS tubes are introduced into the second structure, and therefore voltage swing losses of the signals on a transmission path are reduced effectively. The high-speed decoding circuit has the advantages of being simple in structure, high in speed, small in area, low in power consumption, and the like, in addition, the advantages can be more obvious along with the increase of the number of decoding addresses, and the high-speed decoding circuit can be used for storer address decoding and high-speed data selection circuits.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of decoding circuit, especially a kind of high-speed coding circuit based on transfer of data.
Background technology
Decoder is the important logic module unit of circuit such as data selection circuit, memory.Along with the progress of integrated circuit (IC) design technology and technology characteristics size, the SOC (system on a chip) scale is increasing, and speed also improves day by day.For multichannel data was selected circuit and big capacity storage circuit, the decoder with multidigit address was essential, yet traditional multidigit address decoder structure has shortcomings such as circuit complexity, speed is slow, area is big.Shown in Figure 1 is traditional 3 lines-8 line decoder circuit, and its agent structure is made of 8 " 3 input nand gates ", comprises 24 NMOS pipes and 24 PMOS pipes altogether, on the one hand big, the technology cost height of circuit structure more complicated, chip area; On the other hand, with the transistor that each NAND gate output directly links to each other 6 (4 PMOS pipes and 2 NMOS pipes) are arranged, cause the output parasitic capacitance bigger, circuit speed is not high.
Summary of the invention
The objective of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of high-speed coding circuit based on transfer of data is provided, it reduces area by the device count that reduces in the circuit on the one hand, improve circuit speed by the parasitic capacitance that reduces on the signal transmission path on the other hand, make chip be issued to more excellent performance at littler area.
The objective of the invention is to solve by the following technical programs:
This high-speed coding circuit based on transfer of data is specially: this high-speed coding circuit the right and left is symmetrical structure, comprise 16 MOS transistor altogether, wherein: nmos pass transistor has N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11, and the PMOS transistor has P0, P1, P2, P3, P10 and P11; If: S＜1 with Sv＜1, S＜0 with Sv＜0 be that the high low order address of two complementations is selected signal, D＜0, D＜1, D＜2 and D＜3 be the output signal of decoding circuit;
Left-half at circuit: the grid of PMOS transistor P10 and nmos pass transistor N10 is all received S＜1 〉, source electrode is connected to power supply and ground respectively, and drain electrode connects the source electrode of PMOS pipe P0 and P1 together; The source ground of NMOS pipe N0 and N1; Two pairs of transistorized grids of P0 and N0 and P1 and N1 are subjected to S＜0 respectively〉and Sv＜0 control, drain electrode is connected to output D＜0 respectively〉and D＜1; Nmos pass transistor M0 and M1 constitute transmission gate with PMOS transistor P0 and P1 respectively, and the grid of nmos pass transistor M0 and M1 is subjected to Sv＜0 respectively〉and S＜0 control;
Right half part at circuit: the grid of PMOS transistor P11 and nmos pass transistor N11 is all received Sv＜1 〉, source electrode is connected to power supply and ground respectively, and drain electrode connects the source electrode of PMOS pipe P2 and P3 together; The source ground of NMOS pipe N2 and N3; Two pairs of transistorized grids of P2 and N2 and P3 and N3 are subjected to S＜0 respectively〉and Sv＜0 control, drain electrode is connected to output D＜2 respectively〉and D＜3; Nmos pass transistor M2 and M3 enough become transmission gate with PMOS transistor P2 with P3 respectively, and the grid of nmos pass transistor M2 and M3 is subjected to Sv＜0 respectively〉and S＜0 control.
Further, above-mentioned nmos pass transistor M0, M1, M2 and M3 enough become transmission gate with PMOS transistor P0, P1, P2 and P3 respectively; Wherein, the source electrode of nmos pass transistor M0, M1, M2 and M3 connects the source electrode of PMOS transistor P0, P1, P2 and P3, and the drain electrode of nmos pass transistor M0, M1, M2 and M3 connects the drain electrode of PMOS transistor P0, P1, P2 and P3.
The above high-speed coding circuit is according to S＜1〉with Sv＜1, S＜0 with Sv＜0 these two complementary address signals, the orderly conducting by the control related transistor with turn-off to realize correct decoding function.
Further, above-mentioned 16 MOS transistor are all taked with a kind of manufacture craft, and wherein, nmos pass transistor N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11 have same size, PMOS transistor P0, P1, P2, P3, P10 and P11 are made in the same N trap, have identical size.
Above-mentioned 16 MOS transistor are all taked minimum dimension design.
The present invention has following beneficial effect:
Compare existing conventional decoder, circuit structure provided by the invention is simple, and its transistor all can be taked minimum dimension design, therefore, the parasitic capacitance of each node is less on the whole data transfer path, and not only operating rate is higher, and dynamic power consumption is less.When simplifying circuit structure, reducing chip area, reduce production costs, improved circuit performance, can better satisfy the needs of IC industry production.
Description of drawings
Fig. 1 is existing 3 lines-8 line tradition decoding circuit;
Fig. 2 is novel decoding circuit structure of the present invention (2 lines-4 line);
Fig. 3 is the 3 lines-8 line decoding circuit that obtains in the expansion of Fig. 2 basis.
Embodiment
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Referring to Fig. 2, the high-speed coding circuit the right and left that the present invention is based on transfer of data is symmetrical structure, comprises 16 MOS transistor altogether, wherein, nmos pass transistor has N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11, and the PMOS transistor has P0, P1, P2, P3, P10 and P11.As figure, if: S＜1 with Sv＜1, S＜0 with Sv＜0 be that the high low order address of two complementations is selected signal, D＜0 〉, D＜1, D＜2 and D＜3 be the output of decoder, below branch left-half and right half part are elaborated to circuit connecting relation of the present invention respectively:
The left-half of circuit
The grid of PMOS transistor P10 and NMOS pipe N10 is all received S＜1 〉, source electrode is connected to power supply and ground respectively, and drain electrode connects the source electrode of PMOS pipe P0 and P1 together; The source ground of NMOS pipe N0 and N1; Two pairs of transistorized grids of P0 and N0 and P1 and N1 are subjected to S＜0 respectively〉and Sv＜0 control, drain electrode is connected to output D＜0 respectively〉and D＜1; Nmos pass transistor M0 and M1 constitute transmission gate with PMOS transistor P0 and P1 respectively, and the grid of nmos pass transistor M0 and M1 is subjected to Sv＜0 respectively〉and S＜0 control.
The right half part of circuit
The grid of PMOS transistor P11 and nmos pass transistor N11 is all received Sv＜1 〉, source electrode is connected to power supply and ground respectively, and drain electrode connects the source electrode of PMOS pipe P2 and P3 together; The source ground of NMOS pipe N2 and N3; Two pairs of transistorized grids of P2 and N2 and P3 and N3 are subjected to S＜0 respectively〉and Sv＜0 control, drain electrode is connected to output D＜2 respectively〉and D＜3; Nmos pass transistor M2 and M3 enough become transmission gate with PMOS transistor P2 with P3 respectively, and the grid of nmos pass transistor M2 and M3 is subjected to Sv＜0 respectively〉and S＜0 control.
In order to reduce to export the voltage swing loss of data on transmission path, above nmos pass transistor M0, M1, M2 and M3 enough become transmission gate with PMOS transistor P0, P1, P2 and P3 respectively; Wherein, the source electrode of nmos pass transistor M0, M1, M2 and M3 connects the source electrode of PMOS transistor P0, P1, P2 and P3, and the drain electrode of nmos pass transistor M0, M1, M2 and M3 connects the drain electrode of PMOS transistor P0, P1, P2 and P3.
Above-mentioned decoding circuit is according to S＜1〉with Sv＜1, S＜0 with Sv＜0 these two complementary address signals, the orderly conducting by the control related transistor with turn-off to realize correct decoding function.Such as, when S＜1 and S＜0 when being high level, data transfer path shown in signal stray arrow head among Fig. 2, D＜3〉be output as " 1 ", D＜2:0 be output as " 000 ".The all crystals Guan Jun of decoding circuit takes with a kind of manufacture craft, wherein, nmos pass transistor N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11 have same size, PMOS transistor P0, P1, P2, P3, P10 and P11 are made in the same N trap, have identical size, all MOS transistor all can be taked minimum dimension design.
In order to express the purpose, technical solutions and advantages of the present invention clearer, the present invention is further described in more detail below in conjunction with accompanying drawing.At this, embodiments of the invention and explanation only are explanation of the invention, and be not as a limitation of the invention.
Figure 2 shows that a basic circuit diagram of the present invention, it is 2 lines-4 line decoding circuit.Entire circuit comprises two-layer from top to bottom, and left and right sides two parts are symmetrical structure.
Wherein, ground floor is made of PMOS transistor P10, P11 and nmos pass transistor N10, N11, and the grid of P10, N10 is subjected to high-order decoding address S＜1〉control, the grid of P11, N11 is by inversion signal Sv＜1 of high-order decoding address〉control.When S＜1〉be high level " 1 ", Sv＜1〉when being low level " 0 ", transistor P10, N11 end, and the equal conducting of N10, P11, respectively low level " 0 " and high level " 1 " are delivered to second layer circuit, respectively as the two-part input in the left and right sides of second layer circuit; On the contrary, when S＜1〉be " 0 ", Sv＜1〉when being " 1 ", P10, N11 conducting, the two-part input in the second layer circuit left and right sides is respectively " 1 " and " 0 ".
Fig. 2 second layer circuit left and right sides two parts are identical, are example with the left-half, comprise two PMOS transistors (P0 and P1) and four NMOS pipe (N0, N1 and M0, M1).Wherein, when second layer circuit be input as high level " 1 " time, the circuit that is made of P0, P1, four transistors of N0 and N1 is all identical on structure and principle with the ground floor circuit.When second layer circuit be input as " 0 " time, can there be the voltage swing loss in PMOS pipe P0 or P1 when the transmission low level, for this reason, this part circuit has been introduced NMOS pipe M0 and M1, with P0 and P1 combination, constitutes two transmission gates respectively, efficiently solves above problem.When S＜0〉be " 1 ", Sv＜0〉be 0 " time; transistor P0, M0 and N1 end; and the equal conducting of N0, M1 and P1; N0 is transferred to drain electrode as decoding output D＜0 with the low level " 0 " of source electrode 〉; the transmission gate that M1 and P1 constitute is transferred to output with the input of this part second layer circuit, as decoding output D＜1 〉.Connected mode and the operation principle of second layer right half part circuit are identical therewith, are used for producing decoding output D＜2〉and D＜3.
To sum up can get: as S＜1:0=00 the time, D＜3:0 〉=0001; As S＜1:0 〉=01 the time, D＜3:0 〉=0010; As S＜1:0 〉=10 the time, D＜3:0 〉=0100; As S＜1:0 〉=11 the time, D＜3:0 〉=1000.Release thus: D＜0=Sv＜1〉Sv＜0 〉; D＜1 〉=Sv＜1〉S＜0 〉; D＜2 〉=S＜1〉Sv＜0 〉; D＜3 〉=S＜1〉S＜0 〉.
Based on the basic circuit of Fig. 2 of the present invention, below provide another kind of embodiment, i.e. the 3 lines-8 line decoding circuit embodiment that obtains in the expansion of the basis of 2 lines-4 line decoding circuit:
This circuit comprises three layers from top to bottom, and left and right sides two parts are symmetrical structure, as shown in Figure 3:
Wherein, ground floor is made of PMOS transistor P20, P21 and nmos pass transistor N20, N21, and the grid of P20 and N20 is subjected to high-order decoding address S＜2〉control, the grid of P21 and N21 is by inversion signal Sv＜2 of high-order decoding address〉control.Second layer circuit left and right sides two parts are identical, are example with the left-half, comprise two PMOS transistors (P10 and P11) and four NMOS pipe (N10, N11, M10 and M11).M11, P10 and N10 are subjected to decoding address S＜1〉control, M10, P11 and N11 are by S＜1〉inversion signal Sv＜1 control.More than the two-layer circuit that constitutes all identical on structure and principle with the 2 lines-4 line decoding circuit shown in Fig. 2.Basis in above two-tier circuit is expanded, and has increased three-decker, is made of four unit modules similar to second layer circuit, is subjected to low level decoding address S＜0〉and inversion signal Sv＜0 control.
As S＜2:0 〉=000 the time, D＜7:0 〉=00000001; As S＜2:0 〉=001 the time, D＜7:0 〉=00000010; As S＜2:0 〉=010 the time, D＜7:0 〉=00000100; As S＜2:0 〉=011 the time, D＜7:0 〉=00001000; As S＜2:0 〉=100 the time, D＜7:0 〉=00010000; As S＜2:0 〉=101 the time, D＜7:0 〉=00100000; As S＜2:0 〉=110 the time, D＜7:0 〉=01000000; As S＜2:0 〉=111 the time, D＜7:0 〉=10000000; Release thus: D＜0=Sv＜2〉Sv＜1〉Sv＜0 〉; D＜1 〉=Sv＜2〉Sv＜1〉S＜0 〉; D＜2 〉=Sv＜2〉S＜1〉Sv＜0 〉; D＜3 〉=Sv＜2〉S＜1〉S＜0 〉; D＜4 〉=S＜2〉Sv＜1〉Sv＜0 〉; D＜5 〉=S＜2〉Sv＜1〉S＜0 〉; D＜6 〉=S＜2〉S＜1〉Sv＜0 〉; D＜7 〉=S＜2〉S＜1〉S＜0 〉.
What arrow was represented among Fig. 3 is as S＜2:0 〉=data transfer path 111 time, D＜7〉be output as " 1 ", D＜6:0〉be output as " 0000000 ".Wherein, transmission signal longest path is D＜7〉and D＜3 output, go through 3 MOS transistor, D＜7〉output go through P21, P13 and P7, D＜3 output go through N20, M11 and M3.
The invention provides a kind of decoding circuit simple in structure, not only device count is few, and most of metal-oxide-semiconductor all takes minimum dimension design, can reduce chip area, reduce cost.In addition, the parasitic capacitance of each node is less on the circuit output data transfer path, not only can improve operating rate, can also reduce dynamic power consumption.
The above is preferred embodiment of the present invention, and is in order to limit the present invention, not every within the spirit and principles in the present invention scope, and that does anyly is equal to replacement, retouching and improvement etc., all should be considered as protection scope of the present invention.
Claims (5)
1. high-speed coding circuit based on transfer of data, it is characterized in that, this high-speed coding circuit the right and left is symmetrical structure, comprise 16 MOS transistor altogether, wherein: nmos pass transistor has N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11, and the PMOS transistor has P0, P1, P2, P3, P10 and P11; If: S＜1 with Sv＜1, S＜0 with Sv＜0 be that the high low order address of two complementations is selected signal, D＜0, D＜1, D＜2 and D＜3 be the output signal of decoding circuit;
Left-half at circuit: the grid of PMOS transistor P10 and NMOS pipe N10 is all received S＜1 〉, source electrode is connected to power supply and ground respectively, and drain electrode connects the source electrode of PMOS pipe P0 and P1 together; The source ground of NMOS pipe N0 and N1; Two pairs of transistorized grids of P0 and N0 and P1 and N1 are subjected to S＜0 respectively〉and Sv＜0 control, drain electrode is connected to output D＜0 respectively〉and D＜1; Nmos pass transistor M0 and M1 constitute transmission gate with PMOS transistor P0 and P1 respectively, and the grid of nmos pass transistor M0 and M1 is subjected to Sv＜0 respectively〉and S＜0 control;
Right half part at circuit: the grid of PMOS transistor P11 and nmos pass transistor N11 is all received Sv＜1 〉, source electrode is connected to power supply and ground respectively, and drain electrode connects the source electrode of PMOS pipe P2 and P3 together; The source ground of NMOS pipe N2 and N3; Two pairs of transistorized grids of P2 and N2 and P3 and N3 are subjected to S＜0 respectively〉and Sv＜0 control, drain electrode is connected to output D＜2 respectively〉and D＜3; Nmos pass transistor M2 and M3 enough become transmission gate with PMOS transistor P2 with P3 respectively, and the grid of nmos pass transistor M2 and M3 is subjected to Sv＜0 respectively〉and S＜0 control.
2. the high-speed coding circuit based on transfer of data according to claim 1 is characterized in that, described nmos pass transistor M0, M1, M2 and M3 enough become transmission gate with PMOS transistor P0, P1, P2 and P3 respectively; Wherein, the source electrode of nmos pass transistor M0, M1, M2 and M3 connects the source electrode of PMOS transistor P0, P1, P2 and P3, and the drain electrode of nmos pass transistor M0, M1, M2 and M3 connects the drain electrode of PMOS transistor P0, P1, P2 and P3.
3. the high-speed coding circuit based on transfer of data according to claim 1, it is characterized in that, this high-speed coding circuit is according to S＜1〉with Sv＜1, S＜0 with Sv＜0 these two complementary address signals, the orderly conducting by the control related transistor with turn-off to realize correct decoding function.
4. the high-speed coding circuit based on transfer of data according to claim 1, it is characterized in that, described 16 MOS transistor are all taked with a kind of manufacture craft, wherein, nmos pass transistor N0, N1, N2, N3, M0, M1, M2, M3, N10 and N11 have same size, PMOS transistor P0, P1, P2, P3, P10 and P11 are made in the same N trap, have identical size.
5. the high-speed coding circuit based on transfer of data according to claim 4 is characterized in that, described 16 MOS transistor are all taked minimum dimension design.
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Citations (3)
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2013
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| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| CN1983442A (en) * | 2005-12-15 | 2007-06-20 | 松下电器产业株式会社 | Decoder circuit |
| US20110292731A1 (en) * | 2010-05-25 | 2011-12-01 | Kinam Kim | Three-Dimensional Non-Volatile Memory Devices Having Highly Integrated String Selection and Sense Amplifier Circuits Therein |
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