CN109671460B - Cache circuit and memory for read and write operations - Google Patents

Cache circuit and memory for read and write operations Download PDF

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CN109671460B
CN109671460B CN201811543326.3A CN201811543326A CN109671460B CN 109671460 B CN109671460 B CN 109671460B CN 201811543326 A CN201811543326 A CN 201811543326A CN 109671460 B CN109671460 B CN 109671460B
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CN109671460A (en
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宋金星
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

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Abstract

The invention discloses a cache circuit and a memory for read-write operation, wherein the cache circuit is provided with a first data input and output positive terminal, a first data input and output negative terminal, a second data input and output positive terminal, a second data input and output negative terminal, a first control terminal, a second control terminal and a third control terminal; the cache circuit includes: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor and two switch units. The invention adopts the same circuit structure to realize the write cache operation and the read operation, thereby reducing the cost of the memory; and, through the mechanism of precharging, has shortened the cycle of the read operation, has improved the speed of the read operation of the memorizer.

Description

Cache circuit and memory for read and write operations
Technical Field
The invention belongs to the technical field of cache, and particularly relates to a cache circuit and a memory for read-write operation.
Background
In recent years, with the wide application and upgrade of MCU (single chip microcomputer) and SIM (Subscriber identity Module) cards, the proportion of embedded memories in these systems is increasing, and its performance directly determines the performance of the whole system. Embedded memory systems often include a write channel and a read channel. FIG. 1 shows a portion of a memory, the write channel including a write operation buffer circuit 101. The write operation buffer circuit 101 is provided with a data input positive terminal Din, a data input negative terminal Dinb, a data output positive terminal BL, and a data output negative terminal BLB. The data output positive terminal BL and the data output negative terminal BLB are electrically connected with the memory cell and are used for outputting a pair of differential data signals to the memory cell, the pair of differential data signals represent one bit (bit) data, and the memory cell stores the one bit data. The write cache circuit 101 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a first switch k1, and a second switch k 2. The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the first PMOS transistor MP1, and the second PMOS transistor MP2 form the cache unit 102. During a write operation, the data input positive terminal Din and the data input negative terminal Dinb are used for receiving a pair of differential data signals from the data input port. In a write buffer period of a write operation, the switch control signal CTR is at a low level, and both the first switch k1 and the second switch k2 are turned off. In a write cache cycle of a write operation, the write control signal bkw maintains a high level for a period of time, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on, and data input from the data input port is written into the cache unit 102; then, the write control signal bkw changes to low level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the buffer unit 102 buffers the written data.
The write channel related circuitry in FIG. 1 can only be used for write caching and cannot implement read operations. The read channel of the memory needs to be additionally provided with a relevant circuit, and generally comprises an input buffer, a decoding circuit and a sensitive amplifier, so that the occupied hardware resources are more, and the cost of the memory is increased. In addition, the performance of the memory, especially high speed memory devices, is primarily determined by the read channel. How to increase the read speed in memory design has been a direction of effort for engineers. The read speed is usually increased by increasing the speed of the sense amplifier, which is limited, and the precharge time plus the sense time of the amplifier is usually over 100 ns, i.e. the speed is up to 10 mhz. The read speed of the high-speed memory device in the prior art is not fast enough for 20 mhz SPI (serial peripheral interface) application or 33 mhz embedded application, and cannot meet the requirement.
Disclosure of Invention
The invention aims to overcome the defects that a reading channel of a memory in the prior art occupies more hardware resources and has insufficient reading speed, and provides a low-cost cache circuit for reading and writing operations and a memory.
The invention solves the technical problems through the following technical scheme:
the invention provides a cache circuit for read-write operation, which is provided with a first data input and output positive end, a first data input and output negative end, a second data input and output positive end, a second data input and output negative end, a first control end, a second control end and a third control end;
in the input mode, the first data input output positive terminal and the first data input output negative terminal are used for receiving input differential data from a data input port of the memory; in the output mode, the first data input and output positive terminal and the first data input and output negative terminal are used for outputting differential data to a sensitive amplifier of the memory;
in the input mode, the second data input output positive terminal and the second data input output negative terminal are used for receiving differential data from the storage unit of the memory; in the output mode, the second data input and output positive terminal and the second data input and output negative terminal are used for outputting differential data to the storage units of the memory;
the cache circuit includes: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor and two switch units;
the switch unit is provided with a first data end, a second data end and a switch control end; the switch control ends of the two switch units are electrically connected with the third control end;
the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are electrically connected with the first control end, the drain electrode of the third NMOS tube is electrically connected with the positive end of the first data input and output, and the source electrode of the third NMOS tube is simultaneously electrically connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube and the first data end of the first switch unit;
the drain electrode of the fourth NMOS tube is electrically connected with the negative end of the first data input/output, and the source electrode of the fourth NMOS tube is simultaneously electrically connected with the grid electrode of the second PMOS tube, the grid electrode of the second NMOS tube, the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the first data end of the second switch unit;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both electrically connected with a power supply end;
the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are electrically connected with the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube is electrically connected with the second control end, and the source electrode of the fifth NMOS tube is grounded;
the second data terminal of the first switch unit is electrically connected with the positive second data input/output terminal, and the second data terminal of the second switch unit is electrically connected with the negative second data input/output terminal.
Preferably, the switching unit includes a transmission gate and an inverter; the transmission gate is composed of an NMOS tube and a PMOS tube;
the drain electrode of the NMOS tube and the source electrode of the PMOS tube are electrically connected with the first data end, the source electrode of the NMOS tube and the drain electrode of the PMOS tube are electrically connected with the second data end, the grid electrode of the NMOS tube and the input end of the phase inverter are electrically connected with the switch control end, and the output end of the phase inverter is electrically connected with the grid electrode of the PMOS tube.
Preferably, the NMOS transistor of the switch unit is an enhancement NMOS transistor.
Preferably, in the write buffer period, the first control terminal is at a high level, and the third control terminal and the second control terminal are both at a low level.
Preferably, the read operation cycle comprises a precharge stage, a data read stage, and a data transmit stage in sequence; the data sending stage sequentially comprises a first sub-stage and a second sub-stage;
in the pre-charging stage, the first control end is at a high level, the second control end is at a low level, and the third control end is at a high level;
in the data reading stage, the first control end is at a low level, the second control end is at a high level, and the third control end is at a high level;
in the first sub-stage, the first control end is at a high level, the second control end is at a high level, and the third control end is at a low level;
in the second sub-stage, the first control terminal is at a low level, the second control terminal is at a high level, and the third control terminal is at a low level.
Preferably, the write cache operation cycle sequentially includes a write phase and a cache phase;
in the writing stage, the first control end is at a high level, the second control end is at a high level, and the third control end is at a low level;
in the buffering stage, the first control terminal is at a low level, the second control terminal is at a high level, and the third control terminal is at a low level.
The invention also provides a memory, which is provided with a data input port and a data output port; the memory comprises a storage unit, a sensitive amplifier and a cache circuit for read-write operation;
the first data input and output positive end and the first data input and output negative end are respectively electrically connected with the data input port; the first data input/output positive end is also electrically connected with the positive input end of the sensitive amplifier, and the first data input/output negative end is also electrically connected with the negative input end of the sensitive amplifier;
the output end of the sensitive amplifier is electrically connected with the data output port;
the second data input and output positive terminal and the second data input and output negative terminal are respectively electrically connected with the storage unit.
Preferably, the memory is an EEPROM.
The positive progress effects of the invention are as follows: the invention adopts the same circuit structure to realize the write cache operation and the read operation, thereby reducing the cost of the memory; and, through the mechanism of precharging, has shortened the cycle of the read operation, has improved the speed of the read operation of the memorizer.
Drawings
Fig. 1 is a partial structure diagram of a memory in the prior art.
Fig. 2 is a schematic structural diagram of a cache circuit for read/write operations according to a preferred embodiment of the invention.
FIG. 3 is a timing waveform diagram of a write buffer operation of the buffer circuit for read and write operations according to a preferred embodiment of the present invention.
FIG. 4 is a timing waveform diagram of a read operation of a buffer circuit for read and write operations according to a preferred embodiment of the present invention.
FIG. 5 is a diagram illustrating a memory structure according to a preferred embodiment of the invention.
Detailed Description
The present invention is further illustrated by the following preferred embodiments, but is not intended to be limited thereby.
Referring to fig. 2, the buffer circuit includes a first positive data input/output terminal Dio, a first negative data input/output terminal Diob, a second positive data input/output terminal BL, a second negative data input/output terminal BLB, a first control terminal bkw, a second control terminal sea, and a third control terminal CTR. The positive first data input/output terminal Dio is electrically connected to the positive input terminal of the sense amplifier SA of the memory, the negative first data input/output terminal Diob is electrically connected to the negative input terminal of the sense amplifier SA, and the output terminal of the sense amplifier SA is electrically connected to the data output port 302 of the memory. In the input mode, the first data input output positive terminal Dio and the first data input output negative terminal Diob are used to receive input differential data from the data input port 301 of the memory; in the output mode, the first data input output positive terminal Dio and the first data input output negative terminal Diob are used to output differential data to the sense amplifier of the memory.
In the input mode, the second data input output positive terminal BL and the second data input output negative terminal BLB are used to receive differential data from the memory cells 303 of the memory; in the output mode, the second data input output positive terminal BL and the second data input output negative terminal BLB are used to output differential data to the memory cells 303 of the memory. The memory cell 303 is capable of storing one bit of binary data.
The buffer circuit of the embodiment comprises: the transistor comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first PMOS transistor MP1, a second PMOS transistor MP2 and two switch units, namely a first switch unit SW1 and a second switch unit SW 2.
The two switch units have the same structure and are provided with a first data end, a second data end and a switch control end; the switch control ends of the two switch units are electrically connected with the third control end CTR. Taking the first switch unit SW1 as an example, it includes a transmission gate TG and an inverter INV. The transmission gate TG is composed of an NMOS tube and a PMOS tube. The drain electrode of the NMOS tube and the source electrode of the PMOS tube are electrically connected with a first data end, the source electrode of the NMOS tube and the drain electrode of the PMOS tube are electrically connected with a second data end, the grid electrode of the NMOS tube and the input end of the phase inverter are electrically connected with a switch control end, and the output end of the phase inverter INV is electrically connected with the grid electrode of the PMOS tube.
The gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4 are both electrically connected to the first control terminal bkw, the drain of the third NMOS transistor MN3 is electrically connected to the positive first data input/output terminal Dio, and the source of the third NMOS transistor MN3 is simultaneously electrically connected to the gate of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1, the drain of the second PMOS transistor MP2, the drain of the second NMOS transistor MN2, and the first data terminal of the first switch unit SW 1;
the drain of the fourth NMOS transistor MN4 is electrically connected to the negative data input/output terminal Diob, and the source of the fourth NMOS transistor MN4 is simultaneously electrically connected to the gate of the second PMOS transistor MP2, the gate of the second NMOS transistor MN2, the drain of the first PMOS transistor MP1, the drain of the first NMOS transistor MN1, and the first data terminal of the second switch unit SW 2.
The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both electrically connected to the Power source terminal Power.
The source electrode of the first NMOS transistor MN1 and the source electrode of the second NMOS transistor MN2 are both electrically connected to the drain electrode of the fifth NMOS transistor MN5, the gate electrode of the fifth NMOS transistor MN5 is electrically connected to the second control terminal sea, and the source electrode of the fifth NMOS transistor MN5 is electrically connected to the ground terminal GND.
The second data terminal of the first switching unit SW1 is electrically connected to the second data input/output positive terminal BL, and the second data terminal of the second switching unit SW2 is electrically connected to the second data input/output negative terminal BLB.
The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the first PMOS transistor MP1, and the second PMOS transistor MP2 form the optimized cache unit 202.
As shown in FIG. 3, a write cache operation cycle TwrComprising in sequence a writing phase SwrAnd a caching stage SbufIn a writing stage SwrThe first control terminal bkw is high, the second control terminal SEAN is high, and the third control terminal CTR is low. In a writing stage SwrThe first switch unit SW1 and the second switch unit SW2 are all turned off, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are turned on, and the data inputted from the data input port 301 is written into the optimized cache unit 202.
In a buffer stage SbufThe first control terminal bkw is low, the second control terminal SEAN is high, and the third control terminal CTR is low. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are disconnected, and the optimized cache unit 202 caches the written data.
Refer to the drawings4, read operation period TrdComprising in turn a pre-charging stage SchData reading stage SrData transmission stage Ss。
In a precharge phase SchThe first control terminal bkw is high, the second control terminal SEAN is low, and the third control terminal CTR is high. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both turned on, the fifth NMOS transistor MN5 is turned off, the first switch unit SW1 and the second switch unit SW2 are both turned on, and Dio and Diob are both power supplies with stronger pull-up capability at this time, and precharge the data signals data, data _ b, BL and BLB to the same potential.
In a data read-out phase SrThe first control terminal bkw is low, the second control terminal SEAN is high, and the third control terminal CTR is high. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both turned off, the fifth NMOS transistor MN5 is turned on, since BL and BLB are differential signals, the data signal data is pulled down rapidly by the pull-down current of BL at this time, BLB has no pull-down current, the data signal data _ b remains unchanged at the beginning, along with the drop of the data signal data voltage, the first PMOS transistor MP1 is turned on slowly, the data signal data _ b is pulled up, and due to the effect of positive feedback, the data of BL and BLB is amplified to data and data _ b rapidly, and is stored well.
Data transmission phase SsSequentially comprises a first sub-stage S1And a second sub-phase S2. In a first sub-stage S1The first control terminal bkw is high, the second control terminal SEAN is high, and the third control terminal CTR is low. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both turned on, and the data stored in the optimized cache unit 202 is transmitted to the sense amplifier SA through the first data input/output positive terminal Dio and the first data input/output negative terminal Diob, converted into a single-ended signal by the sense amplifier SA, and then output to the outside through the data output port 302. In a second sub-phase S2The first control terminal bkw is low, the second control terminal SEAN is high, and the third control terminal CTR is low. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both turned off, the data stops being output, and the read operation ends.
The cache circuit for read-write operation of the embodiment is formed by improving the write channel of the memory in the prior art, and the cache circuit for read-write operation can realize the write cache operation and can also perform the read operation by adopting very low cost, so that the related circuit of the original read channel can be omitted, and the cost is reduced.
The buffer circuit for read and write operations of the present embodiment corresponds to a memory cell for storing a one-bit binary number. When the buffer circuit is applied to a memory, the buffer circuits for read-write operation of the embodiment are correspondingly arranged according to the number of the storage units required by the memory. When applied to memory, all data of one page can be pre-read at a time. The pre-read (corresponding to the pre-charge phase S)ch) Is the key to improving the reading speed. When the memory is used, the data input port 301 and the data output port 302 often adopt SPI (Serial Peripheral Interface) interfaces or IIC (Inter-Integrated Circuit bus) interfaces, and instructions of the SPI interfaces or the IIC interfaces are Serial clocks. Therefore, when applied to a memory, data of 8 bytes are read ahead, that is, there is a time of 3 clock cycles for the read-ahead, and then, when the clock frequency is 33 mhz, that is, there is a time of 90 ns for the read-ahead, which is 2.5 clock cycles more than the read operation of the high speed memory device of the prior art. Assuming that the related art high-speed memory device can operate at a clock of 10 mhz at most, the memory having the cache circuit for read and write operations of the present embodiment can operate at 30 mhz or more. Moreover, the number of bytes to be read in advance can be adjusted according to the number of the memory cells, and when the number is larger, the operating frequency of the memory with the cache circuit for read-write operation of the embodiment can be further improved.
The present embodiment also provides a memory, and referring to fig. 5, the memory is provided with a data input port 301 and a data output port 302; the memory includes a memory cell 303, a sense amplifier SA, and a buffer circuit for read and write operations of the present embodiment. The first data input/output positive terminal Dio and the first data input/output negative terminal Diob are electrically connected to the data input port 301, respectively; the first positive data input/output terminal Dio is also electrically connected to the positive input terminal of the sense amplifier, and the first negative data input/output terminal Diob is also electrically connected to the negative input terminal of the sense amplifier. The output of the sense amplifier is electrically connected to the data output port 302. The second data input/output positive terminal BL and the second data input/output negative terminal BLB are electrically connected to the memory cell, respectively. In the memory, the number of the buffer circuits for read/write operations is plural, the number of the storage units 303 is plural, and each buffer circuit for read/write operations and each storage unit 303 are respectively provided correspondingly.
As a preferred embodiment, the memory of the present embodiment is an EEPROM (Electrically erasable and programmable read only memory). The specific structure of the EEPROM and the arrangement manner of the cache circuit for read/write operation in the EEPROM in this embodiment are realized by those skilled in the art in combination with the specification, drawings of the specification, and knowledge in the art, and are not described herein again.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (8)

1. A cache circuit for read-write operation is characterized in that the cache circuit is provided with a first data input and output positive terminal, a first data input and output negative terminal, a second data input and output positive terminal, a second data input and output negative terminal, a first control terminal, a second control terminal and a third control terminal;
in an input mode, the first data input output positive terminal and the first data input output negative terminal are for receiving input differential data from a data input port of a memory; in an output mode, the first positive data input output terminal and the first negative data input output terminal are used for outputting differential data to a sense amplifier of the memory;
in an input mode, the second data input output positive terminal and the second data input output negative terminal are for receiving differential data from the memory cells of the memory; in an output mode, the second data input output positive terminal and the second data input output negative terminal are used for outputting differential data to the memory cells of the memory;
the cache circuit includes: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first switch unit and a second switch unit;
the first switch unit and the second switch unit are respectively provided with a first data end, a second data end and a switch control end; the switch control ends of the first switch unit and the second switch unit are electrically connected with the third control end;
the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are both electrically connected with the first control end, the drain electrode of the third NMOS tube is electrically connected with the positive first data input and output end, and the source electrode of the third NMOS tube is simultaneously electrically connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube and the first data end of the first switch unit;
the drain electrode of the fourth NMOS tube is electrically connected with the negative end of the first data input/output, and the source electrode of the fourth NMOS tube is simultaneously electrically connected with the grid electrode of the second PMOS tube, the grid electrode of the second NMOS tube, the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the first data end of the second switch unit;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both electrically connected with a power supply end;
the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both electrically connected with the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube is electrically connected with the second control end, and the source electrode of the fifth NMOS tube is grounded;
the second data terminal of the first switch unit is electrically connected with the positive second data input/output terminal, and the second data terminal of the second switch unit is electrically connected with the negative second data input/output terminal.
2. The buffer circuit for read and write operations of claim 1, wherein the first switching unit and the second switching unit each comprise a transmission gate and an inverter; the transmission gate is composed of an NMOS tube and a PMOS tube;
the drain electrode of the NMOS tube and the source electrode of the PMOS tube are electrically connected with the first data end, the source electrode of the NMOS tube and the drain electrode of the PMOS tube are electrically connected with the second data end, the grid electrode of the NMOS tube and the input end of the phase inverter are electrically connected with the switch control end, and the output end of the phase inverter is electrically connected with the grid electrode of the PMOS tube.
3. The buffer circuit for read-write operations of claim 2 wherein the NMOS transistors of the first switch unit and the second switch unit are enhancement NMOS transistors.
4. The buffer circuit of claim 1, wherein the first control terminal is high and the third control terminal and the second control terminal are both low during a write buffer cycle.
5. The buffer circuit for read and write operations of claim 1 wherein a read operation cycle comprises, in order, a precharge phase, a data read phase, a data transmit phase; the data sending stage sequentially comprises a first sub-stage and a second sub-stage;
in the pre-charging stage, the first control terminal is at a high level, the second control terminal is at a low level, and the third control terminal is at a high level;
in the data reading stage, the first control terminal is at a low level, the second control terminal is at a high level, and the third control terminal is at a high level;
in the first sub-stage, the first control terminal is at a high level, the second control terminal is at a high level, and the third control terminal is at a low level;
in the second sub-stage, the first control terminal is at a low level, the second control terminal is at a high level, and the third control terminal is at a low level.
6. The cache circuit for read and write operations of claim 1, wherein a write cache cycle comprises a write phase and a cache phase in sequence;
in the write-in phase, the first control terminal is at a high level, the second control terminal is at a high level, and the third control terminal is at a low level;
in the buffering stage, the first control terminal is at a low level, the second control terminal is at a high level, and the third control terminal is at a low level.
7. A memory, characterized in that the memory is provided with a data input port, a data output port; the memory comprises a memory cell, a sense amplifier and a buffer circuit for read and write operations according to any one of claims 1 to 6;
the first data input and output positive end and the first data input and output negative end are respectively electrically connected with the data input port; the first positive data input/output terminal is further electrically connected with the positive input end of the sense amplifier, and the first negative data input/output terminal is further electrically connected with the negative input end of the sense amplifier;
the output end of the sensitive amplifier is electrically connected with the data output port;
the second data input and output positive terminal and the second data input and output negative terminal are respectively electrically connected with the storage unit.
8. The memory of claim 7, wherein the memory is an EEPROM.
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CN102270505A (en) * 2011-06-24 2011-12-07 北京时代全芯科技有限公司 Phase change storage unit and phase change memory

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