CN101814313A

CN101814313A - Single-tube single-capacitor type (1T1C) ferroelectric random access memory (FeRAM)

Info

Publication number: CN101814313A
Application number: CN 201010140458
Authority: CN
Inventors: 贾泽; 张弓; 任天令; 陈弘毅
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2010-04-02
Filing date: 2010-04-02
Publication date: 2010-08-25
Anticipated expiration: 2030-04-02
Also published as: CN101814313B

Abstract

The invention designs a single-tube single-capacitor type (1T1C) ferroelectric random access memory (FeRAM) storing array based on a reading self-reference phase inverter without a reference unit, belonging to the technical field of design and manufacture of integrated circuits. A ferroelectric reference unit in the traditional 1T1C structure FeRAM is removed, and the reading operation is finished by utilizing a self-reference inverting circuit. The FeRAM designed on the basis of the method has favorable fatigue resistant characteristics. In addition, because the ferroelectric reference unit for generating a reference signal is not needed, and a relevant timing sequence control circuit generated by the reference signal can be omitted, the difficulty and the complexity of design are reduced, and the power consumption is lowered.

Description

Single tube single capacitor sections electrical storage

Technical field

The present invention relates to integrated circuit (IC) design manufacturing technology field, relate in particular to a kind of based on the single tube single capacitor sections electrical storage storage array that need not reference unit of reading the self-reference phase inverter.

Background technology

Ferroelectric memory is a kind of novel non-volatile memory device.It utilizes the storage of the spontaneous polarization phenomenon realization two-value data in the ferroelectric material.The cellular construction of single tube single capacitor (1T1C) has been represented the developing direction of high density FeRAM design.

At present, in 1T1C structure FeRAM, the design of reference signal generation circuit is maximum challenge.Traditional reference signal generation circuit mainly contains following two classes: shared ferroelectric reference unit of every row and the shared ferroelectric reference unit of every row.Among the 1T1C FeRAM of the shared ferroelectric reference unit of every row, the fatigue rate of ferroelectric reference unit is fast more a lot of than ferroelectric storage cell, and through behind the read-write operation repeatedly, the accuracy meeting of reference signal seriously descends like this.The 1T1C FeRAM of the shared ferroelectric reference unit of every row can solve the inconsistent problem of fatigue strength, but needs the current mode sense amplifier, and consequently reference signal generation circuit is comparatively complicated, and power consumption, complex time degree and design difficulty all increase greatly.

Summary of the invention

In order to solve the problem that traditional reference signal production method exists among the 1T1C cellular construction FeRAM, the present invention proposes a kind of based on the 1T1C FeRAM storage array that need not reference unit of reading the self-reference phase inverter, it is characterized in that described ferroelectric memory is made up of ferroelectric storage array and sensing circuit two parts;

Wherein, the shared bit lines BLi of pipe single capacitor type storage unit that whenever itemizes of ferroelectric storage array, wherein, i=0...m, every shared word line WLj of capable single tube single capacitor type storage unit and printed line PLj, wherein a j=0...n;

Described sensing circuit is by reading the self-reference phase inverter and sensitive amplifying circuit is formed, and wherein, every row of described ferroelectric storage array connect one and read the self-reference phase inverter, and sense amplifier is connected on described two ends of reading the self-reference phase inverter;

The described self-reference phase inverter of reading is made up of a NMOS pipe M0, the 2nd NMOS pipe M2, PMOS pipe M1 and the 2nd PMOS pipe M3, the grid of the one NMOS pipe M0 is connected on every row shared bit line BLi, i=0...m wherein, the drain electrode of its source electrode and the 2nd NMOS pipe M2 is joined, the output that the drain electrode of its drain electrode and PMOS pipe M1 is joined and read the self-reference phase inverter as described; The grid of the one PMOS pipe M1 also is connected on described this row shared bit line BLi, and the drain electrode of its source electrode and the 2nd PMOS pipe M3 is joined; The grid of the 2nd NMOS pipe M2 and the 2nd PMOS pipe M3 is connected to enable signal Read_en respectively and reaches

The source ground of the 2nd NMOS pipe M2, the source electrode of the 2nd PMOS pipe M3 is connected to power supply vdd_inv.

Described NMOS pipe M0 and PMOS pipe M1 are low threshold mos pipe.

A kind of write operation sequential based on the single tube single capacitor sections electrical storage of reading the self-reference phase inverter is characterized in that the whole operation process is divided into 4 stage T0, T1, T2, T3;

-T0 is in the stage, and precharging signal PRE is a high level, and whole storage array is in pre-charge state;

-T1 is in the stage, and precharging signal PRE becomes low level, and data to be written appear on the bit line BL, and corresponding word line WL signal becomes high level by low level, and storage unit to be operated is in opening;

-T2 is in the stage, and word line WL keeps high level, and under the pulse action of printed line PL signal, data write ferroelectric storage cell;

-T3 is in the stage, and precharging signal PRE becomes high level by low level, and word line WL becomes low level by high level, and storage unit is closed, and write operation finishes.

A kind of read operation sequential based on the single tube single capacitor sections electrical storage of reading the self-reference phase inverter is characterized in that the whole operation process is divided into 5 stage t0, t1, t2, t3, t4;

-t0 is in the stage, and precharging signal PRE is a high level, and storage array is in pre-charge state;

-t1 is in the stage, and precharging signal PRE becomes low level, and corresponding word line WL becomes high level by low level, and printed line PL becomes high level by low level, and the voltage on the bit line BL becomes V0 or V1, depends on that the data of storing in the storage unit are ' 0 ' or ' 1 ';

-t2 read the self-reference phase inverter and enables in the stage, activated sense amplifier then, and data are read from storage unit;

-t3 is in the stage, and printed line PL becomes low level by high level, and data are written back in the storage unit;

-t4 is in the stage, and precharging signal PRE becomes high level by low level, and word line WL signal becomes low level by high level, and read operation finishes.

Compare with traditional 1T1C FeRAM, need not ferroelectric reference unit, have good fatigue resistance based on the 1T1C FeRAM that reads the self-reference phase inverter; In addition, owing to do not need ferroelectric reference unit to produce reference signal, producing relevant sequential control circuit with reference signal can save, and has consequently reduced the difficulty and the complexity of design, has reduced power consumption.

Description of drawings

Below in conjunction with accompanying drawing the present invention is elaborated:

Fig. 1 is based on reading the 1T1C ferroelectric memory framework that the self-reference phase inverter need not reference unit;

Fig. 2 is the write operation sequential of ferroelectric memory;

Fig. 3 is the read operation sequential of ferroelectric memory;

Fig. 4 is the read operation simulation result of ferroelectric memory.

Reference numeral:

The ferroelectric storage array of 1-.

Embodiment

As shown in Figure 1, the ferroelectric storage cell of 1T1C is pressed the ranks proper alignment, and every row of ferroelectric storage array 1 connect one and read the self-reference phase inverter, and sense amplifier is connected on the two ends of negater circuit.By reading the self-reference negater circuit and sensitive amplifying circuit can be finished the operation of reading with write-back.Fig. 1 dotted line block diagram partly represents to read the electrical block diagram of self-reference phase inverter inv, it is made up of two NMOS pipes and two PMOS pipes, Read_en is the enable signal of phase inverter, vdd_inv is the supply voltage of phase inverter, the value of this voltage is a little less than V1, and wherein V1 is that ferroelectric storage cell carries out electric charge with bit line BL stray capacitance when depositing ' 1 ' and shares magnitude of voltage on the bit line of back.Two of horizontal direction lines are represented the input and output of phase inverter in this block diagram.Input is connected to bit line BL, specifically is the magnitude of voltage that reads out from the storage unit the inside, is connected to the output of SA simultaneously.The magnitude of voltage that output is read from storage unit exactly passes through the data behind the phase inverter, is connected to the input of SA simultaneously.Can finish the operation of reading by reading the such connected mode of self-reference negater circuit and sensitive amplifying circuit with write-back.In order to guarantee that this tristate inverter can operate as normal under low voltage, M0 and M1 are the metal-oxide-semiconductor of low threshold value.

As shown in Figure 2, the write operation temporal aspect is: the whole operation process is divided into 4 stages (T0, T1, T2, T3).T0 is in the stage, and PRE is a high level, and whole storage array is in pre-charge state; T1 is in the stage, and precharging signal PRE becomes low level, and data to be written appear on the bit line BL, and corresponding word-line signal WL becomes high level by low level, and storage unit to be operated is in opening; T2 is in the stage, and WL keeps high level, and under the pulse action of PL signal wire, data write ferroelectric storage cell; T3 is in the stage, and PRE becomes high level by low level, and WL becomes low level by high level, and storage unit is closed, and write operation finishes.

As shown in Figure 3, the read operation temporal aspect is: the whole operation process is divided into 5 stages (t0, t1, t2, t3, t4).T0 is in the stage, and PRE is a high level, and whole storage array is in pre-charge state; T1 is in the stage, and PRE becomes low level by high level, and corresponding word-line signal WL becomes high level by low level, and ferroelectric storage cell to be operated is in opening.Because ferroelectric capacitor shows different capacitances under different store statuss, so carry out after electric charge shares with the bit line stray capacitance, the voltage on the data signal line BL becomes V0 or V1 (depending on that the data of storing in the ferroelectric storage cell are ' 0 ' or ' 1 '); T2 is in the stage, and the Read_en signal becomes high level, reads the self-reference phase inverter and enables.Activate sense amplifier then, data are read from ferroelectric storage cell; T3 is in the stage, and pulse signal-line PL becomes low level by high level, and the data of reading are written back to ferroelectric storage cell; T4 is in the stage, and PRE becomes high level by low level, and word-line signal WL becomes low level by high level, and storage unit is closed, and read operation finishes.The simulation result of read operation is seen Fig. 4.

Claims

1. one kind based on the single tube single capacitor sections electrical storage of reading the self-reference phase inverter, it is characterized in that described ferroelectric memory is made up of ferroelectric storage array and sensing circuit two parts;

The described self-reference phase inverter of reading is made up of a NMOS pipe M0, the 2nd NMOS pipe M2, PMOS pipe M1 and the 2nd PMOS pipe M3, the grid of the one NMOS pipe M0 is connected on every row shared bit line BLi, i=0...m wherein, the drain electrode of its source electrode and the 2nd NMOS pipe M2 is joined, the output that the drain electrode of its drain electrode and PMOS pipe M1 is joined and read the self-reference phase inverter as described; The grid of the one PMOS pipe M1 also is connected on described this row shared bit line BLi, and the drain electrode of its source electrode and the 2nd PMOS pipe M3 is joined; The grid of the 2nd NMOS pipe M2 and the 2nd PMOS pipe M3 is connected to enable signal Read_en respectively and reaches The source ground of the 2nd NMOS pipe M2, the source electrode of the 2nd PMOS pipe M3 is connected to power supply vdd_inv.

2. ferroelectric memory as claimed in claim 1 is characterized in that, described NMOS pipe M0 and PMOS pipe M1 are low threshold mos pipe.

3. the write operation sequential based on the single tube single capacitor sections electrical storage of reading the self-reference phase inverter is characterized in that the whole operation process is divided into 4 stage T0, T1, T2, T3;

4. the read operation sequential based on the single tube single capacitor sections electrical storage of reading the self-reference phase inverter is characterized in that the whole operation process is divided into 5 stage t0, t1, t2, t3, t4;