CN103886895A - Time-sequence control circuit of static random access memory (SRAM) - Google Patents
Time-sequence control circuit of static random access memory (SRAM) Download PDFInfo
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- CN103886895A CN103886895A CN201410115159.8A CN201410115159A CN103886895A CN 103886895 A CN103886895 A CN 103886895A CN 201410115159 A CN201410115159 A CN 201410115159A CN 103886895 A CN103886895 A CN 103886895A
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Abstract
The invention discloses a time-sequence control circuit of a static random access memory (SRAM). The time-sequence control circuit comprises an amplifier control circuit, a decoding control circuit and a pre-charge control circuit, wherein the pre-charge control circuit comprises a first phase inverter, a second phase inverter, a third phase inverter and a three-input nor gate; the decoding control circuit comprises a fourth phase inverter, a fifth phase inverter, a sixth phase inverter and a first nand gate; the amplifier control circuit comprises a seventh phase inverter, an eighth phase inverter, a ninth phase inverter and a second nand gate. The time-sequence control circuit is simple and effective as well as easy to implement, and has universality in SRAMs with various structures.
Description
Technical field
The present invention relates to the in-line memory technical field of SIC (semiconductor integrated circuit), be specifically related to a kind of static RAM (Static Random Access Memory, SRAM) sequential control circuit.
Background technology
In-line memory is the key modules of current integrated circuit (Integrated Circuit, IC), is the important component part of SOC (system on a chip) (System-on-Chip, SoC).According to SIA (Semiconductor Industry Association, SIA) prediction, to in-line memory in 2014 in SoC by the chip area that occupies approximately 94%.Therefore, in-line memory will play conclusive effect to the performance of SoC at aspects such as power consumption, speed, stability and integrated levels.Compared with the semiconductor memory of other types on present market, static RAM (SRAM) has advantages of low-power consumption and quick storage data, is widely used in aspect portable consumer electronics and the high-end field such as buffer memory.
As semiconductor memory, stably storing data is the most important functions of SRAM.In stability Design, what first need solution is how to produce timing control signal accurately and effectively.Meanwhile, for keeping its advantage of other storeies relatively, SRAM should have the less access time, can write faster and sense data.SRAM in development, must take into account at a high speed and two of stability aspect.But between speed and stability, be mutual restriction, tend to reduce stability when improving speed, strengthening stability needs to realize by underspeeding.
Summary of the invention
(1) technical matters that will solve
Based on above problem, the present invention proposes a kind of SRAM sequential control circuit just, to guarantee the correctness of SRAM timing control signal in high-speed read-write process, thereby realize high stability.
(2) technical scheme
For achieving the above object, the invention provides a kind of static RAM sequential control circuit, comprise amplifier control circuit 101, decoding control circuit 102 and preliminary filling control circuit 103, wherein: amplifier control circuit 101 is for controlling unlatching or the shutoff of static RAM sense amplifier; Decoding control circuit 102 is for controlling unlatching or the shutoff of static RAM column decode circuitry; Preliminary filling control circuit 103 is for controlling unlatching or the shutoff of static RAM precharging circuit.
In such scheme, described amplifier control circuit 101 is made up of the 7th phase inverter 116, the 8th phase inverter 117, the 9th phase inverter 118 and the second Sheffer stroke gate 110, wherein, the output of the 7th phase inverter 116 connects the input of the 8th phase inverter 117, the output of the 8th phase inverter 117 connects the input of the second Sheffer stroke gate 110, and the output of the second Sheffer stroke gate 110 connects the input of the 9th phase inverter 118.
In such scheme, described decoding control circuit 102 is made up of the 4th phase inverter 113, the 5th phase inverter 114, hex inverter 115 and the first Sheffer stroke gate 109, wherein, the output of the 4th phase inverter 113 connects the input of the 5th phase inverter 114, the output of the 5th phase inverter 114 connects the input of the first Sheffer stroke gate 109, and the output of the first Sheffer stroke gate 109 connects the input of hex inverter 115.
In such scheme, described preliminary filling control circuit 103 is made up of the first phase inverter 110, the second phase inverter 111, the 3rd phase inverter 112 and three input rejection gates 108, wherein, the output of the first phase inverter 110 connects the input of the second phase inverter 111, the output of the second phase inverter 111 connects the input of three input rejection gates 108, and the output of three input rejection gates 108 connects the input of the 3rd phase inverter 112.
In such scheme, described amplifier control circuit 101, described decoding control circuit 102 and described preliminary filling control circuit 103 have a common input pulse signal 104, these pulse signal 104 subject clock signal controls.
In such scheme, the another one input signal of described amplifier control circuit 101 is column decode circuitry enable signals 106 that decoding control circuit 102 is exported, column decode circuitry enable signal 106 is connected the input end of the second Sheffer stroke gate 110 after the 8th phase inverter 117 time delays through the 7th phase inverter 116, pulse signal 104 is directly connected to the input end of the second Sheffer stroke gate 110, and the output end signal of the second Sheffer stroke gate 110 is exported sense amplifier enable signal 105 after the 9th phase inverter 118 drives.
In such scheme, the another one input signal of described decoding control circuit 102 is precharging circuit enable signals 107 that preliminary filling control circuit 103 is exported, precharging circuit enable signal 107 is connected the input end of the first Sheffer stroke gate 109 after the 5th phase inverter 114 time delays through the 4th phase inverter 113, pulse signal 104 directly connects the input end of the first Sheffer stroke gate 109, and the output end signal of the first Sheffer stroke gate 109 is exported column decode circuitry enable signal 106 after hex inverter 115 drives.
In such scheme, two other input signal of described preliminary filling control circuit 103 is respectively the sense amplifier enable signal 105 that the column decode circuitry enable signal 106 exported of decoding control circuit 102 and amplifier control circuit 101 are exported, sense amplifier enable signal 105 is by the first phase inverter 110 and the input end that is connected rejection gate 108 after the second phase inverter 111 time delays, pulse signal 104 and column decode circuitry enable signal 106 are directly connected the input end of rejection gate 108, the output end signal of rejection gate 108 is exported precharging circuit enable signal 107 after the 3rd phase inverter 112 drives.
In such scheme, described sense amplifier enable signal 105 is enable signals of sense amplifier, sense amplifier work when high level, and when low level, sense amplifier is not worked; Described column decode circuitry enable signal 106 is enable signals of column decode circuitry, column decode circuitry work when high level, and when low level, column decode circuitry is not worked; Described precharging circuit enable signal 107 is enable signals of precharging circuit, and when high level, precharging circuit is not worked, and when low level, array neutrality line is charged in advance supply voltage by precharging circuit work.
In such scheme, after described precharging circuit enable signal 107 becomes high level, described column decode circuitry enable signal 106 just can become high level, and after described column decode circuitry enable signal 106 becomes high level, described sense amplifier enable signal 105 just can become high level; After described column decode circuitry enable signal 106 and described sense amplifier enable signal 105 all become low level, described precharging circuit enable signal 107 just can become low level.
(3) beneficial effect
SRAM sequential control circuit provided by the invention is made up of basic phase inverter, Sheffer stroke gate, rejection gate, easily realizes technically.SRAM sequential control circuit provided by the invention, influencing each other and restricting between each output signal, produces and effectively controls sequential.SRAM sequential control circuit provided by the invention is simple in structure, and area is little, in the SRAM of any framework, has versatility.
Accompanying drawing explanation
Fig. 1 is the one-piece construction schematic diagram of existing SRAM;
Fig. 2 is the schematic diagram of SRAM sequential control circuit in Fig. 1;
Fig. 3 is the schematic diagram of SRAM sequential control circuit provided by the invention;
Fig. 4 is the input/output signal waveform schematic diagram of SRAM sequential control circuit provided by the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The read-write operation of SRAM depends on the cooperation between each functional module.Fig. 1 is the one-piece construction schematic diagram of existing SRAM, and this SRAM comprises decoding scheme, cell array, sense amplifier and sequential control circuit.Wherein sequential control circuit is used for receiving external timing signal and control signal, produces the needed timing control signal of inner function module work.Wherein signal 002 is the enable signal of precharging circuit, is used for controlling precharging circuit and when opens or turn-off.Wherein signal 003 is the enable signal of decoding scheme, is used for controlling decoding scheme and when opens or turn-off.Wherein signal 001 is the enable signal of sense amplifier, is used for controlling sense amplifier and when opens or turn-off.The sequential relationship of these three timing control signals has directly affected the duty of SRAM.
Fig. 2 is the schematic diagram of SRAM sequential control circuit in Fig. 1, and this sequential control circuit is by preliminary filling control circuit 304, decoding control circuit 305, and amplifier control circuit 306 forms; Wherein, preliminary filling control circuit 304 is negative edge delay circuits, and it is made up of phase inverter 307, phase inverter 308, resistance 319, nmos pass transistor 313, electric capacity 316.Decoding control circuit 305 is rising edge delay circuits, and it is made up of phase inverter 309, phase inverter 310, resistance 320, PMOS transistor 314, electric capacity 317.Amplifier control circuit 306 is a rising edge delay circuit equally, and it is made up of phase inverter 311, phase inverter 312, resistance 321, PMOS transistor 315, electric capacity 318.304,305,306 have a common input signal 300, and signal 300 is pulse signals of a subject clock signal control.304 output signal is preliminary filling control signal 301, when opens or turn-offs for controlling precharging circuit.305 output signal is encoded control signal 302, when opens or turn-offs for controlling decoding scheme.306 output signal is amplifier control signal 303, when opens or turn-offs for controlling sense amplifier.
SRAM carries out the operation of read and write in normal operation, while starting to operate, should first turn-off precharging circuit, opens afterwards decoding scheme, finally opens sense amplifier; When end operation, should first turn-off decoding scheme and sense amplifier, then open precharging circuit.If modules can not, according to above-mentioned sequential working, will likely cause SRAM to occur the mistake of read and write.In the circuit shown in Fig. 2, control the sequential relationship between each output signal by the numerical value of control capacittance and resistance just, to meet the demand of the correct read-write of SRAM.But the impact that the circuit shown in Fig. 2 is risen and fallen by voltage fluctuation, temperature variation, technique easily, causes producing between each signal wrong sequential relationship.
Fig. 3 is the schematic diagram of SRAM sequential control circuit provided by the invention, and this SRAM sequential control circuit comprises amplifier control circuit 101, decoding control circuit 102 and preliminary filling control circuit 103.Wherein, amplifier control circuit 101 is for controlling unlatching or the shutoff of static RAM sense amplifier.Decoding control circuit 102 is for controlling unlatching or the shutoff of static RAM column decode circuitry.Preliminary filling control circuit 103 is for controlling unlatching or the shutoff of static RAM precharging circuit.
Preliminary filling control circuit 103 is made up of the first phase inverter 110, the second phase inverter 111, the 3rd phase inverter 112 and three input rejection gates 108; Wherein, the output of the first phase inverter 110 connects the input of the second phase inverter 111, and the output of the second phase inverter 111 connects the input of three input rejection gates 108, and the output of three input rejection gates 108 connects the input of the 3rd phase inverter 112.
Preliminary filling control circuit 103, decoding control circuit 102, amplifier control circuit 101 have a common input pulse signal 104, pulse signal 104 subject clock signal controls.Two other input signal of preliminary filling control circuit 103 is respectively the sense amplifier enable signal 105 that the column decode circuitry enable signal 106 exported of decoding control circuit 102 and amplifier control circuit 101 are exported, sense amplifier enable signal 105 is by the first phase inverter 110 and the input end that is connected rejection gate 108 after the second phase inverter 111 time delays, and pulse signal 104 and column decode circuitry enable signal 106 are directly connected the input end of rejection gate 108; The another one input signal of decoding control circuit 102 is precharging circuit enable signals 107 that preliminary filling control circuit 103 is exported, precharging circuit enable signal 107 is connected the input end of the first Sheffer stroke gate 109 after the 5th phase inverter 114 time delays through the 4th phase inverter 113, pulse signal 104 directly connects the input end of the first Sheffer stroke gate 109; The another one input signal of amplifier control circuit 101 is column decode circuitry enable signals 106 that decoding control circuit 102 is exported, column decode circuitry enable signal 106 is connected the input end of the second Sheffer stroke gate 110 after the 8th phase inverter 117 time delays through the 7th phase inverter 116, pulse signal 104 is directly connected to the input end of the second Sheffer stroke gate 110.
The output end signal of rejection gate 108 is exported precharging circuit enable signal 107 after the 3rd phase inverter 112 drives; The output end signal of the first Sheffer stroke gate 109 is exported column decode circuitry enable signal 106 after hex inverter 115 drives; The output end signal of the second Sheffer stroke gate 110 is exported sense amplifier enable signal 105 after the 9th phase inverter 118 drives.
SRAM sequential control circuit shown in Fig. 3, can realize and under any circumstance all export correct timing control signal.Wherein precharging circuit enable signal 107 is enable signals of precharging circuit, and when high level, precharging circuit is not worked, and when low level, array neutrality line is charged in advance supply voltage by precharging circuit work.Column decode circuitry enable signal 106 is enable signals of column decode circuitry, column decode circuitry work when high level, and when low level, column decode circuitry is not worked.Sense amplifier enable signal 105 is enable signals of sense amplifier, sense amplifier work when high level, and when low level, sense amplifier is not worked.After precharging circuit enable signal 107 becomes high level, column decode circuitry enable signal 106 just can become high level, and after column decode circuitry enable signal 106 becomes high level, sense amplifier enable signal 105 just can become high level.Similarly, after column decode circuitry enable signal 106 and sense amplifier enable signal 105 all become low level, precharging circuit enable signal 107 just can become low level.Guarantee the under any circumstance correctness of timing control signal by the mutual restricting relation that influences each other between these three signals just.
Fig. 4 has provided input signal and the signal output waveform of general SRAM sequential control circuit.Wherein input signal 200 is pulse signals of a subject clock signal control, precharging circuit enable signal 201 is used for controlling precharging circuit and when opens or turn-off, decoding scheme enable signal 202 is used for controlling decoding scheme and when opens or turn-off, and sense amplifier enable signal 203 is used for controlling sense amplifier and when opens or turn-off.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a static RAM sequential control circuit, is characterized in that, comprises amplifier control circuit (101), decoding control circuit (102) and preliminary filling control circuit (103), wherein:
Amplifier control circuit (101) is for controlling unlatching or the shutoff of static RAM sense amplifier;
Decoding control circuit (102) is for controlling unlatching or the shutoff of static RAM column decode circuitry;
Preliminary filling control circuit (103) is for controlling unlatching or the shutoff of static RAM precharging circuit.
2. static RAM sequential control circuit according to claim 1, it is characterized in that, described amplifier control circuit (101) is by the 7th phase inverter (116), the 8th phase inverter (117), the 9th phase inverter (118) and the second Sheffer stroke gate (110) form, wherein, the output of the 7th phase inverter (116) connects the input of the 8th phase inverter (117), the output of the 8th phase inverter (117) connects the input of the second Sheffer stroke gate (110), the output of the second Sheffer stroke gate (110) connects the input of the 9th phase inverter (1118).
3. static RAM sequential control circuit according to claim 1, it is characterized in that, described decoding control circuit (102) is by the 4th phase inverter (113), the 5th phase inverter (114), hex inverter (115) and the first Sheffer stroke gate (109) form, wherein, the output of the 4th phase inverter (113) connects the input of the 5th phase inverter (114), the output of the 5th phase inverter (114) connects the input of the first Sheffer stroke gate (109), the output of the first Sheffer stroke gate (109) connects the input of hex inverter (115).
4. static RAM sequential control circuit according to claim 1, it is characterized in that, described preliminary filling control circuit (103) is by the first phase inverter (110), the second phase inverter (111), the 3rd phase inverter (112) and three input rejection gates (108) form, wherein, the output of the first phase inverter (110) connects the input of the second phase inverter (111), the output of the second phase inverter (111) connects the input of three input rejection gates (108), the output of three input rejection gates (108) connects the input of the 3rd phase inverter (112).
5. static RAM sequential control circuit according to claim 1, it is characterized in that, described amplifier control circuit (101), described decoding control circuit (102) and described preliminary filling control circuit (103) have a common input pulse signal (104), this pulse signal (104) subject clock signal control.
6. static RAM sequential control circuit according to claim 5, it is characterized in that, the another one input signal of described amplifier control circuit (101) is the column decode circuitry enable signal (106) of decoding control circuit (102) output, column decode circuitry enable signal (106) is connected the input end of the second Sheffer stroke gate (110) after the 8th phase inverter (117) time delay through the 7th phase inverter (116), pulse signal (104) is directly connected to the input end of the second Sheffer stroke gate (110), the output end signal of the second Sheffer stroke gate (110) is output sense amplifier enable signal (105) after the 9th phase inverter (118) drives.
7. static RAM sequential control circuit according to claim 5, it is characterized in that, the another one input signal of described decoding control circuit (102) is the precharging circuit enable signal (107) of preliminary filling control circuit (103) output, precharging circuit enable signal (107) is connected the input end of the first Sheffer stroke gate (109) after the 5th phase inverter (114) time delay through the 4th phase inverter (113), pulse signal (104) directly connects the input end of the first Sheffer stroke gate (109), the output end signal of the first Sheffer stroke gate (109) is output column decode circuitry enable signal (106) after hex inverter (115) drives.
8. static RAM sequential control circuit according to claim 5, it is characterized in that, two other input signal of described preliminary filling control circuit (103) is respectively the column decode circuitry enable signal (106) of decoding control circuit (102) output and the sense amplifier enable signal (105) of amplifier control circuit (101) output, sense amplifier enable signal (105) is by the first phase inverter (110) and the input end that is connected rejection gate (108) after the second phase inverter (111) time delay, pulse signal (104) and column decode circuitry enable signal (106) are directly connected the input end of rejection gate (108), the output end signal of rejection gate (108) is output precharging circuit enable signal (107) after the 3rd phase inverter (112) drives.
9. static RAM sequential control circuit according to claim 8, is characterized in that,
Described sense amplifier enable signal (105) is the enable signal of sense amplifier, sense amplifier work when high level, and when low level, sense amplifier is not worked;
Described column decode circuitry enable signal (106) is the enable signal of column decode circuitry, column decode circuitry work when high level, and when low level, column decode circuitry is not worked;
Described precharging circuit enable signal (107) is the enable signal of precharging circuit, and when high level, precharging circuit is not worked, and when low level, array neutrality line is charged in advance supply voltage by precharging circuit work.
10. static RAM sequential control circuit according to claim 8 or claim 9, is characterized in that,
After described precharging circuit enable signal (107) becomes high level, described column decode circuitry enable signal (106) just can become high level, and after described column decode circuitry enable signal (106) becomes high level, described sense amplifier enable signal (105) just can become high level;
After described column decode circuitry enable signal (106) and described sense amplifier enable signal (105) all become low level, described precharging circuit enable signal (107) just can become low level.
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Cited By (3)
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| CN104882158A (en) * | 2015-05-25 | 2015-09-02 | 清华大学 | Programmable static random access memory synchronous clock control module circuit |
| CN105304121A (en) * | 2014-07-31 | 2016-02-03 | 展讯通信（上海）有限公司 | Central management control circuit of SRAM |
| CN105336361A (en) * | 2015-12-04 | 2016-02-17 | 安徽大学 | SRAM self-tracking copy bit line circuit |
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| CN101034585A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | SRAM system circuit without sensitive amplifier |
| CN101131999A (en) * | 2006-08-25 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and testing method of same |
| CN102664041A (en) * | 2012-05-22 | 2012-09-12 | 安徽大学 | Programmable SRAM (static random Access memory) time sequence control system based on BIST (built-in self-test) control |
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2014
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| US20050213404A1 (en) * | 2004-03-25 | 2005-09-29 | Fujitsu Limited | Semiconductor memory device and precharge control method |
| CN101034585A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | SRAM system circuit without sensitive amplifier |
| CN101131999A (en) * | 2006-08-25 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and testing method of same |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304121A (en) * | 2014-07-31 | 2016-02-03 | 展讯通信（上海）有限公司 | Central management control circuit of SRAM |
| CN104882158A (en) * | 2015-05-25 | 2015-09-02 | 清华大学 | Programmable static random access memory synchronous clock control module circuit |
| CN104882158B (en) * | 2015-05-25 | 2017-10-31 | 清华大学 | A kind of programmable SRAM synchronised clock control module circuit |
| CN105336361A (en) * | 2015-12-04 | 2016-02-17 | 安徽大学 | SRAM self-tracking copy bit line circuit |
| CN105336361B (en) * | 2015-12-04 | 2018-07-27 | 安徽大学 | A kind of SRAM autotrackings duplication bit line circuit |
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