CN103886895B - A kind of static RAM sequential control circuit - Google Patents
A kind of static RAM sequential control circuit Download PDFInfo
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- CN103886895B CN103886895B CN201410115159.8A CN201410115159A CN103886895B CN 103886895 B CN103886895 B CN 103886895B CN 201410115159 A CN201410115159 A CN 201410115159A CN 103886895 B CN103886895 B CN 103886895B
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Abstract
The invention discloses a kind of static RAM sequential control circuit, including amplifier control circuit, decoding control circuit and preliminary filling control circuit, wherein, preliminary filling control circuit is made up of the first phase inverter, the second phase inverter, the 3rd phase inverter and three input nor gates；Decoding control circuit is made up of the 4th phase inverter, the 5th phase inverter, hex inverter and the first NAND gate；Amplifier control circuit is made up of the 7th phase inverter, the 8th phase inverter, the 9th phase inverter and the second NAND gate.The circuit is simply effective, easily realizes, has versatility in the SRAM of various frameworks.
Description
Technical field
The present invention relates to the in-line memory technical field of semiconductor integrated circuit, and in particular to a kind of static random is deposited
Access to memory (Static Random Access Memory, SRAM) sequential control circuit.
Background technology
In-line memory is the key modules of contemporary integrated circuits (Integrated Circuit, IC), is to be on piece
The important component part of system (System-on-Chip, SoC).According to SIA (Semiconductor
Industry Association, SIA) prediction, about 94% chip face will be occupied in SoC to in-line memory in 2014
Product.Therefore, the performance to SoC is played conclusive at aspects such as power consumption, speed, stability and integrated levels by in-line memory
Effect.Compared with other kinds of semiconductor memory currently on the market, static RAM (SRAM) is with low work(
Consumption and flash storage data advantage, in terms of portable consumer electronics and caching etc. high-end field be widely used.
Used as semiconductor memory, stably data storage is the most important functions of SRAM.In stability Design, first
Need solution is how to produce accurately and effectively timing control signal.Meanwhile, it is the advantage for keeping its relative other memorizer,
SRAM should have less access time, can write faster and read data.SRAM must take into account in development at a high speed and
Two aspects of stability.But it is mutually restriction between speed and stability, while improving speed, often reduces stable
Property, and enhanced stability then needs by reducing speed to realize.
The content of the invention
(1) technical problem to be solved
Problem above is based on, the present invention proposes a kind of SRAM sequential control circuits, to ensure in high-speed read-write mistake
The correctness of SRAM timing control signals in journey, so as to realize high stability.
(2) technical scheme
To reach above-mentioned purpose, the invention provides a kind of static RAM sequential control circuit, including putting
Big device control circuit 101, decoding control circuit 102 and preliminary filling control circuit 103, wherein：Amplifier control circuit 101 is used to control
In static RAM processed, sense amplifier is on or off；Decoding control circuit 102 be used to controlling it is static with
In machine access memorizer, row decoding circuit is on or off；Preliminary filling control circuit 103 is deposited for controlling static random-access
In reservoir, precharging circuit is on or off.
In such scheme, the amplifier control circuit 101 is anti-by the 7th phase inverter 116, the 8th phase inverter the 117, the 9th
Phase device 118 and the second NAND gate 110 are constituted, wherein, the output of the 7th phase inverter 116 connects the input of the 8th phase inverter 117, the
The output of eight phase inverters 117 connects the input of the second NAND gate 110, and the output of the second NAND gate 110 connects the defeated of the 9th phase inverter 118
Enter.
In such scheme, the decoding control circuit 102 is anti-phase by the 4th phase inverter 113, the 5th phase inverter the 114, the 6th
Device 115 and the first NAND gate 109 are constituted, wherein, the output of the 4th phase inverter 113 connects the input of the 5th phase inverter 114, and the 5th
The output of phase inverter 114 connects the input of the first NAND gate 109, and the output of the first NAND gate 109 connects the defeated of hex inverter 115
Enter.
In such scheme, the preliminary filling control circuit 103 is anti-phase by the first phase inverter 110, the second phase inverter the 111, the 3rd
Device 112 and three input nor gates 108 are constituted, wherein, the output of the first phase inverter 110 connects the input of the second phase inverter 111, the
The output of two phase inverters 111 connects the input of three input nor gates 108, and the output of three input nor gates 108 connects the 3rd phase inverter 112
Input.
In such scheme, the amplifier control circuit 101, the decoding control circuit 102 and preliminary filling control electricity
Road 103 has a common input pulse signal 104, and 104 subject clock signal of pulse signal is controlled.
In such scheme, another input signal of the amplifier control circuit 101 is that decoding control circuit 102 is defeated
The row decoding circuit for going out enables signal 106, and row decoding circuit enables signal 106 through the 7th phase inverter 116 and the 8th phase inverter
Connect the input of the second NAND gate 110 after 117 time delays, pulse signal 104 is directly connected to the input of the second NAND gate 110
End, the output end signal of the second NAND gate 110 Jing after the driving of the 9th phase inverter 118 export sense amplifier and enable signal 105.
In such scheme, another input signal of the decoding control circuit 102 is that preliminary filling control circuit 103 is exported
Precharging circuit enable signal 107, precharging circuit enable signal 107 through the 4th phase inverter 113 and 114 time delay of the 5th phase inverter
Connect the input of the first NAND gate 109 afterwards, pulse signal 104 is directly connected to the input of the first NAND gate 109, first with it is non-
The output end signal of door 109 Jing after the driving of hex inverter 115 exports row decoding circuit and enables signal 106.
In such scheme, two other input signal of the preliminary filling control circuit 103 is decoding control circuit 102 respectively
The row decoding circuit of output enables signal 106 and the sense amplifier of the output of amplifier control circuit 101 enables signal 105, spirit
Quick amplifier enables the input that signal 105 connects nor gate 108 after 111 time delay of the first phase inverter 110 and the second phase inverter
End, pulse signal 104 and row decoding circuit enable the input that signal 106 is directly connected to nor gate 108, nor gate 108 it is defeated
Go out end signal and precharging circuit enable signal 107 is exported Jing after the driving of the 3rd phase inverter 112.
In such scheme, the sense amplifier enables the enable signal that signal 105 is sense amplifier, spirit during high level
Quick amplifier operation, during low level, sense amplifier does not work；It is row decoding circuit that the row decoding circuit enables signal 106
Signal is enabled, row decoding circuit work during high level, during low level, row decoding circuit does not work；The precharging circuit enables signal
107 is the enable signal of precharging circuit, and during high level, precharging circuit does not work, and during low level, precharging circuit works array middle position
Line is charged to supply voltage in advance.
In such scheme, the precharging circuit enables the row decoding circuit after signal 107 becomes high level and enables signal
106 can just become high level, and the row decoding circuit enables the sense amplifier after signal 106 becomes high level and enables signal
105 can just become high level；The row decoding circuit enables signal 106 and the sense amplifier enables signal 105 and all becomes
After low level, the precharging circuit enable signal 107 can just become low level.
(3) beneficial effect
The SRAM sequential control circuits that the present invention is provided are made up of basic phase inverter, NAND gate, nor gate, technically
Easily realize.The SRAM sequential control circuits that the present invention is provided, influencing each other between each output signal and restrict, and have
The control sequential of effect.The SRAM sequential control circuit simple structures that the present invention is provided, area are little, have in the SRAM of any framework
There is versatility.
Description of the drawings
Fig. 1 is the overall structure diagram of existing SRAM；
Fig. 2 is the schematic diagram of SRAM sequential control circuits in Fig. 1；
The schematic diagram of the SRAM sequential control circuits that Fig. 3 is provided for the present invention；
The input/output signal waveform diagram of the SRAM sequential control circuits that Fig. 4 is provided for the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
The read-write operation of SRAM depends on the cooperation between each functional module.Fig. 1 is the overall structure of existing SRAM
Schematic diagram, the SRAM include decoding circuit, cell array, sense amplifier and sequential control circuit.Wherein sequential control circuit
For receiving external timing signal and control signal, the timing control signal required for inner function module work is produced.Wherein
Signal 002 is the enable signal of precharging circuit, when on or off for controlling precharging circuit.Wherein signal 003 is to translate
The enable signal of code circuit, it is when on or off for controlling decoding circuit.Wherein signal 001 is making for sense amplifier
Energy signal, it is when on or off for controlling sense amplifier.The direct shadow of sequential relationship of these three timing control signals
The working condition of SRAM is rung.
Schematic diagrams of the Fig. 2 for SRAM sequential control circuits in Fig. 1, the sequential control circuit are translated by preliminary filling control circuit 304
Code control circuit 305, amplifier control circuit 306 are constituted；Wherein, preliminary filling control circuit 304 is a trailing edge delay circuit,
It is made up of phase inverter 307, phase inverter 308, resistance 319, nmos pass transistor 313, electric capacity 316.Decoding control circuit 305 is one
Individual rising edge delay circuit, it is made up of phase inverter 309, phase inverter 310, resistance 320, PMOS transistor 314, electric capacity 317.Put
Big device control circuit 306 is equally a rising edge delay circuit, and it is by phase inverter 311, phase inverter 312, resistance 321, PMOS
Transistor 315, electric capacity 318 are constituted.304th, 305,306 have a common input signal 300, and signal 300 is one by clock
The pulse signal of signal control.304 output signal is preliminary filling control signal 301, for control precharging circuit when open or
Person turns off.305 output signal is encoded control signal 302, when on or off for controlling decoding circuit.306
Output signal is amplifier control signal 303, when on or off for controlling sense amplifier.
SRAM performs the operation read and write in normal operation, starts to turn off precharging circuit first during operation, it
After open decoding circuit, finally open sense amplifier；Decoding circuit and sense amplifier are turned off during end operation first should, then
Open precharging circuit.If modules can not be according to above-mentioned sequential working, it would be possible to cause SRAM to occur what is read and write
Mistake.In the circuit shown in Fig. 2, be exactly based on adjust the numerical value of electric capacity and resistance control between each output signal when
Order relation, to meet the demand that SRAM correctly reads and writes.But the circuit shown in Fig. 2 easily receives voltage pulsation, temperature change, technique
The impact of fluctuating, causes to produce the sequential relationship of mistake between each signal.
The schematic diagram of the SRAM sequential control circuits that Fig. 3 is provided for the present invention, the SRAM sequential control circuits include amplifying
Device control circuit 101, decoding control circuit 102 and preliminary filling control circuit 103.Wherein, amplifier control circuit 101 is used to control
In static RAM, sense amplifier is on or off.Decoding control circuit 102 is used to control static random
In access memorizer, row decoding circuit is on or off.Preliminary filling control circuit 103 is used to control static random access memory
In device, precharging circuit is on or off.
Amplifier control circuit 101 is by the 7th phase inverter 116, the 8th phase inverter 117, the 9th phase inverter 118 and second
NAND gate 110 is constituted；Wherein, the output of the 7th phase inverter 116 connects the input of the 8th phase inverter 117, the 8th phase inverter 117 it is defeated
Go out the input for connecing the second NAND gate 110, the output of the second NAND gate 110 connects the input of the 9th phase inverter 118.
Decoding control circuit 102 by the 4th phase inverter 113, the 5th phase inverter 114, hex inverter 115 and first with
Not gate 109 is constituted；Wherein, the output of the 4th phase inverter 113 connects the input of the 5th phase inverter 114, the output of the 5th phase inverter 114
The input of the first NAND gate 109 is connect, the output of the first NAND gate 109 connects the input of hex inverter 115.
Preliminary filling control circuit 103 is by the first phase inverter 110, the second phase inverter 111, the 3rd phase inverter 112 and three inputs
Nor gate 108 is constituted；Wherein, the output of the first phase inverter 110 connects the input of the second phase inverter 111, the second phase inverter 111 it is defeated
Go out the input for connecing three input nor gates 108, the output of three input nor gates 108 connects the input of the 3rd phase inverter 112.
Preliminary filling control circuit 103, decoding control circuit 102, amplifier control circuit 101 have a common input pulse
Signal 104, the control of 104 subject clock signal of pulse signal.Two other input signal of preliminary filling control circuit 103 is decoding respectively
The row decoding circuit of the output of control circuit 102 enables signal 106 and the sense amplifier of the output of amplifier control circuit 101 is enabled
Signal 105, sense amplifier enable signal 105 and connect nor gate after 111 time delay of the first phase inverter 110 and the second phase inverter
108 input, pulse signal 104 and row decoding circuit enable the input that signal 106 is directly connected to nor gate 108；Decoding
Another input signal of control circuit 102 is that the precharging circuit of the output of preliminary filling control circuit 103 enables signal 107, preliminary filling
Circuit enables the input that signal 107 connects the first NAND gate 109 after the 4th phase inverter 113 and 114 time delay of the 5th phase inverter
End, pulse signal 104 are directly connected to the input of the first NAND gate 109；Another input letter of amplifier control circuit 101
Number it is that the row decoding circuit of the output of decoding control circuit 102 enables signal 106, row decoding circuit enables signal 106 through the 7th
Connect the input of the second NAND gate 110 after 117 time delay of phase inverter 116 and the 8th phase inverter, pulse signal 104 is directly connected to
The input of the second NAND gate 110.
The output end signal of nor gate 108 Jing after the driving of the 3rd phase inverter 112 exports precharging circuit and enables signal 107；The
The output end signal of one NAND gate 109 Jing after the driving of hex inverter 115 exports row decoding circuit and enables signal 106；Second with
The output end signal of not gate 110 Jing after the driving of the 9th phase inverter 118 exports sense amplifier and enables signal 105.
SRAM sequential control circuits shown in Fig. 3, it is possible to achieve all export correct sequencing contro letter under any circumstance
Number.Wherein precharging circuit enables the enable signal that signal 107 is precharging circuit, and during high level, precharging circuit does not work, low level
When precharging circuit work array neutrality line is charged to into supply voltage in advance.It is row decoding circuit that row decoding circuit enables signal 106
Signal is enabled, row decoding circuit work during high level, during low level, row decoding circuit does not work.Sense amplifier enables signal
105 is the enable signal of sense amplifier, sense amplifier work during high level, and during low level, sense amplifier does not work.In advance
Charging circuit enables row decoding circuit enable signal 106 after signal 107 becomes high level and can just become high level, and row decoding circuit makes
After energy signal 106 becomes high level, sense amplifier enable signal 105 can just become high level.Similarly, row decoding circuit makes
Energy signal 106 and sense amplifier enable precharging circuit enable signal 107 after signal 105 all becomes low level and can just become low electricity
It is flat.The mutual restricting relation that influences each other being exactly based between these three signals ensure that timing control signal under any circumstance
Correctness.
Fig. 4 gives the input signal and signal output waveform of general SRAM sequential control circuits.Wherein input signal 200
The pulse signal of subject clock signal control, precharging circuit enable signal 201 be used for controlling precharging circuit when open or
Person turns off, and decoding circuit enables signal 202 is used for controlling when on or off decoding circuit is, and sense amplifier enables signal
203 is when on or off for controlling sense amplifier.
Particular embodiments described above, has been carried out to the purpose of the present invention, technical scheme and beneficial effect further in detail
Describe bright, the be should be understood that specific embodiment that the foregoing is only the present invention in detail, be not limited to the present invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., should be included in the guarantor of the present invention
Within the scope of shield.
Claims (3)
1. a kind of static RAM sequential control circuit, it is characterised in that including amplifier control circuit (101),
Decoding control circuit (102) and preliminary filling control circuit (103), wherein：
Amplifier control circuit (101) for controlling the on or off of sense amplifier in static RAM,
It is made up of the 7th phase inverter (116), the 8th phase inverter (117), the 9th phase inverter (118) and the second NAND gate (110), its
In, the output of the 7th phase inverter (116) terminates the input of the 8th phase inverter (117), the output termination of the 8th phase inverter (117)
The input of the second NAND gate (110), the output of the second NAND gate (110) terminate the input of the 9th phase inverter (118)；
Decoding control circuit (102) for controlling the on or off of row decoding circuit in static RAM, by
4th phase inverter (113), the 5th phase inverter (114), hex inverter (115) and the first NAND gate (109) are constituted, wherein,
The output of the 4th phase inverter (113) terminates the input of the 5th phase inverter (114), the output termination of the 5th phase inverter (114) the
The input of one NAND gate (109), the input of output termination hex inverter (115) of the first NAND gate (109)；
Preliminary filling control circuit (103) for controlling the on or off of precharging circuit in static RAM, by
One phase inverter (110), the second phase inverter (111), the 3rd phase inverter (112) and three inputs nor gate (108) are constituted, wherein,
The output of the first phase inverter (110) terminates the input of the second phase inverter (111), the output termination three of the second phase inverter (111)
The input of input nor gate (108), the output of three inputs nor gate (108) terminate the input of the 3rd phase inverter (112)；
The amplifier control circuit (101), the decoding control circuit (102) and the preliminary filling control circuit (103) have
One common input pulse signal (104), input pulse signal (104) subject clock signal are controlled；
Another input signal of the amplifier control circuit (101) is the row decoding that decoding control circuit (102) is exported
Circuit enables signal (106), and row decoding circuit enables signal (106) through the 7th phase inverter (116) and the 8th phase inverter (117)
Connect the input of the second NAND gate (110) after time delay, pulse signal (104) is directly connected to the defeated of the second NAND gate (110)
Enter end, the output end signal of the second NAND gate (110) Jing after the driving of the 9th phase inverter (118) exports sense amplifier and enables signal
(105)；
Another input signal of the decoding control circuit (102) is the precharging circuit that preliminary filling control circuit (103) is exported
Signal (107) is enabled, precharging circuit enables signal (107) after the 4th phase inverter (113) and the 5th phase inverter (114) time delay
Connect the input of the first NAND gate (109), pulse signal (104) is directly connected to the input of the first NAND gate (109), first
The output end signal of NAND gate (109) Jing after hex inverter (115) driving exports row decoding circuit and enables signal (106)；
Two other input signal of the preliminary filling control circuit (103) is that the row that decoding control circuit (102) is exported is translated respectively
Code circuit enables sense amplifier enable signal (105) that signal (106) and amplifier control circuit (101) are exported, sensitive to put
Big device is enabled signal (105) and is connected nor gate (108) after the first phase inverter (110) and the second phase inverter (111) time delay
Input, pulse signal (104) and row decoding circuit enable the input that signal (106) is directly connected to nor gate (108), or non-
The output end signal of door (108) Jing after the driving of the 3rd phase inverter (112) exports precharging circuit and enables signal (107).
2. static RAM sequential control circuit according to claim 1, it is characterised in that
The sense amplifier enables the enable signal that signal (105) is sense amplifier, sense amplifier work during high level,
During low level, sense amplifier does not work；
The row decoding circuit enables the enable signal that signal (106) is row decoding circuit, row decoding circuit work during high level,
During low level, row decoding circuit does not work；
The precharging circuit enables the enable signal that signal (107) is precharging circuit, and during high level, precharging circuit does not work, low electricity
Array neutrality line is charged to supply voltage by precharging circuit work in advance at ordinary times.
3. static RAM sequential control circuit according to claim 1 and 2, it is characterised in that
The precharging circuit enables row decoding circuit enable signal (106) after signal (107) becomes high level and can just become
High level, the row decoding circuit enable the sense amplifier after signal (106) becomes high level and enable signal (105) ability
Become high level；
The row decoding circuit enables signal (106) and the sense amplifier enables signal (105) and all becomes institute after low level
State precharging circuit enable signal (107) and can just become low level.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410115159.8A CN103886895B (en) | 2014-03-26 | 2014-03-26 | A kind of static RAM sequential control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410115159.8A CN103886895B (en) | 2014-03-26 | 2014-03-26 | A kind of static RAM sequential control circuit |
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| CN103886895B true CN103886895B (en) | 2017-04-05 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105304121B (en) * | 2014-07-31 | 2018-11-16 | 展讯通信（上海）有限公司 | The center control circuit of SRAM memory |
| CN104882158B (en) * | 2015-05-25 | 2017-10-31 | 清华大学 | A kind of programmable SRAM synchronised clock control module circuit |
| CN105336361B (en) * | 2015-12-04 | 2018-07-27 | 安徽大学 | A kind of SRAM autotrackings duplication bit line circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034585A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | SRAM system circuit without sensitive amplifier |
| CN101131999A (en) * | 2006-08-25 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and testing method of same |
| CN102664041A (en) * | 2012-05-22 | 2012-09-12 | 安徽大学 | Programmable static random access memory (SRAM) time sequence control system based on build-in self-test (BIST) control |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005276348A (en) * | 2004-03-25 | 2005-10-06 | Fujitsu Ltd | Semiconductor storage device and precharge control method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034585A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | SRAM system circuit without sensitive amplifier |
| CN101131999A (en) * | 2006-08-25 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and testing method of same |
| CN102664041A (en) * | 2012-05-22 | 2012-09-12 | 安徽大学 | Programmable static random access memory (SRAM) time sequence control system based on build-in self-test (BIST) control |
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