KR20140117062A - 3d nand flash memory - Google Patents

Abstract

A memory device comprises an array of NAND strings in memory cells. The device comprises stacks of a plurality of conductive strips which are separated by an insulation material and have the bottoms, the middle sides, and the tops of conductive strips. The device comprises charge storage structures in boundary areas of cross-points between the conductive strips of the middle sides in stacks and the side surfaces of semiconductor elements between the stacks in a plurality of bit line structures. One or more reference line structures are vertical to the tops of the stacks. The device comprises vertical conductive elements between the stacks, which are connected to a reference conductor between the bottoms of the conductive strips and a substrate, and connection elements on the stacks which connect the vertical conductive elements. The vertical conductive elements have a side size which is bigger than that of the semiconductor elements.

Description

3D NAND FLASH MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high density memory devices, and more particularly to memory devices in which the multi-layered surfaces of memory cells are arranged to provide a three-dimensional (3D) array.

As critical dimensions of devices in integrated circuits have been reduced to the limits of conventional memory cell technologies, designers have found that techniques for stacking multiple layers of memory cells to achieve greater storage capacity and achieve lower cost per bit I have noticed. For example, thin film transistor technologies are described in Lai et al., "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory" (IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006); And Jung et al. &Quot; Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node "(IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006) have.

In addition, cross-point array techniques are described in Johnson et al., &Quot; 512-Mb PROM with a Three-Dimensional Array of Diode / Anti-fuse Memory Cells " , No. 11, Nov. 2003) for anti-fuse memory memories. In the design described by Johnson et al., Multiple layers of word lines and bit lines are provided with memory elements at the cross-points. The memory elements include a p + polysilicon anode connected to the word line and an n-polysilicon cathode connected to the bit line, wherein the anode and the cathode are separated into anti-fuse materials.

In the processes described by Lai et al., Jung et al. And Johnson et al., The number of some very important etch steps required to fabricate the device is multiplied by the number of layers being performed. Thus, even with the advantage that higher densities are realized using three-dimensional (3D) arrays, the use of this technique results in a higher manufacturing cost limit.

Other structures for providing vertical NAND cells in charge trapping memory technology are described in Tanaka et al., "Bit Cost Scalable Technology with Punch and Plug Processes for Ultra High Density Flash Memory" (2007 Symposium on VLSI Technology Digest of Technical Papers, 12-14 June 2007 , pages 14-15). The structure described in Tanaka et al. Discloses a multi-gate field effect transistor structure having vertical channels that operate like a NAND gate using silicon-oxide-nitride-silicon (SONOS) charge trapping techniques to create storage sites at the gate / . The memory structure is based on a pillar of semiconductor material arranged in a vertical channel for a multi-gate cell having a lower select gate adjacent the substrate and an upper select gate at the top. A plurality of horizontal control gates are formed using planar electrode layers that intersect the pillars. The planar electrode layers used for the control gates do not require extremely critical etching and thus the cost is reduced. However, many very important etch steps are needed for each of the vertical cells. Also, there is a limit to the number of control gates that can be layered in this manner, as determined by functions such as the vertical channel conductivity, the programming and erasing processes being used, and the like.

Accordingly, it would be desirable to provide a three-dimensional integrated circuit memory that includes very small memory elements that are reliable at low manufacturing costs.

The memory device includes an array of NAND strings of memory cells. The apparatus includes an integrated circuit substrate and a plurality of stacks of conductive strips separated by an insulating material comprising at least a bottom surface of the conductive strips, a plurality of intermediate surfaces of the conductive strips and an upper surface of the conductive strips .

A plurality of bitline structures are arranged orthogonal to the plurality of stacks, and having conformal surfaces to the plurality of stacks, wherein between the stack semiconductor body elements and between the stack semiconductors And connecting elements on top of the stacks connecting the body elements. The memory device includes reference selection switches in interface regions having string selection switches and bottom surfaces of the conductive strips in interface regions having an upper surface of the conductive strips.

The memory device may further include an interfacial region at cross-points between the conductive strips of the plurality of intermediate surfaces in the stacks and the side surfaces of the semiconductor body elements between the stacks of the plurality of bit line structures. Lt; RTI ID = 0.0 > charge storage structures.

In one aspect of the technique described herein, a reference conductor is disposed between the bottom surface of the conductive strips and the substrate. At least one reference line structure is arranged orthogonally to the top of the plurality of stacks and includes inter-stack vertical conductive elements between the stacks in electrical communication with the reference conductors. The at least one reference line structure also includes connecting elements on top of the stacks connecting the stacked vertical conductive elements. The inter-stack vertical conductive elements may have greater conductivity than the inter-stack semiconductor body elements.

In another aspect of the presently described technology, at least a portion of the conductive strips in the plurality of stacks comprise a silicon body having a silicide layer on a side of the silicon body opposite the side surfaces on which the charge storage structures are disposed do.

Methods for fabricating the memory devices described herein are also provided.

Other aspects and advantages of the invention will be subsequently understood with reference to the accompanying drawings, the description of the invention, and the claims.

According to exemplary embodiments of the present invention, it is possible to provide a three-dimensional integrated circuit memory including very small memory elements that are reliable at low manufacturing cost.

1 is a schematic diagram of a three-dimensional memory device.
Figure 2 is a schematic layout corresponding to a top view of the schematic three-dimensional drawing of Figure 1;
3 is a schematic diagram of a three-dimensional memory including decoding structures.
Figure 4 is a schematic layout corresponding to a top view of the schematic three-dimensional drawing of Figure 3;
Figure 5 is an optional schematic layout for the schematic layout shown in Figure 4.
Figure 6 is a schematic layout illustrating a side wall word line silicide formation.
7 is a schematic three-dimensional view illustrating a sidewall wordline suicide formation in a double-gate vertical channel structure.
8 is a schematic three-dimensional diagram illustrating a vertical channel structure.
Figure 9 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention.
10 is a flow chart illustrating a method for fabricating a dual-gate vertical channel structure.
11 through 18 are diagrams illustrating an exemplary process flow for a dual-gate vertical channel structure.
Figures 19-24 are illustrations of an exemplary process flow for an embodiment of a sidewall silicide formation within a vertical channel structure.
FIGS. 25-33 are diagrams illustrating an exemplary process for an alternative embodiment of a sidewall silicide formation in a vertical channel structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description of embodiments of the present invention is provided with reference to Figs.

Figure 1 is a schematic diagram of a three-dimensional (3D) memory device 100. The memory device 100 includes NAND strings of memory cells and may be a double-gate vertical channel memory array (DGVC). The memory device 100 includes an integrated circuit substrate and at least conductive strips of a bottom plane GSL, conductive strips of a plurality of intermediate planes WLs, and conductive strips of a top plane And stacks of a plurality of conductive strips separated by insulating material, having strips (SSLs). 1, the stack 110 includes conductive strips GSL on the bottom surface, conductive strips WLs on a plurality of intermediate surfaces ranging from WL ₀ to WL _N-1 , Strips (SSLs), where N may be 8, 16, 32, 64, and so on.

A plurality of bitline structures are arranged orthogonally on the plurality of stacks and have conformal surfaces on the stacks and inter-stack semiconductor body elements 120 between the stacks 120 < RTI ID = 0.0 > And connecting elements 130 connecting the interstack semiconductor body elements 120 on top of the stacks. In such an embodiment, the connecting elements 130 comprise a semiconductor, such as polysilicon, having a higher conductivity than the inter-stack semiconductor body elements 120 because they have a relatively high doping concentration, Lt; / RTI >

The memory device may include a cross-point between the side surfaces of the conductive strips (WLs) of the plurality of intermediate surfaces in the stacks and the semiconductor body elements (120) between the stacks of bit line structures Lt; RTI ID = 0.0 > 180 < / RTI > In the illustrated embodiment, the memory cells in the cross-points 180 are arranged in a vertical double-gate NAND (NAND) configuration where conductive strips on opposite sides of a single stack of semiconductor elements act as double- Strings, and may operate in concert for read, erase, and programming operations.

A reference conductor 160 is disposed between the conductive strips GSL on the bottom surface and the integrated circuit substrate (not shown). At least one reference line structure is orthogonally aligned on top of the plurality of stacks and between the stacks in electrical communication with the reference conductor 160 between the stack vertical conductive elements 140 And connection elements 150 connecting the inter-stack vertical conductive elements 140 on the stacks. The inter-stack vertical conductive elements 140 may have a higher conductivity than the inter-stack semiconductor body elements 120.

The memory device includes string select switches 190 in interface regions having an upper surface of the conductive strips and reference select switches 170 in interface regions having a bottom surface GSL of the conductive strips . The dielectric layers of the charge storage structure may function as gate dielectric layers for the switches 170, 190 in some instances.

The memory device includes a first top patterned conductive layer (not shown) coupled to the plurality of bit line structures having global bit lines connected to sensing circuits. The memory device may also be patterned and includes a second top conductive layer (not shown) that may be located above or below the first patterned conductive layer. The second upper conductive layer is connected to at least one of the reference line structures as they are in contact with the coupling element 150. The second patterned conductive layer may connect the at least one reference line structure to a reference voltage source or to a circuit for providing a reference voltage.

In the embodiment shown in FIG. 1, the coupling elements 130 of the bit line structures comprise N + doped semiconductor material. The inter-stack semiconductor body elements 120 of the bit line structures include a lightly doped semiconductor material. In the embodiment shown in FIG. 1, the reference conductor 160 comprises N + doped semiconductor material, and the coupling elements 150 of the at least one reference line structure include N + doped semiconductor material. The inter-stack conductive elements 140 of the at least one reference line structure also include an N + doped semiconductor material. In alternative embodiments, a metal or metal compound may be used in place of the doped semiconductors.

In one embodiment, to reduce the resistance of the reference conductor 160, the memory device may have a bottom gate 101 near the reference conductor 160. During read operations, the bottom gate 101 may apply a suitable pass voltage to the bottom doped wells or wells in the substrate, or to patterning the other bottoms to increase the conductivity of the reference conductor 160. [ Lt; RTI ID = 0.0 > on < / RTI > conductor structures.

Figure 2 is a schematic layout corresponding to a top view of the schematic three-dimensional drawing of Figure 1; The bit lines 231 to 234 and the bit lines 235 to 238 correspond to the connection elements 130 (Fig. 1) in the plurality of bit line structures. Source line 240 corresponds to connecting elements 150 (FIG. 1) in the at least one reference line structure (FIG. 1), and other source lines may be spaced along the array. The bit lines BL and the source line SL are arranged to be orthogonal to the upper side of the word lines (WL) 211 to 216, and the word lines are located in a plurality of intermediate planes of the conductive strips. Although only four bit lines are shown on each side of the source line 240, any number of bit lines may be located on each side of the source line 240. For example, there may be eight or sixteen bit lines on the side of each source line 240.

In the embodiment shown in FIG. 2, the memory device includes a first top layer, which has first top lines 281-288. The first upper conductive layer may comprise a metal, a doped semiconductor, or a combination of materials. The first upper lines 281 through 288 are connected directly to bit lines 231 through 238 through bit line contacts 251 to minimize bit line loading resistance. As described herein, bit lines 231 through 238 correspond to connecting elements 130 (FIG. 1) in the plurality of bit lines, Lines. The first upper conductive layer may comprise a plurality of generic bit lines coupled to sensing circuits (not shown). The locations of the bit line contacts 251 are shown as one embodiment. The physical layout of the bit line contacts may be periodic or aperiodic, which may provide more regular layouts for better etch exposure.

In the embodiment shown in FIG. 2, the memory device includes a second top layer 290. The second upper conductive layer comprises a metal, a semiconductor, or a combination of materials. The second upper layer 290 is connected directly to the source line 240 through the source line contacts 255 to minimize the source line loading resistance. As described herein, the source line 240 corresponds to the connection elements 150 (FIG. 1) in the at least one reference line structure, so that the conductive layer of the second upper portion is connected to the at least one reference line structure Line structure. The second upper conductive layer may be connected to a reference voltage source (not shown). The locations of the source line contacts 255 are shown as an example. The physical layout of the source line contacts may be periodic or aperiodic, which may provide more regular layouts for better etch exposure.

The inter-stack vertical conductive elements 140 (FIG. 1) in the at least one reference line structure may have a larger cross-sectional area than the inter-stack semiconductor body elements 120 (FIG. 1) in the bit line structures have. Correspondingly, the source line contacts 255 may have a larger cross-sectional area than the bit line contacts 251.

3 is a schematic diagram of a three-dimensional memory device including examples of pad regions within conductive strips for horizontal wordlines and GSL line structures configured for stair contacts for upper decoding circuits; The string selection lines in the top surface of the conductive strips are independently connected to the string selection line decoding circuits and controlled by the string selection line decoding circuits.

The conductive strips WLs in the intermediate surfaces and the conductive strips GSL in the bottom surface are connected together to reduce the decoder areas and consequently the overall size of the memory device. The conductive strips (SSL) in the top surface are individually decoded to enable correction bit line decoding.

The memory device includes connection elements such as connection elements 361 and 362 that provide pad areas connecting the sets of word lines in the intermediate planes WL and a landing area 362 in the connection elements 361 and 362. [ Such as interlayer interconnects 371 and 372, which are connected to landing regions of the lower intermediate planes and which are connected to landing regions in the extension of the lower intermediate planes, . The landing areas are present in interfacial areas between the bottom surfaces of the interlayer conductors and the upper surfaces of the connecting elements.

As illustrated in FIG. 3, the interlayer connectors for the set of word lines in the multilayers in the plurality of intermediate planes are arranged in a stepped structure. Accordingly, the interlayer connectors 371 and 372 are connected to the landing areas in two different layers in the plurality of intermediate surfaces. The step structure may be formed in a word line decoder region near the boundary of an area for the array of NAND strings of the memory cells and for peripheral circuits.

In the embodiment shown in FIG. 3, the memory device includes connecting elements such as a connecting element 363 connecting the sets of ground select lines in the bottom surface GSL of the conductive strips, Such as an interlayer connector 373, which is connected to the landing areas in the intermediate surfaces WLs, and the interlayer conductors extend through openings in the connection elements in the intermediate surfaces WLs. The landing areas are present in interfacial areas between the bottom surfaces of interlayer conductors, such as interlayer connectors 373, and the upper surfaces of connecting elements such as connecting element 363.

Figure 4 is a schematic layout corresponding to a top view of the schematic three-dimensional drawing of Figure 3; 4, the connection elements 431 to 438 in the bit line structures and at least the group 430 of connection elements 440 in the at least one reference line structure are formed on the intermediate surfaces WL And a second adjacent set of word lines 420 in the intermediate planes (WL). The coupling elements 431 to 438 in the bit line structures function as bit lines. The connecting element (440) in the at least one reference line structure serves as a source line. In the embodiment shown in Figure 4, bit line contacts 451 connect connecting elements 431 through 438 in the bit line structures to the first upper lines (e. G., 281 in Figure 2) 0.0 > 288 < / RTI > Source line contacts 455 connect the connecting element 440 in the at least one reference line structure directly to the first top layer (e.g., reference numeral 290 in FIG. 2). The locations of the bit line contacts and source line contacts are an example as one embodiment. The actual physical layout of the bit line contacts and source line contacts for the word lines may be periodic or aperiodic, which may provide more regular layouts for better etch exposure.

The group 430 includes a first set 410 of word lines 411-416 in the middle planes WL and a second set of word lines 421-416 in the middle planes WL. (420). The numbers of the first set 410 are joined together by a connecting element to provide a pad on top of which each one of the interlayer connectors 471 to 474 contacts the landing areas. Similarly, the numbers of the second set 420 are coupled together by a connecting element to provide a pad on each of which the respective one of the interlayer connectors 491 to 494 contacts the landing areas .

Interlayer connectors 471 through 474 for the first set 410 are aligned on the sides of the group 430 parallel to the bit lines in the group 430. The interlayer connectors 491 to 494 for the second set 420 are aligned on the same side of the group 430. String select lines within the top surface of the conductive strips corresponding to the first set 410 and the second set 420 are connected to string select line decoding circuits < RTI ID = 0.0 > (Not shown).

The coupling elements 460 couple the word lines in the first set 410 in a single patterned word line structure for a block of memory cells. The interlayer connectors 471 to 474 are connected to the landing areas in the connection elements 460 and are connected to the word line decoding circuits (not shown). Similarly, coupling element 480 couples the word lines in the second set 420. The interlayer connectors 491 to 494 are connected to the landing areas in the coupling element 480 and are connected to the word line decoding circuits. The landing areas are present in interfacial areas between the bottom surfaces of the interlayer conductors and the upper surfaces of the connecting elements.

As described herein with respect to FIG. 3, interlayer connectors for sets of word lines in the plurality of intermediate planes are adapted to contact the pads (e.g., connection elements 460, 480) within the step structure . Accordingly, the interlayer connectors 471 to 474 can be connected to the landing areas in four different layers in the plurality of intermediate surfaces, and the interlayer connectors 491 to 494 can be connected at the same position, And may be connected to landing regions at other ones of the four different layers within the intermediate planes.

Although the first set 410 and the second set 420 each include six word lines, as illustrated in FIG. 4, more word lines may be present in each set. For example, the first set 410 and the second set 420 may each comprise eight, sixteen, or thirty-two word lines. Similarly, although there are four bit lines on either side of the connecting element 440 in the at least one reference line structure, there may be more bit lines on either side of the connecting element 440 . For example, there may be eight to sixteen bit lines on each side of the connecting element 440.

The circuit layout shown in Fig. 4 can be repeated in horizontal and vertical directions.

Figure 5 is an optional schematic layout. The description for FIG. 4 can also be applied to FIG. 5 in general. 5, a group 530 of connection elements 531 to 538 in the bit line structure and at least a connection element 540 in the at least one reference line structure are formed on the intermediate surfaces WL The first set 510 of word lines 511 through 516 and the second adjacent set 520 of word lines 521 through 526 in the intermediate planes WL. The connecting elements 531 to 538 in the bit line structures function as bit lines. The connecting element (540) in the at least one reference line structure serves as a source line.

The interlayer connectors 571 to 574 for the first set 510 are aligned on one side of the group 530 in the connecting element 560. The interlayer connectors 591 to 594 for the second set 520 are aligned on the other opposing sides of the group 530 in the connecting element 580.

String select lines in the top surface of the conductive strips corresponding to the first set 510 are selected from the same side of the group 530 on the side of the interlayer connectors for the second set of word lines 520 Line decoding circuits. String select lines in the top surface of the conductive strips corresponding to the second set 520 are selected from the same side of the group 530 on the side of the interlayer connectors for the first set of word lines 510 Line decoding circuits.

The alternative layout illustrated in Figure 5 provides a larger processing window for the word line decoding circuits and string select line decoding circuits and can be repeated with an image of a mirror image in the word line direction, May be shared among the groups with contacts for connection elements that are created in every other set and aligned as an offset type as shown for adjacent wordline structures.

Figure 6 is a schematic layout illustrating a side wall word line silicide formation. Sidewall wordline silicide builds can reduce the resistance of the wordline structures and thus reduce the wordline RC delay for large arrays. The memory device may comprise blocks comprising connection elements connecting sets of word lines in the intermediate planes (WLs) and interlayer interconnects coupled to landing areas in the connection elements, The ends of the word lines in the word lines are connected via the connecting elements and the connecting elements include openings through which interlayer insulators connect to the landing areas in the lower intermediate plane extensions. The memory device may further include sidewall silicide formations disposed on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks.

6, the memory device includes adjacent blocks 615 and 671 including a connecting element 660 connecting a set of word lines 610 in the intermediate planes WLs. And interlayer connectors 671 to 674 connected to the landing areas in the connection element 660. [ The ends of the word lines in adjacent blocks 615 and 617 are connected through the coupling element 660.

The memory device also includes adjacent blocks 625 and 627 that include a connecting element 680 connecting the set of word lines 620 in the intermediate planes WLs and a landing Lt; RTI ID = 0.0 > 691 < / RTI > The ends of the word lines in adjacent blocks 625 and 627 are connected via the coupling element 680.

The connecting elements include openings through which the interlayer connectors that are connected to the landing areas in the lower intermediate plane extensions pass. In the embodiment shown in FIG. 3, the coupling elements 361, 362 include openings through which the interlayer connectors 372, 373, which are connected to the landing areas within the lower intermediate surface extension, pass.

In this embodiment, the word line structure including the coupling element 660 includes sidewall silicide formations 602 and 604 disposed on the sides of the outermost conductive strips 611 and 613. [ Also, in this embodiment, the word line structure comprising the coupling element 680 includes sidewall silicide formations 606, 608 disposed on the sides of the outermost conductive strips 621, 623. The silicide formations can improve the conductivity of the word line structures for distribution of word line voltages within a large scale array.

The region 609 of FIG. 6 can be understood in more detail with reference to the schematic three-dimensional drawing of FIG.

7 is a schematic three dimensional perspective view illustrating a sidewall wordline silicide formation in a double-gate vertical channel structure corresponding to region 609 of FIG. Two layers of word lines are illustrated. The first layer of the two layers includes a word line 722 and a word line 752. The second layer of the two layers includes a word line 724 and a word line 754. The four word lines become a set of word lines (e.g., 610 in FIG. 6). The word lines 722 and 724 are in the set of word lines 610. The word lines 752 and 754 correspond to the outermost conductive strips 611 and 613 of Figure 6 and are formed on their respective sidewalls on the sides of the set of word lines 610, (762, 764).

7, dielectric charge storage layers 710 and 730, such as ONO (oxide-nitride-oxide) materials, are formed on the word line 722 and the word line 724 on the opposite sidewalls. Dielectric charge storage layers 740 may be formed on the sidewalls of the word lines 752 and word lines 754 opposite the sidewalls of the word lines having sidewall silicide formations. The word lines are separated from the other word lines by insulating oxide materials 770 either above or below.

In another alternative embodiment, as illustrated in Figure 33, the memory device may include pairs of adjacent stacks in the stacks of the plurality of conductive strips, and may include a multilayer dielectric charge storage structure A memory layer 2990 is formed on the first side of the conductive strips, such as 3131 and 3133 in the intermediate planes WLs, and on the side surfaces of interstack semiconductor body elements, such as 2791 in the plurality of bitline structures Are placed in the interfacial areas at the cross-points between. The memory device is disposed on the side surfaces on the second side of the conductive strips, such as 3131 and 3133, opposite the first side in the middle surfaces (WLs) of the conductive strips in the pairs of adjacent stacks, Lt; RTI ID = 0.0 > 3132 < / RTI >

The sidewall silicide formations are parallel to the word lines in the intermediate planes WLs of the conductive strips and orthogonal to the interstack semiconductor body elements in the plurality of bit line structures. Detailed descriptions of alternative embodiments are provided in connection with Figs. 25-33.

8 is a schematic three-dimensional diagram illustrating a vertical channel structure. 8, the dual-gate vertical channel structure is arranged as charge storage structures 832, 834 between the side surfaces of each horizontal gate 812, 814 and vertical channel 820 Dielectric layers.

The current flow is vertical as indicated by the arrow 840 through the vertical channel 820. Gates 812 and 814 are portions of the conductive strips in the intermediate planes WLs in the stacks. The conductive strips may be doped with doping such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W) And may include various materials including semiconductors, metals, and conductive compounds. Vertical channel 820 is part of the bit line structure in the memory device and may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), silicon carbide (SiC), and graphene. Which are arranged to function as channels for the memory cells. The charge storage structures in the memory device including the charge storage structures 832 and 834 may include multilayer dielectric charge trapping structures known from flash memory technologies known in the art as ONOS, BE-SONOS, TANOS, and MA BE-SONOS. .

Figure 9 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. In the embodiment shown in FIG. 9, the integrated circuit 975 may be a dual structure implemented as one or both of source line structures and word line structures on an integrated circuit substrate, as described herein. - gate vertical channel memory array (DGVC) 960. A row decoder 961 is connected to a plurality of word lines 962 and aligned along the rows in the memory array 960. A column decoder 963 is coupled to a plurality of bit lines 964 (or SSL lines as described above) and is coupled to the memory array 960 for reading and programming data from the memory cells in the memory array 960 Aligned along the columns in the memory array 960. A plane decoder 958 is coupled to a plurality of planes in the memory array 960 on the SSL lines 959 (or bit lines as described above). Addresses are supplied to a column decoder 963, a row decoder 961 and a plane decoder 958 on a bus 965. The sense amplifiers and data-in structures in block 966 are connected to the column decoder 963 via a data bus 967 in this example. Data may be transferred from input / output ports on the integrated circuit 975 or from other data sources internal or external to the integrated circuit 975 via the data-input line 971 to a data input Lt; / RTI > In the illustrated embodiment, other networks 974 such as a general purpose processor or a combination of modules that provide system-on-chip functionality supported by a specific purpose application network or a programmable resistance cell array ) Are included on the integrated circuit. Data may be transferred from the sense amplifiers in block 966 to the input / output ports on the integrated circuit 975 via the data output line 972 or to other data destinations on or within the integrated circuit 975 / RTI >

In this example, a controller implemented using a bias arrangement state machine 969 is coupled to a bias arrangement (not shown) generated or provided through voltage supplies or supplies in block 968, such as read and program voltages, Adjust the application of the supply voltage. The controller may be implemented using a specific purpose logic network as is known in the art. In other alternative embodiments, the controller may comprise a general purpose processor that may be implemented on the same integrated circuit, which executes a computer program to control operations of the device. In yet other embodiments, a combination of a specific purpose logic network and a general purpose processor may be utilized for implementation of the controller.

10 is a flow diagram illustrating a method for manufacturing a memory device. The method includes identifying areas on a substrate for the formation of three dimensional memory blocks having the same structure as in the case of FIG. For each region, the method includes forming auxiliary gate conductors by embedding assist gate wells in the substrate or by patterning a conductive material on the substrate. Above the assist gate conductors, a layer of an assist gate dielectric such as silicon oxide is formed (block 1009). Above the insulating layer, the process includes forming layers of a plurality of first conductive materials separated by an insulating material (block 1010) and etching the plurality of layers to define stacks of the plurality of conductive strips Block 1020). The stacks include at least the bottom surface (GSL) of the conductive strips, the plurality of intermediate surfaces (WLs) of the conductive strips and the top surfaces (SSLs) of the conductive strips.

The method includes forming a memory layer on the side surfaces of the conductive strips in the plurality of stacks (block 1030). The memory layer is in contact with the side surfaces of the plurality of conductive strips. The method includes forming a layer of a second conductive material having a conformed surface over the memory layer on the plurality of stacks (block 1040).

The method includes etching the layer of the second conductive material to define a plurality of bit line structures that are aligned orthogonally to the top of the stacks and have conformal surfaces to the stacks (block 1050) . The bit line structures include inter-stack semiconductor body elements between the stacks and connection elements connecting the inter-stack semiconductor body elements on top of the stacks.

Etching a layer of a second conductive material to define at least one reference line structure that is orthogonally aligned over the plurality of stacks (block 1050) is also used in this example. The reference line structure includes inter-stack vertical conductive elements between the stacks in electrical communication with the layer of common source conductive material. In addition, the reference line structure may include connecting elements connecting the stacked vertical conductive elements on top of the stacks. Etching the layer of the second conductive material is stopped at a level above the layer of the assist gate dielectric such that portions of the layer of the second conductive material below the level remain to form a reference conductor. The reference conductor is coupled to the reference line structure and the bit line structures to enable electrical communication from the reference line structure to the bit line structures (block 1050).

As a result of forming the bit line structures, memory cells are formed in a cross between the conductive strips in the plurality of intermediate planes (WLs) in the stacks and the side surfaces of the semiconductor body elements between the stacks of bit line structures Lt; RTI ID = 0.0 > of-points. ≪ / RTI > In addition, the string selection switches are disposed in the interface regions having the conductive strips (SSLs) on the top surface, and the reference selection switches are disposed in the interface regions having the conductive strips (GSL) on the bottom surface. The memory layer may include dielectric layers capable of functioning as the gate dielectric layers for the string select switches and the reference select switches.

In one embodiment, the method further comprises forming a plurality of bit line structures at a first energy level on the connecting members in the plurality of bit line structures, on the connecting elements in the reference conductor and the reference connector and in the at least one reference line structure N + doping material (block 1060). The method may further include injecting an N + doping material at a second energy level onto the stack of vertical conductive elements of the at least one reference line structure (block 1060) 1 energy level.

The inter-stack vertical conductive elements in the at least one reference line structure may have a larger cross-sectional area than the inter-stack semiconductor body elements in the bit line structures, as illustrated in FIG.

In one embodiment, the step of etching the plurality of layers to define stacks of a plurality of static strips in the method (block 1020) includes connecting the sets of word lines in the middle surfaces WL as part of a decoding structure To form connecting elements to be connected. The method further includes forming apertures in the coupling elements and forming interlayer conductors coupled to landing areas within the coupling elements as a different part of the decoding structure, The interlayer conductors connected to the landing areas extend through the openings in the connecting elements (block 1070).

The step of etching the plurality of layers to define stacks of conductive strips in the method (block 1020) may further comprise forming connection elements connecting the sets of ground selection lines in the bottom surface. The method further includes forming interlayer connectors that are connected to landing areas within the connecting elements of the bottom surface, wherein the interlayer connectors are formed by interposing openings in the connecting elements of the intermediate surfaces (WLs) (Block 1070).

In one embodiment, the bit lines of the bit line structures and at least a group of source lines of the at least one reference line structure are connected to a first set of word lines of the intermediate planes (WL) ), The interlayer connectors for the first set being aligned on the sides of the group parallel to the bit lines in the group, and the second set of word lines in the second set Lt; / RTI > are aligned on the sides of the group.

In another alternative embodiment, the bit lines of the bit line structures and at least a group of source lines of the at least one reference line structure are connected to a first set of word lines of the intermediate planes (WL) (WL), the interlayer interconnects for the first set being aligned on the sides of the group parallel to the bit lines in the group, The interlayer connectors for the two sets are aligned on the opposite sides of the group.

In one embodiment, the method comprises forming blocks comprising interconnection elements connecting sets of word lines in the intermediate planes (WLs) and interlayer interconnects connected to landing areas in the interconnection elements The ends of the word lines in adjacent blocks being connected via the connecting elements and the connecting elements being connected to the landing areas in the lower intermediate plane extensions, . The method may further include forming sidewall silicide formations on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks.

In an alternative embodiment, the method may further comprise forming pairs of adjacent stacks in the stacks of the plurality of conductive strips, wherein charge storage structures are formed on the word lines in the middle surfaces (WLs) Are disposed in interfacial regions at cross-points between the first side and the side surfaces of the semiconductor body elements between the stacks in the plurality of bit line structures. The method may further comprise forming sidewall silicide formations on the second side of the word lines opposite the first side of the intermediate surfaces (WLs) of the conductive strips in pairs of adjacent stacks.

The method includes forming a first top conductive layer coupled to the plurality of bit line structures, the global top bit line structure including global bit lines coupled to sensing circuits, Forming a second top layer coupled to the line structure (block 1080).

11 through 18 illustrate an exemplary process flow for a dual-gate vertical channel structure. 11 illustrates a method of forming a plurality of first conductive materials 1102, such as layers 1110, 1120, 1130, 1140, separated by an auxiliary gate conductor 1101 and layers of insulating material 1105 on an integrated circuit substrate (not shown) ≪ / RTI > illustrate the process flow after forming the layers of FIG.

12 illustrates the steps of a process flow after etching the plurality of layers to define stacks of a plurality of conductive strips including stacks 1210, 1211, 1212 and stopping at the auxiliary gate conductor 1101 . The stacks 1210, 1211 and 1212 include at least a bottom surface GSL of the conductive strips, intermediate surfaces WLs of the conductive strips and upper surfaces of the conductive strips SSLs. As illustrated in FIG. 12 for the stack 1210, the plurality of intermediate planes may include N planes ranging from 0 to N-1. Although not shown, the conductive strips are connected by pads defined in the patterns used for etching the stacks. The pads can be used to form connecting elements in subsequent steps, such as in the case of Figs. 4 and 5 described above.

Figure 13 illustrates the steps of a process flow after forming a memory layer 1310 on top and sides of the conductive strips in the plurality of stacks including the stack 1210. The memory layer 1310 contacts the side surfaces of the plurality of conductive strips. The memory layer 1310 may include multiple layers of charge storage structures, as described above.

14 illustrates a method of forming a layer 1410 of a second conductive material having a conformal surface on the memory layer 1310 over the memory layer 1310 on the plurality of stacks including the stack 1210 RTI ID = 0.0 > 1 < / RTI > The second conductive material includes a semiconductor applied at least in regions between the stacks to function as channel regions for vertical strings of memory cells.

15 illustrates the process flow after patterning and timely etching of the layer of second conductive material 1410 and is timed to stop before reaching the memory layer 1310 between the stacks, (E.g., 1560) is formed between each stack. Other processes for stopping the etch to form the reference conductor, including the use of etch stop films disposed in the second conductive material within the trenches to a desired depth, may also be used. The etch pattern defines a plurality of bit line structures 1520/1530, including the stack 1210, aligned orthogonally to the top of the plurality of stacks and having conformal surfaces to the stacks. The bit line structures 1520/1530 may include inter-stack semiconductor body elements 1520 between the stacks extending to the reference conductors 1560, and semiconductor body elements 1520 And connecting elements 1530 on top of the stacks connecting them. To expose the underlying structures, the illustrated bar represents the openings in the regions between the bit line structures between the conductive strips in the stacks. However, these openings will be filled with an insulating material between the strips in the stacks.

The step of etching the layer of second conductive material also defines at least one reference line structures (1540/1550) that are aligned orthogonally to the top of the plurality of stacks. The reference line structure of the stack to connect with the reference conductor (e.g., reference numeral 1560) stacked between the vertical conductive element 1540 and the vertical conductive elements extending to 1540 between the stack And upper coupling elements 1550.

Figure 15 illustrates the reference conductor 1560, which remains as a result of the patterned timed etch being placed between the bottom surface GSL of the conductive strips on the substrate and the auxiliary gate structure 1101.

The memory layer 1310 may serve as an assist gate between the reference conductor 1560 and the assist gate conductor 1101.

Figure 16 illustrates the steps of a process flow after the bit line structures are formed, the process including forming the connecting elements 1530 in the plurality of bit line structures, within the exposed regions between the bit line structures Doped material at a first energy level on the reference conductor 1560 and on the coupling elements 1550 between the bit line structures and the reference line structures and in at least one reference line structure by an arrow 1610 ) In the direction indicated by the arrow. The first energy level may be less than 30 keV at a typical implant dose of about 1E14 per cm < 2 >.

The inter-stack semiconductor body elements 1510 of the bit line structures are substantially vertical (approximately 90 degrees) relative to the reference conductor 1560 when the profile of the inter-stack semiconductor body elements 1510 of the bit line structures is substantially vertical 1520 receive the minimum amount of N + doping material at the first energy level, while most of the N + doping material is injected into the reference conductor 1560 thereby reducing its resistance.

FIG. 17 illustrates the steps of a process flow subsequent to the implantation of FIG. 16, wherein the process flow includes an arrow 1710 at a second energy level on vertical conductive elements 1540 between stacks of the at least one reference line structure. Doping material in a direction indicated by the second energy level, wherein the second energy level is greater than the first energy level. For example, the second energy level may be on the order of 30 keV to 50 keV with a typical dose of about 1E14 to 1E15 per cm < 2 >. An implant mask (not shown) may be used to protect the bit line structures and other portions of the memory array from this additional implantation step. This can improve the conductivity of the inter-stack vertical conductive elements 1540 for the reference line structure.

The inter-stack vertical conductive elements 1540 in the at least one reference line structure may have a larger cross-sectional area than the inter-stack semiconductor body elements 1520 in the bit line structures, as illustrated in FIG. 2 have.

18 illustrates the connection elements 1861, 1862, 1863, 1861, 1861, 1861, 1861, 1861, 1861, Lt; RTI ID = 0.0 > a < / RTI > step etch process. Pads used for connecting elements 1861, 1862, 1863 can be patterned at the same time when the stacks are patterned (see FIG. 12).

In one embodiment, as illustrated in FIG. 4, at least a group 430 of connection elements 440 in the bit line structures and in the at least one reference line structure are formed on the intermediate surfaces WL And a second set of word lines in the middle planes (WL) and are arranged orthogonally on top of the first set of word lines in the first set (410) 471 to 474 are aligned on the sides of the group 430 parallel to the bit lines in the group 430 and interlayer connectors 491 to 492 for the second set 420 are aligned Are aligned on the same side of the group 430.

In an alternative embodiment, the connection elements 531-533 in the bit line structures and at least the group 530 of connection elements 540 in the at least one reference line structure, as illustrated by FIG. 5, Is arranged orthogonally on a first set of word lines (510) in the intermediate planes (WL) and a second set of word lines (520) in the intermediate planes (WL) Layer interconnects 571 to 574 for the second set 520 are aligned on the sides of the group 530 parallel to the bit lines in the group 530, (591-594) are aligned on opposite sides of the group (530).

In one embodiment, the process flow forms blocks comprising interconnection elements connecting sets of word lines in the intermediate planes (WL) and interlayer interconnects connected to landing areas within the interconnection elements The ends of the word lines in adjacent blocks being connected through the connecting elements and the connecting elements passing through the interlayer connectors connected to the landing areas in the lower intermediate plane extensions Apertures. The process flow may further include forming sidewall silicide formations on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks. The sidewall silicide formations may be formed by depositing silicide on the sidewalls of CoSix (cobalt silicide), TiSix (titanium silicide), or, for example, on the sidewalls of the set of word lines, using other silicide (self-aligned silicide) Silicide < / RTI > compounds.

19-24 illustrate an exemplary process flow for an embodiment of a sidewall silicide formation in a vertical channel structure. Figure 19 illustrates the case of Figure 11 comprising conductive strips 1930, 1940, 1950, 1960 (WL ₀ , WL _N-1 ) of the intermediate surface separated by an insulating material 1905 after the word line separation process Sectional view orthogonal to the conductive strips within the same structure. The separation process may be a patterned etch to cut into multiple sets of word lines to expose the sidewalls of said intermediate conductive strip _{(WL 0, WL N-1} ). FIG. 19 illustrates a first set of word lines 1910, a second set of word lines 1920 and a space 1915 between the two sets, with individual word lines formed.

Although the top surfaces of the conductive strips SSLs and the bottom surfaces GSL of the conductive strips are not shown in Figs. 19-24, the process flow is shown on the sides of the set of string selection lines in the top surface, Forming a sidewall silicide formation on the sides of the set of ground select lines on the bottom surface.

Figure 20 illustrates the steps in the process after the process of forming a silicide on the exposed sides between the conductive strips 1930, 1940, 1950, 1960 while preventing silicide formation on the opposing sides. do. The silicide can be formed by depositing a thin suicide precursor, such as a transition metal layer 2090, on top of the sidewalls of the two sets of word lines. Thereafter, the structure is such that the silicide precursor reacts with the conductive material in the intermediate planes WL ₀ , WL _N-1 to form sidewall silicide formations 1939 for the first set of word lines 1910, 1959) and sidewall silicide formations 1941, 1961 for the second set of word lines 1920. The first set of word lines 1920, As shown in Fig. 21, after the reaction to form the sidewall silicide formations 1939, 1959, 1941 and 1961, the residual or excess transition metal is etched away.

Figure 22 illustrates the steps of etching the plurality of layers to divide the conductive strips 1930, 1940, 1950, 1960, which form the divided strips 1931, 1933, 1943, 1945, 1951, 1953, 1963, The steps in the above process are illustrated. The divided strips may include stacks 2210 and 2220 for a first set of word lines 1910 and a plurality of conductive strips 2230 and 2240 such as stacks 2230 and 2240 for a second set of word lines 1920. [ Lt; / RTI > The stacks include at least a bottom surface GSL (not shown) of conductive strips, intermediate surfaces WLs of a plurality of conductive strips, and an upper surface (not shown) of conductive strips SSLs. The plurality of intermediate surfaces may include N surfaces ranging from 0 to N-1.

Figure 23 is a cross-sectional view of a portion of the memory layer 2390 after forming the memory layer 2390 on the side surfaces of the conductive strips in the plurality of stacks in areas not covered by the sidewall silicide formations 1939, 1959, 1941, The steps in the process are illustrated. The memory layer 2390 contacts the side surfaces of the plurality of conductive strips.

Figure 24 illustrates a method of forming a layer of a second conductive material to form a vertical interstack semiconductor body element 2490 having a conformal surface on the memory layer 2390 above the memory layer 2390 on the plurality of stacks The steps in the above process are illustrated. The space 1915 between the two sets of word lines is filled with insulating material 2480 at some location within the process flow. A double-gate flash memory cell (region 2395) is formed between the vertical stack of inter-stack semiconductor body elements 2490 of the bit line structure and the cross-points of the conductive strips 1951 and 1953 and other similar cross- Dimensional memory array. The process flow may then continue to etch the layers and other members of the second conductive material as described with reference to FIG.

25-33 illustrate an exemplary process flow for alternative embodiments of sidewall silicide formation in a vertical channel structure. In an alternative embodiment, charge storage structures are formed at the interface (s) at the cross-points between the first side of the word lines in the intermediate planes (WLs) and the side surfaces of the semiconductor body elements between the stacks in the bit line structures Sidewall silicide formations are disposed on the side surfaces of the second side of the word lines opposite the first side of the intermediate surfaces (WLs) of the conductive strips in pairs of adjacent stacks. 25 illustrates a cross-section of a partially fabricated memory device. 25, the memory device includes a reference conductor layer 2501 and a plurality of sacrificial layers 2502 separated by an insulating material 2505 including sacrificial layers 2510, 2520, 2530, .

Figure 26 illustrates the steps in the process after etching the plurality of sacrificial layers to define a plurality of pairs of adjacent stacks by etching the plurality of sacrificial layers to form openings 2691 and 2692. [ The openings 2691 and 2692 are used to form interstack semiconductor body elements shared by pairs of adjacent stacks.

27 illustrates an opening 2790 using the second conductive material and extending to the reference conductor layer 2501 such that the sacrificial layers 2510, 2520, 2530 and 2540 are exposed and the pairs of adjacent stacks are separated. To form stacks of semiconductor body elements 2791 and 2792 in the openings 2691 and 2692, respectively.

FIG. 28 illustrates the steps in the process after removing the sacrificial layers 2510, 2520, 2530, 2540 exposed by openings such as the openings 2790. This etch process includes depositing a layer of insulating material 2505 in each of the stacks with openings (e.g., reference numeral 2801) attached to the second conductive material acting as the interstack semiconductor body element, Leaves.

FIG. 29 illustrates the steps in the process after forming the memory layer 2990 on the side surfaces of the interstack semiconductor body elements 2791, 2792. The memory layer 2990 may include a multilayer dielectric charge storage structure known from flash memory technologies including, for example, flash memory technologies known as SONOS, BE-SONOS, TANOS, and MA BE-SONOS.

FIG. 30 illustrates a cross-sectional view of an embodiment of a semiconductor memory device that fills the openings left by removal of the sacrificial layers between the layers of insulating material 2505 and includes a plurality of stacks of first conductive material The steps in the above process after forming the layers 3090 are illustrated.

31 is a cross-sectional view showing the bottom surface GSL of at least the conductive strips 3111, 3113, 3115 and 3117, the intermediate surfaces WLs of the conductive strips 3121, 3123, 3125 and 3127 and the conductive strips SSLs (E. G., See < RTI ID = 0.0 > reference), < / RTI > between the stacks of conductive strips to remove excess material in the layers 3090 of the first conductive material to define stacks including upper surfaces of the conductive strips 3141, 3143, 3145, 3101) is etched.

32 is a cross-sectional view illustrating the formation of a silicide on the sidewalls of the conductive strips 3111, 3113, 3115 and 3117, 3121, 3123, 3125 and 3127, 3131, 3133, 3135 and 3137 and 3141, 3143, 3145 and 3147 Illustrating steps in the process after the process, wherein the conductive strips comprise a silicon-containing material. The silicide process includes depositing a thin silicide precursor, such as a transition metal layer 3290, on top of the sidewalls of pairs of adjacent stacks. The silicide precursor then reacts with silicon in the conductive strips 3111, 3113, 3115 and 3117, 3121, 3123, 3125 and 3127, 3131, 3133, 3135 and 3137 and 3141, 3143, 3145 and 3147, 3124, 3136, and 3138, sidewall silicide formations 3142, 3144, 3146, and 3148, and sidewall silicide formations 3112, 3124, 3114, 3116, and 3118). ≪ / RTI >

Figure 33 illustrates the steps in the process after any excess silicide precursor is etched away. The fabrication process continues to complete a three-dimensional memory array, for example, with double-gate vertical channel NAND (NAND) strings, as described above.

While the invention has been described by way of preferred embodiments and examples in the foregoing description, it is to be understood that these examples are illustrative and that the invention is not so limited. Modifications and combinations will be apparent to those skilled in the art, and it is to be understood that such modifications and combinations are within the scope of the following claims and the spirit of the present invention.

100: memory device 101: bottom gate
120: stack stack semiconductor body element 130: connecting element
140: Vertical conductive element between stacks 150: Connecting element
160: Reference conductor 170: Reference selection switch
180: Cross point 190: String selection switch
211 to 216: Word lines 231 to 234: Bit line
235 to 238: bit line 240: source line
251: bit line contact 255: source line contact
281 to 288: first top line 290: second top layer
361, 362, 363: connection elements 371, 372, 373: interlayer connectors
410: first set of word lines 411 to 416: word line
420: second set of word lines 421 to 426: word line
431 to 438: connecting element 440: connecting element
451: bit line contact 455: source line contact
460: connecting elements 471 to 467: interlayer connectors
480: connecting elements 491 to 494: interlayer connectors
511 to 516: Word line 521 to 526: Word line
531 to 538: connecting element 540: connecting element
560: connecting elements 571 to 574: interlayer connectors
580: Connection elements 591 to 594: Interlayer connectors
602, 604: side wall silicide formation
606, 608: side wall silicide formation 610: word line
611, 613: conductive strips 615, 617: block
620: word line 621, 623: conductive strips
625, 627: block 660: connection element
671 to 674: interlayer connectors 680: connection element
691 to 694: interlayer connectors 710, 730, 740: dielectric charge storage layer
722, 752: Word line 724, 754: Word line
762, 764: side wall silicide formation 770: insulating oxide material
812, 814: Horizontal gate 820: Vertical channel
832, 834: charge storage structure 958: plane decoder
960: vertical channel memory array 961: row decoder
962: Word line 963: Column decoder
964: bit line 965: bus
966: block 968: block
969: bias alignment state machine 975: integrated circuit
1101: Auxiliary gate conductor 1105: Layer of insulating material
1110, 1120, 1130, 1140: separated layers 1210, 1211, 1212: stack
1310: memory layer 1410: layer of the second conductive material
1520: stack stack semiconductor body element 1530: connection element
1540: Vertical conductive element between stacks 1550: Connection element
1560: Reference conductor 1861, 1862, 1863: Connection element
1871, 1872, 1873: interlayer connector 1905: insulating material
1915: Space
1930, 1940, 1950, 1960: conductive strips
1931, 1933, 1943, 1945, 1951, 1963, 1965: conductive strips
1939, 1959: Sidewall silicide formation
1941, 1961: Side wall silicide formation
2090: metal layer 2210, 2220: stack
2390: memory layer 2480: insulating material
2490: Vertical Stack Semiconductor Body Element 2501: Reference conductor layer
2505: Insulating material 2510, 2520, 2530, 2540: sacrificial layer
2691, 2692: opening 2790: opening
2791, 2792: stack stack semiconductor body elements 2990: memory layer
3090: layer of first conductive material
3111, 3113, 3115, 3117: conductive strip
3112, 3114, 3116, 3118: side wall silicide formation
3121, 3123, 3125, 3127: conductive strips 3131, 3133: conductive strips
3122, 3124, 3126, 3128: side wall silicide formation
3132, 3134, 3136, 3138: side wall silicide formation
3141, 3143, 3145, 3147: conductive strip 3290: metal layer

Claims (34)

1. A memory device comprising an array of NAND strings of memory cells,
An integrated circuit substrate;
A stack of a plurality of conductive strips separated by an insulating material and comprising at least a bottom surface (GSL) of conductive strips, a plurality of intermediate surfaces (WLs) of conductive strips and an upper surface of conductive strips (SSLs) Stacks;
A reference conductor (CS) disposed within a level between the bottom surface of the conductive strips and the integrated circuit substrate;
Inter-stack semiconductor body elements between the stacks that are orthogonally aligned on top of the plurality of stacks and have conformal surfaces to the stacks and are connected to the reference conductors, A plurality of bit line structures including connection elements on top of the stacks connecting the interstack semiconductor body elements;
Wherein at least one of the inter-stack semiconductor body elements of the plurality of bit line structures and the inter-stack semiconductor body elements of the plurality of bit line structures within the interfacial areas at cross-points between the side surfaces of the conductive strips in the plurality of intermediate planes within the stacks Charge storage structures;
Stacked vertically conductive elements between the stacks that are orthogonally aligned on top of the plurality of stacks and are connected to the reference conductor and connection elements on top of the stacks that connect the stacked vertical conductive elements, At least one reference line structure in which the inter-stack vertical conductive elements have a higher conductivity than the inter-stack semiconductor body elements; And
And reference selection switches in the interfacial areas having the string selection switches in the interfacial areas having the upper surface of the conductive strips and the bottom surface of the conductive strips. 2. The memory device of claim 1, comprising a first upper conductive layer coupled to the plurality of bit line structures and including a plurality of global bit lines coupled to sense circuits. 2. The memory device of claim 1, comprising a second upper conductive layer coupled to the at least one reference line structure and coupled to a reference voltage source. 2. The memory device of claim 1, wherein the reference conductor comprises N + doped semiconductor material, and wherein the coupling elements of the at least one reference line structure comprise N + doped semiconductor material. 2. The memory device of claim 1, wherein the inter-stack vertical conductive elements of the at least one reference line structure comprise N + doped semiconductor material. 2. The memory device of claim 1, wherein the inter-stack vertical conductive elements in the at least one reference line structure have a larger cross-sectional area than the inter-stack semiconductor body elements in the bit line structures. The method according to claim 1,
Connecting elements connecting the sets of word lines in the intermediate planes (WLs); And
Further comprising interlayer interconnects connected to landing areas within the interconnecting elements, the interconnecting elements including openings through which interlayer conductors connected to landing areas within the lower intermediate plane extensions And said memory device. 8. The method of claim 7,
Connecting elements connecting sets of ground select lines in said bottom surface GSL; And
Further comprising interlayer connectors connected to landing areas in the connecting elements of the bottom surface, wherein the interlayer connectors extend through the openings in the connecting elements in the intermediate surfaces (WLs) / RTI > 8. The method of claim 7, wherein connecting elements in the bit line structures and at least a group of connecting elements in the at least one reference line structure are connected to a first set of word lines in the intermediate surfaces (WL) Wherein the interlayer interconnects for the first set are aligned on the sides of the group parallel to the bit lines in the group and the interlayer interconnects for the second set are aligned orthogonally over the second adjacent set of lines, Are arranged on the same side of the group. 8. The method of claim 7, wherein connecting elements in the bit line structures and at least a group of connecting elements in the at least one reference line structure are connected to a first set of word lines in the intermediate surfaces (WL) WL, the interlayer interconnects for the first set being aligned on the sides of the group parallel to the bit lines in the group, and the second set of word lines in the second set Are arranged on opposite sides of the group. ≪ Desc / Clms Page number 13 > The method according to claim 1,
Connecting elements connecting the sets of word lines in the intermediate planes (WLs)
Further comprising blocks comprising interlayer connectors connected to landing areas within the connection elements, the ends of the word lines in adjacent blocks being connected through the connection elements, The openings through which the interlayer connectors that are connected to the landing areas within the extension extend,
And sidewall silicide formations disposed on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks. The method according to claim 1,
Further comprising pairs of adjacent stacks in the stacks of the plurality of conductive strips, wherein charge storage structures are formed between the word lines in the intermediate planes (WLs) and the side surfaces of the semiconductor body elements between the stacks in the bit line structures Are placed in the interface region at the cross-points between them,
And sidewall silicide formations disposed on a side surface of a second side of the word lines opposite the first side of the conductive strips of the intermediate surface (WLs) in the pairs of adjacent stacks. Device. A method of manufacturing a memory device,
Forming a plurality of layers of a first conductive material on the integrated circuit substrate separated by an insulating material;
Etching the plurality of layers such that the stacks define stacks of a plurality of conductive strips including at least the bottom surface (GSL) of the conductive strips, the intermediate surfaces (WLs) of the conductive strips and the top surface of the conductive strips (SSLs) ;
Forming a memory layer in contact with the side surfaces of the plurality of conductive strips on the side surfaces of the conductive strips in the plurality of stacks;
Forming a layer of a second conductive material having a conformed surface on the memory layer above the memory layer on the plurality of stacks; And
Etching the layer of the second conductive material to define a plurality of bit line structures, at least one reference line structure, and a reference conductor (CS)
Wherein the bit line structures are arranged orthogonally to the top of the plurality of stacks and have conformal surfaces on the stacks and between stacks of semiconductor body elements between the stacks in electrical communication with the reference conductor, And connection elements on top of the stacks connecting semiconductor body elements between the stacks,
Wherein the at least one reference conductor structure is arranged orthogonally to the top of the plurality of stacks, and wherein between the stack vertical conductive elements between the stacks in electrical communication with the reference conductor and between the stack vertical conductive elements Said stacking elements having a plurality of stacking elements,
Wherein the reference conductor (CS) is disposed in a level between a bottom surface of the conductive strips and the integrated circuit substrate. 14. The method of claim 13, further comprising implanting an N + doping material at a first energy level on the coupling elements of the plurality of bit line structures, the reference conductor and the coupling elements of the at least one reference line structure ≪ / RTI > 14. The method of claim 13, further comprising: injecting an N + doping material at a first energy level onto the coupling elements in the plurality of bit line structures, the reference conductor and the at least one reference line structure; And
Implanting an N + doping material at a second energy level onto the stack of vertical conductive elements of the at least one reference conductive line structure,
Wherein the second energy level is greater than the first energy level. 14. The method of claim 13, wherein the inter-stack vertical conductive elements in the at least one reference line structure have a larger cross-sectional area than the inter-stack semiconductor body elements in the bit line structures. 14. The method of claim 13, wherein etching the plurality of layers comprises forming connection elements connecting sets of word lines in the intermediate planes (WLs)
Forming openings in the connecting elements; And
Further comprising forming interlayer connectors that are connected to landing areas within the connection elements, wherein the interlayer connectors connected to the landing areas in the lower intermediate surfaces extend through the openings in the connection elements ≪ / RTI > 18. The method of claim 17, wherein etching the plurality of layers comprises forming connecting elements connecting sets of ground select lines in the bottom surface (GSL), wherein landing in the connecting elements Further comprising the step of forming interlayer connectors which are connected to the regions, said interlayer connectors extending through said openings in said connecting elements in said intermediate surfaces (WLs). 18. The method of claim 17, wherein the connecting elements in the bit line structure and at least a group of connecting elements in the at least one reference line structure are connected to a first set of word lines in the middle surfaces (WL) ), The interlayer interconnects for the first set being aligned on the sides of the group parallel to the bit lines in the group, and the second set of word lines in the second set Lt; / RTI > are arranged on the same side of said group. 18. The method of claim 17, wherein connecting elements in the bit line structures and at least a group of connecting elements in the at least one reference line structure form a first set of word lines in the intermediate surfaces (WL) WL), the interlayer interconnects for the first set being aligned on the sides of the group parallel to the bit lines in the group, the second interlevel interconnects for the first set being aligned on the second adjacent set of word lines in the second Wherein the interlayer connectors for the set are aligned on opposite sides of the group. 14. The method of claim 13,
Further comprising forming blocks comprising interconnection elements connecting the sets of word lines in the intermediate planes (WLs) and interlayer interconnects connected to landing areas in the interconnection elements, Wherein the ends of the word lines in the word lines are connected through the coupling elements and the coupling elements have openings through which the interlayer connectors connect to the landing areas in the lower intermediate plane extension,
Further comprising forming sidewall silicide formations on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks. 14. The method of claim 13,
Forming pairs of adjacent stacks in the stacks of the plurality of conductive strips, wherein charge storage structures are formed on the first side of the word lines in the intermediate planes (WLs) and in the plurality of bit line structures Disposed in the face regions at cross-points between the side surfaces of the inter-stack semiconductor body elements,
Forming sidewall silicide formations on the side surfaces of the second side of the word lines opposite to the first side in the intermediate surfaces (WLs) of the conductive strips in the pairs of adjacent stacks Lt; / RTI > 14. The method of claim 13 including forming a first top conductive layer having a plurality of global bit lines coupled to the plurality of bit line structures and coupled to sensing circuits. 14. The method of claim 13, comprising forming a second upper conductive layer coupled to the at least one reference line structure and connected to a reference voltage source. 1. A memory device comprising an array of NAND strings of memory cells,
An integrated circuit substrate;
Stacks of a plurality of conductive strips separated by an insulating material and comprising at least the bottom surfaces (GSL) of the conductive strips, the intermediate surfaces (WLs) of the conductive strips and the upper surfaces of the conductive strips (SSLs);
Stacks of stacked semiconductor body elements and stacks of stacks of semiconductor body elements that are aligned orthogonally over the plurality of stacks and have conformed surfaces on the stacks, A plurality of bit line structures having elements;
Charge storage structures in interfacial areas at cross-points between the conductive strips in the stacks and the side surfaces of semiconductor body elements between the stacks of bit line structures;
At least one reference line structure arranged orthogonally over the plurality of stacks and having connection elements between the stacks of vertical conductive elements between the stacks and the stacks connecting the vertical conductive elements between the stacks; And
And sidewall silicide formations disposed on side surfaces of at least one side of the conductive strips in the stacks opposite the at least one second side of the conductive strips, Wherein said charge storage structures are formed. 26. The method of claim 25,
Further comprising blocks comprising interconnecting elements connecting sets of word lines in the intermediate planes (WLs) and interlayer interconnects connected to landing areas in the interconnecting elements, wherein the word lines in adjacent blocks End portions are connected through the connecting elements, the connecting elements having openings through which interlayer connectors are connected which are connected to landing areas in the lower intermediate plane extensions,
And sidewall silicide formations disposed on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks. 26. The method of claim 25,
Further comprising: pairs of adjacent stacks in the stacks of the plurality of conductive strips, wherein charge storage structures are formed between the first side of the word lines in the intermediate planes (WLs) and the interstack semiconductor body in the plurality of bit line structures Disposed in interfacial areas at cross-points between the side surfaces of the elements,
And sidewall silicide formations disposed on the side surfaces of the second side of the word lines opposite the first side of the intermediate surfaces (WLs) of the conductive strips in the pairs of adjacent stacks. Device. 26. The method of claim 25, wherein the coupling elements in the bit line structures and at least a group of coupling elements in the at least one reference line structure are connected to a first set of word lines in the intermediate surfaces (WL) WL), the interlayer connectors for the first set being aligned on the sides of the group parallel to the bit lines in the group, and the second set of word lines Are arranged on the same side of the group. 26. The method of claim 25, wherein the coupling elements in the bit line structures and at least a group of coupling elements in the at least one reference line structure are connected to a first set of word lines in the intermediate surfaces (WL) WL), the interlayer connectors for the first set being aligned on the sides of the group parallel to the bit lines in the group, and the second set of word lines Are arranged on opposite sides of the group. ≪ Desc / Clms Page number 13 > A method of manufacturing a memory device,
Forming a plurality of layers of a first conductive material on the integrated circuit substrate separated by an insulating material;
Etching the plurality of layers to define stacks of a plurality of conductive strips including at least the bottom surface (GSL) of the conductive strips, the intermediate surfaces (WLs) of the conductive strips and the top surface of the conductive strips (SSLs);
Forming on the side surfaces of the plurality of stacks a memory layer in contact with the side surfaces of the plurality of conductive strips;
Forming a layer of a second conductive material having a conformed surface on the memory layer above the memory layer on the plurality of stacks;
Etching the layer of the second conductive material to define a plurality of bit line structures and at least one reference line structure,
Wherein the bit line structures are arranged orthogonally to the top of the plurality of stacks and have conformed surfaces on the stacks, and wherein between the stack semiconductor body elements and the stack And a connecting element on the upper portion,
Wherein the at least one reference line structure is arranged orthogonally to the top of the plurality of stacks and includes vertical stacked conductive elements between the stacks and connecting elements on top of the stacks connecting the stacked vertical stacked conductive elements In addition,
Forming sidewall silicide formations on at least one of the side surfaces of the conductive strips in the stacks opposite the at least one second side of the conductive strips, Lt; RTI ID = 0.0 > 1, < / RTI > 31. The method of claim 30,
Further comprising forming blocks comprising interconnection elements connecting the sets of word lines in the intermediate planes (WLs) and interlayer connectors connected to the interconnection elements, wherein the word lines in adjacent blocks End portions are connected through the connecting elements, the connecting elements having openings through which interlayer connectors are connected which are connected to landing areas in the lower intermediate plane extensions,
Further comprising forming sidewall silicide formations on at least one side of adjacent blocks parallel to the word lines in the adjacent blocks. 31. The method of claim 30,
Forming pairs of adjacent stacks in the stacks of the plurality of conductive strips, wherein charge storage structures are formed on the first side of the word lines in the intermediate planes (WLs) and in the plurality of bit line structures Disposed in interfacial regions at cross-points between the side surfaces of the interstack semiconductor body elements,
And forming sidewall silicide formations on the side surfaces of the second side of the word lines opposite the first side in the intermediate surfaces (WLs) of the conductive strips in the pairs of adjacent stacks How to. 32. The method of claim 30 wherein at least one of the connecting elements in the bit line structures and at least one of the reference line structures in the at least one reference line structures comprises a first set of word lines in the middle surfaces (WL) Are arranged orthogonally on top of a second adjacent set of word lines in the word line WL, interlayer interconnects for the first set are aligned on the sides of the group parallel to the bit lines in the group, Wherein the interlayer connectors for the set are aligned on the same side of the group. 32. The method of claim 30 wherein at least one of the connecting elements in the bit line structures and at least one of the reference line structures in the at least one reference line structures comprises a first set of word lines in the middle surfaces (WL) Are arranged orthogonally on top of a second adjacent set of word lines in the word line WL, interlayer interconnects for the first set are aligned on the sides of the group parallel to the bit lines in the group, Wherein the interlayer connectors for the set are aligned on opposite sides of the group.

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