KR20110012112A - In plane switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: An in-plane switching mode liquid crystal display device and a manufacturing method thereof for increasing aperture ratio as wide as an active tail are provided to manufacture an array substrate without the active tail in a mask process. CONSTITUTION: A common electrode line is connected to one side of the common electrode. A data pad electrode is electrically connected with a data pad line through a third contact hole. A gate pad electrode(126p) is electrically connected with a gate pad line through a fourth contact hole. A protective layer is formed on a first substrate except for the common electrode, a pixel electrode, a pixel electrode line and the gate pad electrode.

Description

Transverse electric field type liquid crystal display device and manufacturing method thereof {IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device and a manufacturing method thereof, and more particularly, to a transverse electric field method capable of reducing the number of masks, simplifying the manufacturing process, improving yield, and repairing disconnection defects of data lines. A liquid crystal display device and a manufacturing method thereof.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 defining a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is narrow. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules aligned horizontally with the substrate are aligned in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

Accordingly, a transverse electric field type liquid crystal display device, in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate, has been developed, which will be described in detail with reference to FIG. 2.

2 is a plan view schematically illustrating a portion of an array substrate of a general transverse electric field type liquid crystal display device.

As shown in the drawing, the array substrate 10 of a general transverse electric field type liquid crystal display device has a gate line 16 and a data line 17 arranged vertically and horizontally on the array substrate 10 to define a pixel area. Is formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 16 and the data line 17, and a common electrode 8 driving a liquid crystal (not shown) by generating a transverse electric field in the pixel area. And the pixel electrode 18 are alternately formed.

The thin film transistor is connected to the pixel electrode 18 through a gate electrode 21 constituting a part of the gate line 16, a source electrode 22 connected to the data line 17, and a pixel electrode line 18l. It consists of the drain electrode 23 electrically connected. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 22 and the drain electrode 23 by the gate voltage supplied to the gate electrode 21.

A portion of the source electrode 22 extends in one direction to form a portion of the data line 17, and a portion of the drain electrode 23 extends toward the pixel region to form a first contact hole formed in a passivation layer (not shown). Electrically connected to the pixel electrode line 18l and the pixel electrode 18 through 40a.

As described above, a plurality of common electrodes 8 and pixel electrodes 18 for generating a transverse electric field are alternately arranged in the pixel region.

In this case, a common line 8L is formed at a lower end of the pixel area substantially parallel to the gate line 16, and a pair of first connected to the common line 8L is formed at left and right edges of the pixel area. Lines 8a and 8a 'are formed.

In this case, the plurality of common electrodes 8 are connected to each other by a common electrode line 8l at an upper end of which the one side is disposed substantially parallel to the gate line 16, and the common electrode line 8l is The second contact hole 40b formed in the passivation layer is electrically connected to the first lines 8a and 8a '.

In this case, a portion of the pixel electrode line 18l overlaps a portion of the common line 8L below the gate insulating layer (not shown) and the passivation layer to form a storage capacitor Cst. .

In order to fabricate an array substrate including the thin film transistor configured as described above, a total of five photolithography processes are generally required for patterning a gate electrode, an active pattern, a source / drain electrode, a contact hole, and a pixel electrode.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. It has the disadvantage of dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

At this time, by forming the active pattern and the source / drain electrodes in a single mask process using a diffraction mask, a technique for manufacturing an array substrate using a total of four mask processes has been developed.

However, the liquid crystal display device having the above structure is patterned to the source electrode, the drain electrode and the data line, that is, the lower periphery of the data line, by patterning the active pattern and the source / drain electrode through two etching processes by using a diffraction mask. The active tail from which the active pattern protrudes remains.

The active tail is formed of a pure amorphous silicon thin film, and the protruding active tail is exposed to the backlight of the lower portion so that photocurrent is generated by the backlight. At this time, due to the minute flickering of the backlight light, the amorphous silicon thin film reacts finely, and the activation and deactivation states are repeated, thereby causing a change in the photocurrent. The photocurrent component is coupled with a signal flowing to a neighboring pixel electrode to distort the movement of the liquid crystal located in the pixel electrode. As a result, wavy noise in which wavy thin lines appear on the screen of the liquid crystal display is generated.

In addition, the active tail positioned below the data line protrudes a predetermined distance to both sides of the data line, so that the opening ratio of the liquid crystal display device decreases as the opening area of the pixel portion is eroded by the protruding distance.

Meanwhile, the array substrate manufactured as described above is combined with the color filter substrate to form a liquid crystal display device. The manufacturing method of the liquid crystal display device includes an array process of forming a switching element on the array substrate and a color filter on the color filter substrate. The array substrate and the color filter substrate fabricated through each of the array process and the color filter process are finally bonded to each other through a cell process to form a liquid crystal display panel. .

The cell process has almost no repeated process compared to the array process or the color filter process, and the alignment film forming process, the cell gap forming process, the cell cutting process, and the liquid crystal injection process are largely used for the alignment of liquid crystal molecules. Can be divided into On the other hand, the liquid crystal display panel manufactured through such a process is selected through quality inspection, and after attaching polarizing plates to the outside of the liquid crystal display panel selected as good products, connecting the driving circuit, the liquid crystal display device is completed.

In this case, when a defective pixel is found in the inspection process of the liquid crystal display device described above, a repair process is performed.

A defect of the liquid crystal display device may include short defects between adjacent defects and point defects such as color defects of pixels, bright spots (always on), dark spots (always off), and the like. , Line defects caused by the destruction of the switching element by open and static electricity.

In particular, a laser repair process using a laser is generally used to repair disconnection defects such as the open, but the laser repair process requires expensive laser repair equipment and the laser repair should be performed by an inspector. Therefore, there is a disadvantage in that a loss of production occurs due to the addition of a repair process.

An object of the present invention is to provide a transverse electric field type liquid crystal display device and a method of manufacturing the same, which fabricate an array substrate having no active tail in three mask processes.

Another object of the present invention is to provide a transverse electric field type liquid crystal display device and a method of manufacturing the same, which can realize high brightness by enlarging an opening area and at the same time not generating wave noise.

Another object of the present invention is to provide a transverse electric field type liquid crystal display device capable of self repair of disconnection of a data line without the addition of a repair process, and a manufacturing method thereof.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, a transverse electric field type liquid crystal display device of the present invention comprises a first substrate divided into a pixel portion and a pad portion; A gate electrode, a gate line, a first line, and a dummy pattern formed on the pixel portion of the first substrate and formed of a first conductive film; A data pad line and a gate pad line formed on a pad portion of the first substrate and formed of the first conductive layer; A gate insulating film formed on the first substrate; An active pattern formed on the gate electrode and formed of an amorphous silicon thin film; A first contact hole removing a portion of the gate insulating layer to expose a portion of the dummy pattern; A second contact hole exposing a portion of the first line by removing a portion of the gate insulating layer; A third contact hole and a fourth contact hole which remove portions of the gate insulating layer to expose portions of the data pad line and the gate pad line, respectively; A source / drain electrode formed of a third conductive layer on the gate electrode and electrically connected to a source / drain region of the active pattern; A data line formed of the third conductive layer on the dummy pattern and defining a pixel area crossing the gate line, and electrically connected to a dummy pattern under the first contact hole; A common electrode and a pixel electrode formed of a second conductive film in the pixel region and alternately arranged to generate a transverse electric field; A pixel electrode line formed of the second conductive layer and connected to one side of the pixel electrode to electrically connect the drain electrode and the pixel electrode; A common electrode line formed of the second conductive layer and electrically connected to the first line through the second contact hole, and connected to one side of the common electrode; A data pad electrode formed of the second conductive layer and electrically connected to the data pad line through the third contact hole, and a gate pad electrode electrically connected to the gate pad line through the fourth contact hole; A passivation layer formed on the entire surface of the first substrate excluding the common electrode, the pixel electrode, the common electrode line, the pixel electrode line, the gate pad electrode, and the data pad electrode; And a second substrate bonded to and opposed to the first substrate.

In addition, the method of manufacturing a transverse electric field type liquid crystal display device of the present invention comprises the steps of: providing a first substrate divided into a pixel portion and a pad portion; Forming a gate electrode, a gate line, and a dummy pattern formed of a first conductive layer on the pixel portion of the first substrate through a first mask process; Forming a gate insulating film on the first substrate; Forming an active pattern made of an amorphous silicon thin film on the gate electrode through a second mask process; Selectively patterning the gate insulating layer using the second mask process to form a first contact hole exposing a portion of the dummy pattern; Forming a source / drain electrode on the gate electrode through a third mask process, the source / drain electrode electrically connected to a source / drain region of the active pattern; The third conductive layer is formed on the dummy pattern by using the third mask process, and defines a pixel area intersecting the gate line, and electrically connects the dummy pattern under the first contact hole. Forming a data line to connect; Forming a common electrode and a pixel electrode formed of a second conductive layer in the pixel region by using the third mask process and alternately arranged to generate a transverse electric field; And bonding the first substrate and the second substrate to each other.

As described above, the transverse electric field type liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the transverse electric field type liquid crystal display device and the method of manufacturing the same according to the present invention have no active tail, and thus there is no signal interference of the data line, and the aperture ratio increases by the width of the active tail.

In addition, the transverse electric field type liquid crystal display device and the method of manufacturing the same according to the present invention provide an effect that can produce a high-quality liquid crystal display device without the generation of wave noise.

In addition, the transverse electric field type liquid crystal display device and a method of manufacturing the same according to the present invention form a dummy pattern under the data line so as to be connected to the data line through a hole, thereby preventing disconnection of the data line caused by two times of etching. Provides the effect of self repair.

Hereinafter, exemplary embodiments of a transverse electric field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a plan view schematically illustrating a portion of an array substrate of an in plane switching (IPS) liquid crystal display device according to an exemplary embodiment of the present invention, and for convenience of description, a thin film of a gate pad part, a data pad part, and a pixel part. One pixel including a transistor is shown.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

In this case, the present embodiment has been described using a transverse electric field type liquid crystal display as an example, but the present invention is not limited thereto, and the present invention may be applied to a twisted nematic liquid crystal display.

As described above, the twisted nematic liquid crystal display device has a disadvantage that the viewing angle is narrow. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules aligned horizontally with the substrate are aligned in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

Accordingly, a transverse electric field type liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve a viewing angle has been developed, and the present invention illustrates the transverse field type liquid crystal display device as an example.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 according to an embodiment of the present invention, which are arranged vertically and horizontally on the array substrate 110 to define a pixel region. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117, and a common electrode 108 for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel region. And the pixel electrode 118 are alternately formed.

The thin film transistor is connected to the pixel electrode 118 through a gate electrode 121 constituting a part of the gate line 116, a source electrode 122 connected to the data line 117, and a pixel electrode line 118l. The drain electrode 123 is electrically connected. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. In this case, although the shape of the source electrode 122 is "U" shaped and the channel is "U" shaped, for example, a thin film transistor is illustrated, but the present invention is not limited thereto. Applicable regardless of the channel type of the transistor.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to extend the pixel through the pixel electrode line 118l. It is electrically connected to the electrode 118.

In this case, the source electrode 122, the drain electrode 123 and the data line 117 according to an embodiment of the present invention may be made of a low-resistance conductive material such as copper, to prevent the diffusion of the copper below A source electrode pattern (not shown) made of a conductive material such as molybdenum titanium (MoTi) and patterned to have substantially the same shape as the source electrode 122, the drain electrode 123, and the data line 117 to improve adhesion characteristics. ), A drain electrode pattern (not shown) and a data line pattern (not shown) are formed, respectively.

In addition, the transverse electric field type liquid crystal display according to the exemplary embodiment of the present invention has a dummy pattern 114 formed of a conductive material constituting the gate electrode 121 and the gate line 116 under the data line 117. The dummy pattern 114 is connected to the upper data line 117 through the first contact hole 140a formed in the gate insulating layer (not shown). In this case, the first contact hole 140a is formed to be positioned at the upper and lower ends of the dummy pattern 114, for example, but the present invention is not limited thereto, and the first contact hole is not limited thereto. 140a may be composed of two or more so as to be self-repaired by being connected to the dummy pattern 114 at the bottom even if a disconnection defect occurs when a part of the data line 117 is opened by two etchings. Can be.

As described above, a plurality of common electrodes 108 and pixel electrodes 118 for generating a transverse electric field are alternately arranged in the pixel region.

In this case, a common line 108L is formed at a lower end of the pixel area substantially parallel to the gate line 116, and a pair of first connected to the common line 108L is formed at left and right edges of the pixel area. Lines 108a and 108a 'are formed.

In this case, the pair of outermost pixel electrodes 118 adjacent to the data line 117 among the plurality of pixel electrodes 118 overlaps a part of the pair of first lines 108a and 108a ', respectively. On the other hand, the plurality of common electrodes 108 are connected to each other by the common electrode line (108l) of the upper side of which one side is disposed substantially parallel to the gate line (116). The common electrode line 108l is electrically connected to the first lines 108a and 108a 'through a second contact hole 140b formed in a passivation layer (not shown), thereby connecting the common line 108L. The common voltage is applied to the plurality of common electrodes 108.

The first lines 108a and 108a 'are made of the same opaque conductive material as the common line 108L, the gate electrode 121, and the gate line 116, and the common electrode 108 and the pixel electrode 118 ), The common electrode line 108l and the pixel electrode line 118l may be made of the same conductive material as the source electrode pattern, the drain electrode pattern, and the data line pattern.

In this case, a portion of the pixel electrode line 118l overlaps a portion of the common line 108L below the gate insulating layer with the gate insulating layer therebetween to form a storage capacitor Cst. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal. In addition to maintaining the signal, the storage capacitor has effects such as stabilization of gray scale display and reduction of flicker and afterimage.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives a scan signal from a driving circuit or receives a data signal through a gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140c and 140d represent a third contact hole and a fourth contact hole formed in the gate insulating layer, wherein the data pad electrode 127p is connected to the data pad line through the third contact hole 140c. 117p). In addition, the gate pad electrode 126p is electrically connected to the gate pad line 116p through the fourth contact hole 140d.

In this case, as illustrated in FIG. 3, when the common electrode 108, the pixel electrode 118, and the data line 117 have a bent structure, the liquid crystal molecules are arranged in two directions. By forming a two-domain, the viewing angle is further improved compared to the mono-domain. However, the present invention is not limited to the two-domain transverse electric field liquid crystal display device, and the present invention can be applied to the transverse electric field liquid crystal display device having a multi-domain structure of two or more domains. For reference, an IPS structure for forming a multi-domain of two or more domains is referred to as an S-IPS (Super-IPS) structure.

In addition, when the common electrode 108, the pixel electrode 118, and the data line 117 are formed in a bent structure to form a multi-domain structure in which the driving directions of the liquid crystal molecules are symmetrical, birefringence of the liquid crystal is performed. The color shift phenomenon can be minimized by canceling the extraordinary light due to the?

In addition, the active pattern according to the embodiment of the present invention is formed of an amorphous silicon thin film, and is formed in an island shape only on the gate electrode 121, thereby reducing the off current of the thin film transistor.

Here, the transverse electric field type liquid crystal display device according to the embodiment of the present invention uses a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask) and a lift-off using By simultaneously patterning the data line, the pixel / common electrode, and the passivation layer, an array substrate can be fabricated by a total of three mask processes, which will be described in detail with the following method of manufacturing a transverse electric field type liquid crystal display device.

4A to 4C are cross-sectional views sequentially illustrating a manufacturing process along lines IIIa-IIIa ', IIIb-IIIb, and IIIc-IIIc' of the array substrate illustrated in FIG. 3, and an array substrate is manufactured on the left side of the array substrate. The right side shows a step of manufacturing an array substrate of a pad part consisting of a data pad part and a gate pad part.

5A to 5C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

As shown in FIGS. 4A and 5A, the gate electrode 121, the gate line 116, the first lines 108a and 108a ', and the pixel portion of the array substrate 110 made of a transparent insulating material such as glass, The common line 108L and the dummy pattern 114 are formed, and the gate pad line 116p and the data pad line 117p are formed in the pad portion.

In this case, the common line 108L is formed under the pixel area in a direction substantially parallel to the gate line 116, and the first lines 108a and 108a ′ are formed at left and right edges of the pixel area. It is formed to be connected to the common line 108L.

In addition, the dummy pattern 114 is formed in the data line region where the data line is to be formed, and is formed so as not to overlap with the first lines 108a and 108a 'and the common line 108L.

In this case, the gate electrode 121, the gate line 116, the first lines 108a and 108a ', the common line 108L, the dummy pattern 114, the gate pad line 116p and the data pad line 117p. The first conductive film is deposited on the entire surface of the array substrate 110 and then selectively patterned through a photolithography process (first mask process).

Aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy as the first conductive layer Low resistance opaque conductive materials such as the like can be used. In addition, the first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIGS. 4B and 5B, the gate electrode 121, the gate line 116, the first lines 108a and 108a ', the common line 108L, the dummy pattern 114, and the gate are shown. After forming the gate insulating film 115a, the amorphous silicon thin film, and the n + amorphous silicon thin film on the entire surface of the array substrate 110 on which the pad line 116p and the data pad line 117p are formed, a photolithography process (second mask process) is performed. The active pattern 124 made of the amorphous silicon thin film is formed by selectively removing through the pixel portion of the array substrate 110.

In this case, the first contact hole 140a exposing a part of the dummy pattern 114 to the pixel portion of the array substrate 110 by selectively removing a portion of the gate insulating film 115a through the second mask process. ) And a second contact hole 140b exposing portions of the first lines 108a and 108a '.

In addition, a third contact hole exposing a portion of the data pad line 117p to a pad portion of the array substrate 110 by selectively removing a portion of the gate insulating layer 115a through the second mask process. A fourth contact hole 140d exposing a portion 140c and a portion of the gate pad line 116p is formed.

In this case, an n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and patterned in substantially the same shape as the active pattern 124 is formed on the active pattern 124.

Here, the active pattern 124 and the first contact hole 140a to the fourth contact hole 140d according to the embodiment of the present invention are processed in one mask process (second mask process) using a half-tone mask. The second mask process will be described in detail with reference to the accompanying drawings.

6A through 6F are cross-sectional views illustrating a second mask process according to an exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 4B and 5B.

As shown in FIG. 6A, the gate electrode 121, the gate line 116, the first lines 108a and 108a ', the common line 108L, the dummy pattern 114, the gate pad line 116p and The gate insulating layer 115a, the amorphous silicon thin film 120, and the n + amorphous silicon thin film 125 are formed on the entire surface of the array substrate 110 on which the data pad line 117p is formed.

6B, after forming the first photoresist film 170 made of photosensitive material such as photoresist on the entire surface of the array substrate 110, the first half-tone mask according to the embodiment of the present invention. Light is selectively irradiated to the first photoresist layer 170 through 180.

In this case, the first half-tone mask 180 blocks the first transmission region I transmitting all of the irradiated light and the second transmission region II transmitting only a part of the light and blocking part of the light and all the irradiated light. The blocking region III is provided, and only the light passing through the half-tone mask 180 is irradiated to the first photoresist film 170.

Subsequently, after developing the first photoresist layer 170 exposed through the first half-tone mask 180, as shown in FIG. 6C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 170a and the second photoresist pattern 170b having a predetermined thickness remain in the region where all the light is blocked or partially blocked by the light, and the first transmission region I through which all the light is transmitted 1 the photoresist is completely removed to expose the surface of the n + amorphous silicon thin film 125.

In this case, the first photoresist pattern 170a formed in the blocking region III is thicker than the second photoresist pattern 170b formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. May be used.

Next, as illustrated in FIG. 6D, the gate insulating film 115a and the amorphous silicon thin film 120 formed under the first photoresist film pattern 170a and the second photoresist film pattern 170b are formed as masks. ) And n + amorphous silicon thin film 125 are selectively removed.

6D illustrates an example in which the dummy pattern 114, the common electrode line (not shown), and the gate insulating layer 115a on the pad part lines 116p and 117p remain to be partially patterned. In order to prevent the dummy pattern 114, the common electrode line and the pad part lines 116p and 117p from being damaged by plasma during ashing of the photosensitive film, the present invention is not limited thereto. A portion of the dummy pattern 114 and the common electrode line and the pad portion line 116p and 117p may be exposed by removing the gate insulating layer 115a over the 114 and the common electrode line and the pad portion line 116p and 117p. can do.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a and the second photoresist pattern 170b is performed, as illustrated in FIG. 6E, the second photoresist layer of the second transmission region II is formed. The pattern will be completely removed.

In this case, the first photoresist layer pattern is a third photoresist layer pattern 170a 'from which the thickness of the second photoresist layer pattern is removed and remains only in the active pattern region corresponding to the blocking region III.

Thereafter, as shown in FIG. 6F, the array substrate 110 is selectively removed by using the remaining third photoresist pattern 170a ′ as a mask to selectively remove the gate insulating film 115a, the n + amorphous silicon thin film, and the amorphous silicon thin film. The active pattern 124 made of the amorphous silicon thin film is formed in the pixel portion of the ().

In this case, an n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and patterned in substantially the same shape as the active pattern 124 is formed on the active pattern 124.

In this case, the dummy pattern 114 and the common electrode line and the pad portion line 116p and 117p are removed, and thus the dummy pattern 114 and the common electrode line and the pad portion line 116p and 117p are removed. The first contact hole 140a, the second contact hole (not shown), and the third and fourth contact holes 140c and 140d exposing a portion of the C1 are formed.

Next, as shown in FIGS. 4C and 5C, after the second conductive film and the third conductive film are formed on the entire surface of the array substrate 110 on which the active pattern 124 is formed, a photolithography process (third mask process) is performed. ) And a lift-off process, and a source electrode 122, a drain electrode 123, and a data line, each of which is formed of the third conductive layer, in the pixel portion of the array substrate 110 in one mask process. 117, and the common electrode 108, the pixel electrode 118, the common electrode line 108L and the pixel electrode line 118L made of the second conductive layer are formed in the pixel portion of the array substrate 110. To form.

In this case, the data line 117 intersects the gate line 116 to define a pixel area, and is electrically connected to the dummy pattern 114 under the first through the first contact hole 140a. The electrode line 108L is electrically connected to the first line 108a through the second contact hole 140b.

In addition, the data pad electrode 127p and the gate pad electrode 126p formed of the second conductive layer are formed in the pad portion of the array substrate 110 through the third mask process.

In this case, the data pad electrode 127p and the gate pad electrode 126p are respectively disposed through the third contact hole 140c and the fourth contact hole 140d at the lower portion of the data pad line 117p and the gate pad line ( Electrical connection to 116p).

In this case, a source electrode pattern 122 ′ and a drain electrode pattern 123 ′ formed of the second conductive layer may be disposed below the source electrode 122, the drain electrode 123, and the data line 117. ) And data line pattern 117 'are formed, respectively.

In addition, as described above, a dummy pattern 114 formed of the first conductive layer is formed under the data line 117, specifically, the data line pattern 117 ′, and the dummy pattern 114 is a gate. It is electrically connected to the data line 117 through the first contact hole 140a formed in the insulating film 115a. In this case, the embodiment of the present invention shows a case in which the first contact hole 140a is formed so as to be positioned at the upper and lower ends of the dummy pattern 114, for example, but the present invention is not limited thereto. Two first contact holes 140a may be connected to the dummy pattern 114 at the bottom to self-repair even when disconnection defects occur in which a part of the data line 117 is opened by two etchings. The above can be configured.

The front surface of the array substrate 110 except for the common electrode 108, the pixel electrode 118, the common electrode line 108L, the pixel electrode line 118L, the gate pad electrode 126p, and the data pad electrode 127p. A protective film 115b made of a predetermined insulating material is formed in the film.

As described above, in the transverse electric field type liquid crystal display according to the exemplary embodiment of the present invention, since no active tail is present, there is no signal interference of the data line 117 and the aperture ratio increases by the width of the active tail.

In addition, the transverse electric field type liquid crystal display device according to the embodiment of the present invention does not generate wave noise and provides an effect of manufacturing a high quality liquid crystal display device.

In addition, the horizontal field type liquid crystal display according to the exemplary embodiment of the present invention forms a dummy pattern 114 under the data line 117 so as to be connected to the data line 117 through the first contact hole 140a. It provides an effect of self-repairing the disconnection defect of the data line 117 caused by the etch over time.

Here, the third mask process uses a half-tone mask and a lift-off process so that the source electrode 122, the drain electrode 123, the data line 117, and the common electrode 108 are processed through one mask process. The pixel electrode 118, the common electrode line 108L, the pixel electrode line 118L, the gate pad electrode 126p, the data pad electrode 127p, and the passivation layer 115b may be formed. The third mask process will be described in detail.

7A to 7H are cross-sectional views illustrating a third mask process according to an exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 4D, 4C, and 5C.

As shown in FIG. 7A, the second conductive layer 130 and the third conductive layer 150 are formed on the entire surface of the array substrate 110 on which the active pattern 124 is formed.

In this case, the third conductive layer 150 may be made of a low resistance opaque conductive material such as copper to form a source electrode, a drain electrode, and a data line, and the second conductive layer 130 may diffuse the copper. It may be made of a conductive material such as molybdenum titanium (MoTi) to prevent and improve adhesion characteristics.

Subsequently, as shown in FIG. 7B, after forming the second photoresist layer 270 made of photosensitive material such as photoresist on the entire surface of the array substrate 110, the second half-tone mask according to the embodiment of the present invention ( Light is selectively irradiated to the second photoresist layer 270 through 280.

In this case, the second half-tone mask 280 used in the embodiment of the present invention has a first transmission region I for transmitting all of the irradiated light and a second transmission region II for transmitting only part of the light and blocking part thereof. And a blocking region III for blocking all of the irradiated light, and only the light passing through the second half-tone mask 280 is irradiated to the second photosensitive film 270.

Subsequently, after the second photoresist layer 270 exposed through the second half-tone mask 280 is developed, as shown in FIG. 7C, the blocking region III and the second transmission region II may be formed. The first photoresist pattern 270a to the seventh photoresist pattern 270g having a predetermined thickness remain in the region where all the light is blocked or partially blocked through the second photoresist. The photoresist film is completely removed to expose the surface of the third conductive film 150.

In this case, the first photoresist pattern 270a to the fourth photoresist pattern 270d formed in the blocking region III may include the fifth photoresist pattern 270e to seventh photoresist pattern 270g formed through the second transmission region II. It is thicker than). In addition, the second photoresist film is completely removed in the region where all the light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a resist.

Next, as shown in FIG. 7D, the second conductive film and the third conductive film formed below are selectively formed using the first photosensitive film pattern 270a to the seventh photosensitive film pattern 270g formed as described above as a mask. When removed, the source electrode 122 and the drain electrode 123 formed of the third conductive layer on the gate electrode 121 and electrically connected to the source region and the drain region of the active pattern 124, respectively. Will be formed.

In addition, the pixel region of the array substrate 110 is formed of the third conductive layer and intersects the gate line 116 to define a pixel region, while the dummy pattern 114 is disposed below the first contact hole. ) And a data line 117 electrically connected thereto.

In this case, the common region 108 and the pixel electrode 118 formed of the second conductive layer and alternately arranged to generate a transverse electric field are formed in the pixel region, and the gate line is formed of the second conductive layer. A common electrode line (not shown) and a pixel electrode line 118L which are disposed in substantially the same direction as 116 and connected to one side of the common electrode 108 and the pixel electrode 118 are formed, respectively.

In addition, the pad substrate array substrate 110 may be formed of the second conductive layer and electrically connected to the lower data pad line 117p and the gate pad line 116p through the third contact hole and the fourth contact hole, respectively. The data pad electrode 127p and the gate pad electrode 126p are formed.

In this case, the source electrode 122, the drain electrode 123, and the data line 117 formed of the third conductive layer may be formed of the second conductive layer, and the source electrode 122, the drain electrode 123, and the data may be formed. The source electrode pattern 122 ′, the drain electrode pattern 123 ′, and the data line pattern 117 ′ patterned in substantially the same shape as the line 117 are formed.

In addition, the third electrode may be disposed on the common electrode 108, the pixel electrode 118, the common electrode line, the pixel electrode line 118L, the gate pad electrode 126p, and the data pad electrode 127p. It is made of a conductive film and is patterned in substantially the same form as the common electrode 108, the pixel electrode 118, the common electrode line, the pixel electrode line 118L, the gate pad electrode 126p and the data pad electrode 127p. Common electrode pattern 108 ', pixel electrode pattern 118', common electrode line pattern (not shown), pixel electrode line pattern 118L ', gate pad electrode pattern 126p' and data pad electrode pattern 127p ' ) Is formed.

Subsequently, the n + amorphous silicon thin film pattern is selectively removed by using the third mask process to form the n + amorphous silicon thin film, and the source / drain regions and the source / drain electrodes of the active pattern 124 ( An ohmic contact layer 125n for ohmic contact between 122 and 123 is formed.

Subsequently, when the ashing process of removing a portion of the first photoresist pattern 270a to the seventh photoresist pattern 270g is performed, as illustrated in FIG. 7E, the fifth photoresist layer of the second transmission region II is formed. The pattern to the seventh photosensitive film pattern are completely removed.

In this case, the first photoresist pattern to the fourth photoresist pattern include the eighth photoresist pattern 270a 'to the eleventh photoresist pattern 270d' from which the thickness of the fifth photoresist pattern to the seventh photoresist pattern is removed. Only the predetermined area corresponding to (III) remains.

As shown in FIG. 7F, the passivation layer 115b formed of a predetermined insulating material is formed on the entire surface of the array substrate 110 on which the eighth photoresist pattern 270a ′ to the eleventh photoresist pattern 270d ′ remain. Form.

Subsequently, as shown in FIG. 7G, the eighth photosensitive film pattern to the eleventh photosensitive film pattern are removed through a lift-off process, wherein the eighth photosensitive film pattern of the blocking region III is disposed on the eighth photosensitive film pattern. The deposited protective film is removed together with the eighth to eleventh photoresist patterns.

Next, as shown in FIG. 7H, the third conductive layer is etched to selectively remove the common electrode pattern, the pixel electrode pattern, the common electrode line pattern, the pixel electrode line pattern, the gate pad electrode pattern, and the data pad electrode pattern. Accordingly, the surfaces of the common electrode 108, the pixel electrode 118, the common electrode line, the pixel electrode line 118L, the gate pad electrode 126p and the data pad electrode 127p are exposed to the outside.

The array substrate according to the embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outer side of the image display area. Black matrix to prevent leakage and color filter for red, green and blue color are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

As described above, the embodiment of the present invention describes an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern, for example. However, the present invention is not limited thereto, and the present invention provides a polycrystalline silicon thin film as the active pattern. The same applies to the polysilicon thin film transistors used.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view schematically illustrating a portion of an array substrate of a general transverse electric field type liquid crystal display device;

3 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

4A to 4C are cross-sectional views sequentially showing manufacturing processes taken along lines IIIa-IIIa ', IIIb-IIIb and IIIc-IIIc of the array substrate shown in FIG.

5A to 5C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

6A through 6F are cross-sectional views illustrating a second mask process according to an embodiment of the present invention in the array substrate shown in FIGS. 4B and 5B.

7A to 7H are cross-sectional views illustrating a third mask process according to an embodiment of the present invention in the array substrate shown in FIGS. 4C and 5C.

DESCRIPTION OF REFERENCE NUMERALS

108: common electrode 108l: common electrode line

108L: common line 110: array substrate

114: dummy pattern 116: gate line

117 data line 118 pixel electrode

118l: pixel electrode line 121: gate electrode

122 source electrode 123 drain electrode

Claims (12)

Providing a first substrate divided into a pixel portion and a pad portion; Forming a gate electrode, a gate line, and a dummy pattern formed of a first conductive layer on the pixel portion of the first substrate through a first mask process; Forming a gate insulating film on the first substrate; Forming an active pattern made of an amorphous silicon thin film on the gate electrode through a second mask process; Selectively patterning the gate insulating layer using the second mask process to form a first contact hole exposing a portion of the dummy pattern; Forming a source / drain electrode on the gate electrode through a third mask process, the source / drain electrode electrically connected to a source / drain region of the active pattern; The third conductive layer is formed on the dummy pattern by using the third mask process, and defines a pixel area intersecting the gate line, and electrically connects the dummy pattern under the first contact hole. Forming a data line to connect; Forming a common electrode and a pixel electrode formed of a second conductive layer in the pixel region by using the third mask process and alternately arranged to generate a transverse electric field; And A method of manufacturing a transverse electric field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate. The method of claim 1, further comprising forming a data pad line and a gate pad line formed of the first conductive layer on a pad portion of the first substrate. . The method of claim 2, further comprising: forming a first line formed of the first conductive layer at an edge of the pixel region of the first substrate, and forming a common line formed of the first conductive layer at a lower end of the pixel region. Method of manufacturing a transverse electric field type liquid crystal display device further comprising. The third contact hole of claim 3, further comprising: forming a second contact hole exposing a portion of the first line using the second mask process, and exposing a portion of the data pad line and the gate pad line, respectively; A method of manufacturing a transverse electric field type liquid crystal display device further comprising the step of forming a fourth contact hole. The method of claim 1, wherein the first contact hole is formed so as to be positioned one by one on the top and the bottom of the dummy pattern. The semiconductor device of claim 4, wherein the pad portion is formed of the second conductive layer using the third mask process, and is electrically connected to the data pad line and the gate pad line through the third contact hole and the fourth contact hole, respectively. And forming a data pad electrode and a gate pad electrode connected to each other. The method of claim 4, wherein the third mask process Forming a second conductive film and a third conductive film on an entire surface of the first substrate on which the active pattern is formed; Forming first to fourth photoresist patterns of a first thickness and a fourth photoresist pattern and a fifth to seventh photoresist patterns of a second thickness on the first substrate; By selectively removing the second conductive film and the third conductive film formed under the first photosensitive film pattern to the seventh photosensitive film pattern as a mask, the third conductive film is formed on the gate electrode and the source / Forming a source / drain electrode electrically connected to the drain region, and forming a data line crossing the gate line to define a pixel region; The second conductive film and the third conductive film formed below the first photosensitive film pattern and the seventh photosensitive film pattern are selectively removed to form the second conductive film in the pixel area, and are alternately disposed. Forming a common electrode and a pixel electrode for generating a common electrode; The second conductive film and the third conductive film formed under the first photosensitive film pattern to the seventh photosensitive film pattern are selectively removed, and the pad portion is formed of the second conductive film, wherein the third contact hole and Forming a data pad electrode and a gate pad electrode electrically connected to the data pad line and the gate pad line through a fourth contact hole, respectively; By removing the fifth photoresist pattern to the seventh photoresist pattern through an ashing process, a portion of the thickness of the first photoresist pattern to the fourth photoresist pattern is removed to form the eighth photoresist pattern to the eleventh photoresist pattern having a third thickness. step; Forming a protective film made of a predetermined insulating material on an entire surface of the first substrate on which the eighth to eleventh photosensitive film patterns remain; Removing the protective film deposited on the eighth photosensitive film pattern and the eleventh photosensitive film pattern together with the eighth photosensitive film pattern through the lift-off process; And The common conductive pattern, the pixel electrode pattern, and the data pad electrode pattern formed on the common electrode, the pixel electrode, the data pad electrode, and the gate pad electrode by etching the third conductive layer are removed to remove the common electrode pattern. Exposing the surfaces of the electrodes, the pixel electrodes, the data pad electrodes, and the gate pad electrodes, wherein the passivation layer remains on the first substrate corresponding to a region other than the eighth to eleventh photoresist patterns. Method of manufacturing a transverse electric field liquid crystal display device. The source electrode of claim 1, wherein the source electrode, the drain electrode, and the data line formed under the data line are formed of the second conductive layer, respectively, and are patterned in the same form as the source electrode, the drain electrode, and the data line. A method of manufacturing a transverse electric field type liquid crystal display device further comprising the step of forming a pattern, a drain electrode pattern, and a data line pattern. The conductive material of claim 1, wherein the third conductive film is made of a low resistance opaque conductive material such as copper, and the second conductive film is a conductive material such as molybdenum titanium (MoTi) to prevent diffusion of the copper and improve adhesion characteristics. A method of manufacturing a transverse electric field type liquid crystal display device, characterized in that consisting of. The data line of claim 1, wherein the short circuit of the data line is electrically connected to the dummy pattern at the lower portion of the data line through the first contact hole even when a disconnection failure occurs. A method of manufacturing a transverse electric field type liquid crystal display device, wherein a defect is self repaired. A first substrate divided into a pixel portion and a pad portion; A gate electrode, a gate line, a first line, and a dummy pattern formed on the pixel portion of the first substrate and formed of a first conductive film; A data pad line and a gate pad line formed on a pad portion of the first substrate and formed of the first conductive layer; A gate insulating film formed on the first substrate; An active pattern formed on the gate electrode and formed of an amorphous silicon thin film; A first contact hole removing a portion of the gate insulating layer to expose a portion of the dummy pattern; A second contact hole exposing a portion of the first line by removing a portion of the gate insulating layer; A third contact hole and a fourth contact hole which remove portions of the gate insulating layer to expose portions of the data pad line and the gate pad line, respectively; A source / drain electrode formed of a third conductive layer on the gate electrode and electrically connected to a source / drain region of the active pattern; A data line formed of the third conductive layer on the dummy pattern and defining a pixel area crossing the gate line, and electrically connected to a dummy pattern under the first contact hole; A common electrode and a pixel electrode formed of a second conductive film in the pixel region and alternately arranged to generate a transverse electric field; A pixel electrode line formed of the second conductive layer and connected to one side of the pixel electrode to electrically connect the drain electrode and the pixel electrode; A common electrode line formed of the second conductive layer and electrically connected to the first line through the second contact hole, and connected to one side of the common electrode; A data pad electrode formed of the second conductive layer and electrically connected to the data pad line through the third contact hole, and a gate pad electrode electrically connected to the gate pad line through the fourth contact hole; A passivation layer formed on the entire surface of the first substrate excluding the common electrode, the pixel electrode, the common electrode line, the pixel electrode line, the gate pad electrode, and the data pad electrode; And A transverse electric field type liquid crystal display device comprising a second substrate bonded to and opposed to the first substrate. The source electrode pattern of claim 11, wherein the source electrode pattern is formed of the second conductive layer under the source electrode, the drain electrode, and the data line, and is patterned in the same form as the source electrode, the drain electrode, and the data line. And a drain electrode pattern and a data line pattern.

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