KR20090054277A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The liquid crystal display of the present invention and a method of manufacturing the same are designed to prevent deterioration in image quality due to parasitic capacitance between the gate line and the data line by improving the shape of the source electrode to include the data line. Forming a gate line including the gate electrode; Forming a first insulating film on the first substrate; Forming an active pattern, a “U” shaped source electrode, and a drain electrode on the gate electrode; Forming a data line on the first substrate to define a pixel region crossing the gate line, wherein a portion of the data line forms a portion of the source electrode; Forming a second insulating film on the first substrate; Forming a common electrode and a pixel electrode which are alternately disposed in the pixel region to generate a transverse electric field, and forming repair lines on both sides of the data line connected to the source electrode; And bonding the first substrate and the second substrate to each other.

The liquid crystal display of the present invention configured as described above is characterized in that a repair line for connecting data lines between pixels is formed on the data line through which the gate line passes, thereby preventing disconnection of the data line during repair. .

 Gate line, data line, source electrode, repair, repair line

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device and a method for manufacturing the liquid crystal display device which can perform a repair process without disconnection of the data line while reducing parasitic capacitance between the gate line and the data line. It is about.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules aligned horizontally with the substrate are aligned in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

In addition, since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. It is required.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. It has the disadvantage of dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

In general, the liquid crystal display is driven at a driving frequency of 60 Hz, but in recent years, the driving frequency of the liquid crystal display has increased to 90 Hz, 120 Hz, 150 Hz, and the like. However, in general liquid crystal display devices, as the driving frequency increases, the time for charging the data voltage to the storage capacitor is shortened, and as the size of the screen increases, the data voltage is applied to the source electrodes of the pixels formed in the first gate line. Due to a time difference between the time point and the time point at which the data voltage is applied to the source electrodes of the pixels formed at the last gate line, the data voltage cannot be sufficiently charged in the storage capacitor. In addition, this is affected by the parasitic capacitance generated between the gate line and the electrodes of the thin film transistor, which makes it difficult to drive the liquid crystal display at a high driving frequency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display and a method of manufacturing the same, which reduce parasitic capacitances between gate lines and data lines.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can repair a short circuit defect of a thin film transistor without disconnecting a data line.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which produce an array substrate capable of a repair process using four mask processes.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display of the present invention includes a gate line including a gate electrode formed on the first substrate; A first insulating film formed on the first substrate; An active pattern formed on the gate electrode, a source electrode and a drain electrode having a 'U' shape; A data line formed on the first substrate such that a portion thereof forms a part of the source electrode and defining a pixel region intersecting the gate line; A second insulating film formed on the first substrate; A common electrode and a pixel electrode disposed alternately in the pixel region to generate a transverse electric field; A repair line formed in an isolated structure on both sides of the data line connected to the source electrode; And a second substrate bonded to the first substrate.

In addition, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of forming a gate line including a gate electrode on the first substrate; Forming a first insulating film on the first substrate; Forming an active pattern, a “U” shaped source electrode, and a drain electrode on the gate electrode; Forming a data line on the first substrate to define a pixel region crossing the gate line, wherein a portion of the data line forms a portion of the source electrode; Forming a second insulating film on the first substrate; Forming a common electrode and a pixel electrode which are alternately disposed in the pixel region to generate a transverse electric field, and forming repair lines on both sides of the data line connected to the source electrode; And bonding the first substrate and the second substrate to each other.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention provide an effect of reducing the manufacturing process and cost by reducing the number of masks used for manufacturing the thin film transistor.

In addition, the liquid crystal display and the method of manufacturing the same according to the present invention can improve the structure of the thin film transistor to reduce the parasitic capacitance between the gate line and the data line to drive the liquid crystal display at a high driving frequency such as 120 Hz or 150 Hz. To provide an effect of improving image quality.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention have the effect of improving the yield of about 2 to 3% by preventing the disconnection of the data line in repairing short circuit defects of the thin film transistor in the above structure. to provide.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view schematically illustrating a portion of an array substrate of an in plane switching (IPS) liquid crystal display device according to a first embodiment of the present invention, and for convenience of description, a gate pad part, a data pad part, and a pixel. One pixel including a negative thin film transistor is shown.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

In this case, the present embodiment has been described using a transverse electric field type liquid crystal display as an example, but the present invention is not limited thereto, and the present invention may be applied to a twisted nematic liquid crystal display.

As described above, the twisted nematic liquid crystal display has a disadvantage that the viewing angle is narrow to about 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules aligned horizontally with the substrate are aligned in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

Accordingly, a transverse electric field type liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve the viewing angle to 170 degrees or more has been developed, and the present invention illustrates the transverse electric field type liquid crystal display device as an example.

As shown in the drawing, in the array substrate 110 according to the first embodiment of the present invention, a gate line 116 and a data line 117 are arranged vertically and horizontally on the array substrate 110 to define a pixel area. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117, and a common electrode 108 for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel region. And the pixel electrode 118 are alternately formed.

The thin film transistor is connected to the pixel electrode 118 through a gate electrode 121 constituting a part of the gate line 116, a source electrode 122 connected to the data line 117, and a pixel electrode line 118l. The drain electrode 123 is electrically connected. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. In this case, although the shape of the source electrode 122 is "U" shaped and the channel is "U" shaped, for example, a thin film transistor is illustrated, but the present invention is not limited thereto. Applicable regardless of the channel type of the transistor.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to form a first insulating layer (not shown). The pixel electrode line 118l and the pixel electrode 118 are electrically connected to each other through the contact hole 140a.

As described above, a plurality of common electrodes 108 and pixel electrodes 118 for generating a transverse electric field are alternately arranged in the pixel region.

In this case, a common line 108l is formed at a lower end of the pixel area substantially parallel to the gate line 116, and a pair of first connected to the common line 108l is formed at left and right edges of the pixel area. Line 108a is formed.

In this case, the pair of outermost common electrodes 108 adjacent to the data line 117 among the plurality of common electrodes 108 overlap with a part of the pair of first lines 108a, respectively, The plurality of common electrodes 108 are connected to each other by a second line 108b at an upper end of which the one side is disposed substantially parallel to the gate line 116. In addition, the second line 108b is electrically connected to the first line 108a through the second contact hole 140b formed in the second insulating layer, thereby providing a common voltage through the common line 108l. It is applied to and delivered to the plurality of common electrodes 108.

The first line 108a is made of the same opaque conductive material as the common line 108l, and the second line 108b and the pixel electrode line 118l are the common electrode 108 and the pixel electrode 118. It may be made of the same transparent conductive material.

In this case, a portion of the pixel electrode line 118l overlaps a portion of the common line 108l below the first insulating layer (not shown) and the second insulating layer, so that the storage capacitor Cst may overlap. To form. The storage capacitor Cst plays a role of maintaining a constant voltage applied to the liquid crystal capacitor until the next signal. In addition to maintaining the signal, the storage capacitor has effects such as stabilization of gray scale display and reduction of flicker and afterimage.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140c and 140d represent a third contact hole and a fourth contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the third contact hole 140c. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the fourth contact hole 140d.

In this case, as shown in FIG. 2, when the common electrode 108, the pixel electrode 118, and the data line 117 have a bent structure, the liquid crystal molecules are arranged in two directions. By forming a two-domain, the viewing angle is further improved compared to the mono-domain. However, the present invention is not limited to the two-domain transverse electric field liquid crystal display device, and the present invention can be applied to the transverse electric field liquid crystal display device having a multi-domain structure of two or more domains. For reference, an IPS structure for forming a multi-domain of two or more domains is called an S-IPS (Super-IPS) structure.

In addition, when the common electrode 108, the pixel electrode 118, and the data line 117 are formed in a bent structure to form a multi-domain structure in which the driving directions of the liquid crystal molecules are symmetrical, birefringence of the liquid crystal is performed. The color shift phenomenon can be minimized by canceling the extraordinary light due to the?

Here, as the screen size of the liquid crystal display increases, parasitic capacitance generated between the gate line including the gate electrode and the electrodes of the thin film transistor, that is, the source electrode and the drain electrode or the data line, is important for the image quality of the liquid crystal display. In particular, efforts are being made to reduce the parasitic capacitance in driving a liquid crystal display using high-speed driving frequencies such as 90 Hz, 120 Hz, 150 Hz, and the like.

In this case, in the case of the first embodiment of the present invention, the area where the gate line and the data line overlap is relatively large, so that parasitic capacitance occurring between them becomes an issue, and thus data overlapping the gate line is caused. The transverse electric field type liquid crystal display device according to the second embodiment of the present invention for reducing the parasitic capacitance and reducing the resistance of the gate line by improving the structure of the thin film transistor so that a part of the line is included in the source electrode will be described in detail with reference to the drawings. do.

FIG. 3 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a second embodiment of the present invention, except that the structure of the thin film transistor is improved, and is the same as the array substrate of the first embodiment. Consists of elements.

As shown in the figure, in the array substrate 210 according to the second embodiment of the present invention, a gate line 216 and a data line 217 arranged vertically and horizontally on the array substrate 210 to define a pixel area are provided. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 216 and the data line 217, and a common electrode 208 for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel area. ) And the pixel electrode 218 are alternately formed.

The thin film transistor is connected to the pixel electrode 218 through a gate electrode 221 constituting a part of the gate line 216, a source electrode 222 connected to the data line 217, and a pixel electrode line 218l. It consists of the drain electrode 223 electrically connected. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

In this case, the source electrode 222 according to the second embodiment of the present invention is improved to include a part of the data line 217 overlapping with the gate line 216, the transverse field type liquid crystal of the first embodiment Compared to the display device, parasitic capacitance generated between the gate line 216 and the data line 217 can be reduced. That is, the data line 217 passing over the gate line 216 is directed to the next adjacent pixel through a portion of the source electrode 222 of the corresponding pixel. As a portion of the 222 constitutes a part of the data line 217, an area where the gate line 216 and the data line 217 overlap with each other decreases, thereby reducing parasitic capacitance occurring therebetween.

In this case, a part of the drain electrode 223 extends toward the pixel region and is electrically connected to the pixel electrode line 218l and the pixel electrode 218 through a first contact hole 240a formed in a second insulating film (not shown). You will be connected to

As in the first embodiment, a plurality of common electrodes 208 and pixel electrodes 218 for generating a transverse electric field are alternately arranged in the pixel region.

In this case, a common line 208l is formed at a lower end of the pixel area substantially parallel to the gate line 216, and a pair of first connected to the common line 208l is formed at left and right edges of the pixel area. Line 208a is formed.

In this case, the pair of outermost common electrodes 208 adjacent to the data line 217 among the plurality of common electrodes 208 overlap with a portion of the pair of first lines 208a, respectively, The plurality of common electrodes 208 are connected to each other by a second line 208b on the top side of which one side is disposed substantially parallel to the gate line 216. In addition, the second line 208b is electrically connected to the first line 208a through the second contact hole 240b formed in the second insulating layer, and thus the common line is formed through the common line 208l. It is applied to and delivered to the plurality of common electrodes 208.

The first line 208a is made of the same opaque conductive material as the common line 208l, and the second line 208b and the pixel electrode line 218l are the common electrode 208 and the pixel electrode 218. It may be made of the same transparent conductive material.

In this case, a portion of the pixel electrode line 218l is overlapped with a portion of the common line 208l under the first insulating layer (not shown) and the second insulating layer to form a storage capacitor Cst.

The gate pad electrode 226p and the data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad The line 217p receives a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

For reference, reference numerals 240c and 240d denote third and fourth contact holes, respectively, wherein the data pad electrode 227p is electrically connected to the data pad line 217p through the third contact hole 240c. The gate pad electrode 226p is electrically connected to the gate pad line 216p through the fourth contact hole 240d.

As described above, in the second exemplary embodiment of the present invention, as the data line 217 forms a part of the source electrode 222, the area where the gate line 216 overlaps the data line 217 is the first embodiment. Compared to the case of the example, the relative parasitic capacitance between them is reduced. As a result, the liquid crystal display device can be driven using high-speed driving frequencies such as 90 Hz, 120 Hz, and 150 Hz, thereby improving image quality.

In this case, short-circuit defects may occur in the thin film transistor due to various factors such as a short between the source electrode 222 and the drain electrode 223 or a short circuit between the gate electrode 221 and the source / drain electrodes 222 and 223. In order to repair this, as shown in the figure, both sides of the data line 217 are cut by using a laser. In this case, as the data line 217 to the adjacent next pixel is disconnected, a phenomenon in which the data signal is not transmitted to the next pixels occurs.

For reference, reference numeral L denotes a cutting line for cutting the data line 217 by using a laser.

Accordingly, when forming the common electrode and the pixel electrode, a repair line having a floating structure is formed on both data lines between the pixels using a transparent conductive film, and then, when the repair process is necessary, the repair line is cut using the repair line. By connecting data lines, disconnection of the data lines can be prevented, which will be described in detail with the transverse electric field type liquid crystal display device according to the third embodiment of the present invention.

FIG. 4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display according to a third exemplary embodiment of the present invention, except for repair lines formed on both sides of the data line between pixels. It consists of the same components as the array substrate.

As shown in the figure, in the array substrate 310 according to the third embodiment of the present invention, a gate line 316 and a data line 317 are arranged vertically and horizontally on the array substrate 310 to define a pixel region. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 316 and the data line 317, and a common electrode 308 for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel area. ) And the pixel electrode 318 are alternately formed.

The thin film transistor is connected to the pixel electrode 318 through a gate electrode 321 constituting a part of the gate line 316, a source electrode 322 connected to the data line 317, and a pixel electrode line 318l. The drain electrode 323 is electrically connected. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 322 and the drain electrode 323 by a gate voltage supplied to the gate electrode 321.

In this case, according to the third embodiment of the present invention, a portion of the data line 317 may be removed to reduce the area of the data line 317 overlapping with the gate line 316 as in the case of the second embodiment. By improving the shape of the source electrode 322 to include, the parasitic capacitance generated between the gate line 316 and the data line 317 can be reduced compared to the transverse electric field type liquid crystal display device of the first embodiment.

In this case, a part of the drain electrode 323 extends toward the pixel region and is electrically connected to the pixel electrode line 318l and the pixel electrode 318 through a first contact hole 340a formed in a second insulating film (not shown). You will be connected to

In addition, a common line 308l is formed at a lower end of the pixel area substantially parallel to the gate line 316, and a pair of first connected to the common line 308l is formed at left and right edges of the pixel area. Line 308a is formed.

In this case, the pair of outermost common electrodes 308 adjacent to the data line 317 among the plurality of common electrodes 308 overlap with a portion of the pair of first lines 308a, respectively, The plurality of common electrodes 308 are connected to each other by a second line 308b at an upper end of which the one side is disposed substantially parallel to the gate line 316. In addition, the second line 308b is electrically connected to the first line 308a through a second contact hole 340b formed in the second insulating layer, thereby providing a common voltage through the common line 308l. It is applied to and delivered to the plurality of common electrodes 308.

The first line 308a is made of the same opaque conductive material as the common line 308l, and the second line 308b and the pixel electrode line 318l are the common electrode 308 and the pixel electrode 318. It may be made of the same transparent conductive material.

In this case, a portion of the pixel electrode line 318l overlaps a portion of the common line 308l thereunder with a first insulating layer (not shown) and a second insulating layer interposed therebetween to form a storage capacitor Cst. do.

A gate pad electrode 326p and a data pad electrode 327p electrically connected to the gate line 316 and the data line 317 are formed in the edge region of the array substrate 310 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 316 and the data line 317, respectively.

That is, the gate line 316 and the data line 317 extend toward the driving circuit part and are connected to the corresponding gate pad line 316p and the data pad line 317p, respectively, and the gate pad line 316p and the data pad, respectively. The line 317p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 326p and the data pad electrode 327p electrically connected to the gate pad line 316p and the data pad line 317p, respectively. You will be authorized.

For reference, reference numerals 340c and 340d indicate a third contact hole and a fourth contact hole, respectively, wherein the data pad electrode 327p is electrically connected to the data pad line 317p through the third contact hole 340c. The gate pad electrode 326p is electrically connected to the gate pad line 316p through the fourth contact hole 240d.

As described above, in the third exemplary embodiment of the present invention, as the data line 317 forms part of the source electrode 322, the area where the gate line 316 overlaps with the data line 317 is the first embodiment. Compared to the case of the example, the relative parasitic capacitance between them is reduced. As a result, the liquid crystal display device can be driven using high-speed driving frequencies such as 90 Hz, 120 Hz, and 150 Hz, thereby improving image quality.

In this case, when a short circuit defect occurs in the thin film transistor as described above, both of the data lines 317 are cut by using a laser. In this case, in order to prevent a phenomenon in which the data line 317 to the adjacent next pixel is disconnected and the data signal cannot be transmitted to the next pixels, in the case of the third embodiment of the present invention, both side data between the pixels are used. A repair line 390 having an isolated structure is formed on the line 317.

In this case, the repair line 390 is simultaneously formed of a transparent conductive film when the common electrode 308 and the pixel electrode 318 are formed. When the repair process is necessary, the repair line 390 is cut using the repair line 390. By connecting the data lines 317, disconnection of the data lines 317 can be prevented.

For reference, reference numeral L ′ exemplarily shows a cutting line for cutting the data line 317 using a laser.

Herein, the transverse electric field type liquid crystal display device according to the first to third embodiments of the present invention includes a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask). The active substrate, the source / drain electrodes, and the data lines are formed by using a single mask process, thereby manufacturing an array substrate using a total of four mask processes.

In addition, the transverse electric field type liquid crystal display device according to the third exemplary embodiment of the present invention forms a repair line using the same mask process when forming a common electrode and a pixel electrode, thereby enabling a repair process without adding a mask process. An array substrate is manufactured, which will be described in detail through the following method of manufacturing a transverse electric field type liquid crystal display device.

5A through 5D are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate illustrated in FIG. 4, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

6A to 6D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

As shown in FIGS. 5A and 6A, the gate electrode 321, the gate line 316, the first line 308a and the common line may be formed in the pixel portion of the array substrate 310 made of a transparent insulating material such as glass. 308l is formed, and a gate pad line 316p is formed in the gate pad portion of the array substrate 310.

In this case, the common line 308l is formed below the pixel area in a direction substantially parallel to the gate line 316, and the first line 308a is formed on the left and right sides of the pixel area to form the common line. Is connected to line 308l.

In this case, the gate electrode 321, the gate line 316, the first line 308a, the common line 308l, and the gate pad line 316p are deposited on the entire surface of the array substrate 310 after the first conductive layer is deposited. It is formed by selectively patterning through a photolithography process (first mask process).

Here, the first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and Low resistance opaque conductive materials such as molybdenum alloys can be used. In addition, the first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as illustrated in FIGS. 5B and 6B, an array substrate on which the gate electrode 321, the gate line 316, the first line 308a, the common line 308l, and the gate pad line 316p are formed. The gate insulating layer 315a, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are formed on the entire surface of the array 310, and then selectively removed through a photolithography process (second mask process). An active pattern 324 made of the amorphous silicon thin film is formed in the pixel portion, and the source / drain electrodes 322 and 323 made of the second conductive layer and electrically connected to the source / drain regions of the active pattern 324. ).

In addition, a data line 317 made of the second conductive layer is formed in the data line region of the array substrate 310 through the second mask process, and the second data pad portion of the array substrate 310 is formed. A data pad line 317p made of a conductive film is formed.

In this case, an ohmic contact layer 325n formed of the n + amorphous silicon thin film and patterned in the same form as the source / drain electrodes 322 and 323 is formed on the active pattern 324.

In addition, a bottom portion of the data line 317 and the data pad line 317p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 317 and the data pad line 317p. The first amorphous silicon thin film pattern 320 ′, the first n + amorphous silicon thin film pattern 325 ′, the second amorphous silicon thin film pattern 320 ″ and the third n + amorphous silicon thin film pattern 325 ′ ″ are formed.

Here, the active pattern 324, the source / drain electrodes 322 and 323, and the data line 317 according to the third embodiment of the present invention are subjected to one mask process using a half-tone mask (second mask process). At the same time, the second mask process will be described in detail with reference to the accompanying drawings.

7A to 7F are cross-sectional views illustrating a second mask process according to a third exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 5B and 6B.

As shown in FIG. 7A, a gate is formed on an entire surface of the array substrate 310 on which the gate electrode 321, the gate line 316, the first line 308a, the common line 308l, and the gate pad line 316p are formed. An insulating film 315a, an amorphous silicon thin film 320, an n + amorphous silicon thin film 325, and a second conductive film 330 are formed.

In this case, the second conductive layer 330 may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line.

As shown in FIG. 7B, after forming the photoresist film 370 made of a photoresist such as photoresist on the entire surface of the array substrate 310, the half-tone mask 380 according to the third embodiment of the present invention. The light is selectively irradiated to the photosensitive film 370 through).

In this case, the half-tone mask 380 includes a first transmission region I through which all of the irradiated light is transmitted, a second transmission region II through which only a part of the light is transmitted and a part of the light, and a block to block all of the irradiated light. An area III is provided, and only light transmitted through the half-tone mask 380 is irradiated to the photosensitive film 370.

Subsequently, after the photoresist 370 exposed through the half-tone mask 380 is developed, light passes through the blocking region III and the second transmission region II, as shown in FIG. 7C. The first photoresist pattern 370a to the fifth photoresist pattern 370e having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the second conductive layer 330 is exposed.

In this case, the first photoresist pattern 370a to the fourth photoresist pattern 370d formed in the blocking region III are formed thicker than the fifth photoresist pattern 370e formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. May be used.

Next, as shown in FIG. 7D, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second formed on the lower portion of the first photosensitive film pattern 370a to the fifth photosensitive film pattern 370e formed as described above are used as a mask. When the conductive layer is selectively removed, an active pattern 324 made of the amorphous silicon thin film is formed in the pixel portion of the array substrate 310, and the second conductive layer is formed in the data line region of the array substrate 310. The data line 317 is formed.

In addition, a data pad line 317p formed of the second conductive layer is formed on the data pad portion of the array substrate 310.

In this case, the second n + amorphous silicon thin film pattern 325 ′ and the second conductive layer are formed on the active pattern 324, respectively, and are patterned in the same form as the active pattern 324. The conductive film pattern 330 'is formed.

In addition, a bottom portion of the data line 317 and the data pad line 317p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 317 and the data pad line 317p. The first amorphous silicon thin film pattern 320 ′, the first n + amorphous silicon thin film pattern 325 ′, the second amorphous silicon thin film pattern 320 ″ and the third n + amorphous silicon thin film pattern 325 ′ ″ are formed.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 370a to the fifth photoresist pattern 370e is performed, as shown in FIG. 7E, the second transmission region II may be formed. The fifth photosensitive film pattern is completely removed.

In this case, the first photoresist pattern to the fourth photoresist pattern correspond to the blocking region III by the sixth photoresist pattern 370a 'through the ninth photoresist pattern 370d' whose thickness is equal to that of the fifth photoresist pattern. Only the source electrode region and the drain electrode region and the upper portion of the data line 317 and the data pad line 317p remain.

Subsequently, as shown in FIG. 7F, a portion of the second n + amorphous silicon thin film pattern and the second conductive film pattern using the remaining sixth photoresist pattern 370a ′ to ninth photoresist pattern 370d ′ as a mask. The source electrode 322 and the drain electrode 323 formed of the second conductive layer are formed in the pixel portion of the array substrate 310 by removing the?

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active pattern 324 and ohmic-contacting between the source / drain region of the active pattern 324 and the source / drain electrodes 322 and 323. 325n is formed.

As described above, the third embodiment of the present invention uses the half-tone mask to form the active pattern 324, the source / drain electrodes 322 and 323, and the data line 317 through one mask process. do.

Subsequently, as illustrated in FIGS. 5C and 6C, the second insulating layer 315b is disposed on the entire surface of the array substrate 310 on which the active patterns 324, the source / drain electrodes 322 and 323, and the data lines 317 are formed. To form.

The first contact hole 340a exposing a part of the drain electrode 323 by selectively removing a part of the second insulating layer 315b using a photolithography process (a third mask process) and the first contact hole 340a. A second contact hole 340b exposing a part of the first line 308a is formed.

The third contact hole exposing a portion of the data pad line 317p and the gate pad line 316p may be selectively removed by selectively removing a portion of the second insulating layer 315b using the third mask process. 340c and a fourth contact hole 340d are formed.

Next, as shown in FIGS. 5D and 6D, a third conductive layer formed of a transparent conductive material is formed on the entire surface of the array substrate 310 on which the first contact holes 340a to 340d are formed. The pixel electrode line 318l electrically connected to the drain electrode 323 through the first contact hole 340a by selectively removing the third conductive layer using a photolithography process (a fourth mask process). To form.

In this case, by selectively removing the third conductive layer using the fourth mask process, a plurality of common electrodes 308 and pixel electrodes 318 are alternately disposed in the pixel region to generate a transverse electric field. A data pad electrode 327p and a gate pad electrode 326p electrically connected to the data pad line 317p and the gate pad line 316p through the third contact hole 340c and the fourth contact hole 340d, respectively. Will form.

In addition, the third conductive layer may be selectively removed using the fourth mask process to form a repair line 390 having an isolation structure formed on both data lines 317 between the pixels through which the gate line 316 passes. The second line 308b is formed on the pixel area so as to be substantially parallel to the gate line 316.

At this time, the outermost common electrode 308 adjacent to the data line 317 among the plurality of common electrodes 308 overlaps with a portion of the first line 308a below the plurality of common electrodes 308. One side of 308 is connected to each other by the second line 308b. In addition, the second line 308b is electrically connected to the first line 308a through a second contact hole 340b formed in the second insulating layer, so that the common voltage is formed through the common line 308l. Received is delivered to the plurality of common electrodes 308.

In this case, a portion of the pixel electrode line 318l overlaps a portion of the common line 308l therebetween with the first insulating layer 315a and the second insulating layer 315b interposed therebetween to form a storage capacitor Cst. do.

The third conductive layer is formed of indium tin oxide to form the common electrode 308, the second line 308b, the pixel electrode 318, the pixel electrode line 318l, and the repair line 390. ITO) or Indium Zinc Oxide (IZO), and a transparent conductive material having excellent transmittance.

The array substrates of the first to third embodiments of the present invention configured as described above are bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor and the gate are attached to the color filter substrate. A black matrix is formed to prevent light leakage into lines and data lines, and a color filter is formed to realize colors of red, green, and blue.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

As described above, the first to third embodiments of the present invention describe an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern as an example, but the present invention is not limited thereto. It is also applied to polycrystalline silicon thin film transistors using polycrystalline silicon thin films as active patterns.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Hereinafter, in the transverse electric field type liquid crystal display device according to the third embodiment of the present invention configured as described above, a laser repair process for repairing a short circuit defect in some thin film transistors will be described in detail with reference to the accompanying drawings.

FIG. 8 is a plan view schematically illustrating a state in which a short circuit failure occurring in a part of a thin film transistor is repaired in an array substrate according to a third exemplary embodiment of the present invention illustrated in FIG. 4.

9A to 9C are cross-sectional views schematically illustrating a process of repairing a short circuit failure occurring in a part of a thin film transistor in an array substrate according to a third exemplary embodiment of the present invention.

As shown in FIG. 9A, a part of the source electrode 322 and the drain electrode 323 may be shorted or the gate electrode 321 and the source / As in the case where the drain electrodes 322 and 323 are shorted, a short circuit failure may occur in a part of the thin film transistor.

As described above, a pixel in which a short circuit defect occurs in the pixel portion causes a bright spot defect that is always turned on in a normally black mode. As a result, a darkening process is performed to repair the defective pixel. As shown in FIG. 9B, a data signal is applied to the pixel electrode 318 of the pixel in which the short circuit failure occurs. The predetermined region of the data line 317 is cut using a laser.

That is, by cutting both sides of the data line 317 connected to the source electrode 322 using a laser along the cut line L ', the signal is not always applied to the pixel electrode 318. The pixel electrode 318 is darkened.

At this time, the data line 317 in which the cutting line L 'is formed is disconnected from the next adjacent pixels as both sides thereof are cut. To prevent this, the cutting line L is prevented when the laser repair is performed. ') Is formed to remove portions of the second insulating layer 315b on both sides of the disconnected data line 317 to form an exposure hole L ″ exposing a portion of the data line 317.

Thereafter, as illustrated in FIG. 9C, a repair pattern 395 is electrically connected between the data line 317 and the repair line 390 through the exposure hole L ″ using a conductive film such as tungsten. To form.

As described above, when the common electrode 308 and the pixel electrode 318 are formed, a repair line 390 having a structure insulated with a transparent conductive film is formed on both data lines 317 between the pixels, and then repair is required. A short-circuit defect of a thin film transistor is formed by forming a cutting line L 'on a data line 317 of a corresponding pixel and connecting the disconnected data line 317 using the repair line 390 and the repair pattern 395. Yield improvement of 2 ~ 3% can be expected.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention;

3 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a second exemplary embodiment of the present invention;

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a third exemplary embodiment of the present invention.

5A to 5D are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate shown in FIG.

6A to 6D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A to 7F are cross-sectional views illustrating the second mask process according to the third embodiment of the present invention in the array substrate shown in FIGS. 5B and 6B.

8 is a plan view schematically illustrating a state in which a short circuit failure occurring in a part of a thin film transistor is repaired in an array substrate according to a third exemplary embodiment of the present invention shown in FIG. 4.

9A to 9C are cross-sectional views schematically illustrating a process of repairing a short circuit defect occurring in a portion of a thin film transistor in an array substrate according to a third exemplary embodiment of the present invention.

** Explanation of symbols for main parts of drawings **

108,208,308: Common electrode 108l, 208l, 308l: Common line

110,210,310: array substrate 116,216,316: gate line

117,217,317 Data lines 118,218,318 Pixel electrodes

118l, 218l, 318l: pixel electrode lines 121,221,321: gate electrode

122,222,322 Source electrodes 123,223,323 Drain electrodes

124,224,324 Active pattern 390 Repair line

Claims (18)

Forming a gate line including a gate electrode on the first substrate; Forming a first insulating film on the first substrate; Forming an active pattern, a “U” shaped source electrode, and a drain electrode on the gate electrode; Forming a data line on the first substrate to define a pixel region crossing the gate line, wherein a portion of the data line forms a portion of the source electrode; Forming a second insulating film on the first substrate; Forming a common electrode and a pixel electrode which are alternately disposed in the pixel region to generate a transverse electric field, and forming repair lines on both sides of the data line connected to the source electrode; And A method of manufacturing a transverse electric field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate. The transverse electric field of claim 1, further comprising forming a common line at a lower end of the pixel area in a direction substantially parallel to the gate line when forming the gate line on the first substrate. Method of manufacturing a liquid crystal display device. The method of claim 1, further comprising forming a first line at an edge of the pixel region in a direction substantially parallel to the data line when forming a gate line on the first substrate. Method of manufacturing a transverse electric field liquid crystal display device. The transverse electric field method of claim 1, further comprising forming an ohmic contact layer on the active pattern to ohmic-contact the source / drain region of the active pattern and the source / drain electrode. Method of manufacturing a liquid crystal display device. 2. The method of claim 1, further comprising forming a first contact hole exposing a portion of the drain electrode by removing a portion of the second insulating layer. . The transverse electric field liquid crystal display device according to claim 5, further comprising forming a pixel electrode line electrically connected to the drain electrode through the first contact hole and connected to the pixel electrode. Manufacturing method. 4. The method of claim 3, further comprising forming a second contact hole exposing a portion of the first line by removing a portion of the second insulating layer. Way. The method of claim 7, wherein when the common electrode, the pixel electrode, and the repair line are formed on the first substrate, the common electrode, the pixel electrode, and the repair line are arranged in a direction substantially parallel to the gate line to electrically connect with the first line through the second contact hole. And forming a second line connected to the common electrode while being connected to the common electrode. The method of claim 1, wherein when a short circuit defect occurs in a part of the thin film transistor, Cutting both sides of the data line connected to the source electrode of the corresponding pixel, and removing the second insulating layer on the cut data line to form an exposure hole exposing a portion of the data line; And And forming a repair pattern for electrically connecting the data line and the repair line through the exposure hole. A gate line including a gate electrode formed on the first substrate; A first insulating film formed on the first substrate; An active pattern formed on the gate electrode, a source electrode and a drain electrode having a 'U' shape; A data line formed on the first substrate such that a portion thereof forms a part of the source electrode and defining a pixel region intersecting the gate line; A second insulating film formed on the first substrate; A common electrode and a pixel electrode disposed alternately in the pixel region to generate a transverse electric field; A repair line formed in an isolated structure on both sides of the data line connected to the source electrode; And And a second substrate bonded to the first substrate. The transverse electric field liquid crystal display device according to claim 10, further comprising a common line formed at a lower end of the pixel area and formed in a direction substantially parallel to the gate line. The transverse electric field liquid crystal display device according to claim 10, further comprising a first line formed at an edge of the pixel area and formed in a direction substantially parallel to the data line. The transverse electric field liquid crystal of claim 10, further comprising an ohmic contact layer formed on the active pattern and ohmic-contacting a source / drain region of the active pattern and the source / drain electrode. Display. 11. The transverse electric field liquid crystal display device according to claim 10, further comprising a first contact hole for removing a portion of the second insulating layer to expose a portion of the drain electrode. 15. The transverse electric field liquid crystal display device according to claim 14, further comprising a pixel electrode line electrically connected to the drain electrode through the first contact hole and connected to the pixel electrode. 13. The transverse electric field liquid crystal display device according to claim 12, further comprising a second contact hole for removing a portion of the second insulating layer to expose a portion of the first line. 17. The display device of claim 16, further comprising a second line arranged in a direction substantially parallel to the gate line and electrically connected to the first line through the second contact hole while being connected to the common electrode. Transverse electric field type liquid crystal display device characterized in that. The pixel of claim 10, wherein a short circuit defect occurs in the thin film transistor. Cutting lines formed on both sides of the data line connected to the source electrode of the pixel; An exposure hole exposing a portion of the data line by removing a second insulating layer on the cut data line; And And a repair pattern for electrically connecting the data line and the repair line through the exposed hole.

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