KR20080075717A

KR20080075717A - Method of fabricating in plane switching mode liquid crystal display device

Info

Publication number: KR20080075717A
Application number: KR1020070014999A
Authority: KR
Inventors: 오금미; 오재영
Original assignee: 엘지디스플레이 주식회사
Priority date: 2007-02-13
Filing date: 2007-02-13
Publication date: 2008-08-19

Abstract

The method of manufacturing a transverse electric field type liquid crystal display device of the present invention includes an organic insulating film having a low dielectric constant when forming a protective film, thereby improving the aperture ratio of the liquid crystal display panel and treating the organic insulating film at a temperature before curing. Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion to enable a number of masks by collectively etching the inorganic insulating layer; Forming a gate electrode, a gate line, and a first common electrode on the pixel portion of the first substrate; Forming a gate insulating film on the first substrate; Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate, and forming a data line crossing the gate line to define a pixel region; A first passivation layer made of an inorganic insulation layer, a second passivation layer made of an organic insulation layer, and a third passivation layer made of an inorganic insulation layer are formed on the first substrate, wherein the second passivation layer has a temperature before curing of the organic insulation layer. Forming at ° C .; Removing a portion of the first to third passivation layers to form a first contact hole exposing a portion of the drain electrode; Forming a pixel electrode line electrically connected to the drain electrode through the first contact hole, and forming a second common electrode, a third common electrode, and a pixel electrode which are alternately disposed in the pixel region to generate a transverse electric field; step; And bonding the first substrate and the second substrate to each other.

Description

Manufacturing method of transverse electric field type liquid crystal display device {METHOD OF FABRICATING IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view showing a part of an array substrate of a general transverse electric field type liquid crystal display device;

3A to 3E are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate shown in FIG. 2.

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

5A to 5D are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate shown in FIG.

6A to 6D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A to 7F are cross-sectional views illustrating a second mask process according to an embodiment of the present invention in the array substrate shown in FIGS. 5B and 6B.

8A to 8E are cross-sectional views illustrating a third mask process according to an embodiment of the present invention in the gate pad portion of the array substrate illustrated in FIGS. 5C and 6C.

** Explanation of symbols for main parts of drawings **

108a ~ 108c: common electrode 108l: common line

110 array substrate 115a gate insulating film

115b '~ 115b' ": Shield 116: Gate line

117 data line 118 pixel electrode

118l: pixel electrode line 121: gate electrode

122 source electrode 123 drain electrode

124: active pattern 140a ~ 140d: contact hole

The present invention relates to a method of manufacturing a transverse electric field type liquid crystal display device, and more particularly, to a transverse electric field type liquid crystal display which can reduce the number of masks, simplify the manufacturing process, improve yield, and improve the aperture ratio of the liquid crystal display panel. A method of manufacturing a device.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, a liquid crystal display (LCD) is a device that displays an image using optical anisotropy of liquid crystal, and is actively applied to a laptop or a desktop monitor because it is excellent in resolution, color display, and image quality. It is becoming.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules oriented horizontally with the substrate are oriented almost perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

Accordingly, there is an in-plane switching (IPS) type liquid crystal display device in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle to 170 degrees or more.

2 is a plan view illustrating a part of an array substrate of a general transverse electric field type liquid crystal display device.

As shown in the figure, a gate line 16 and a data line 17 are formed on the array substrate 10 of the transverse electric field type liquid crystal display device, which is arranged vertically and horizontally on the transparent array substrate 10 to define a pixel area. The thin film transistor, which is a switching element, is formed at the intersection of the gate line 16 and the data line 17.

The thin film transistor includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor may include a gate insulating film (not shown) for insulation between the gate electrode 21 and the source / drain electrodes 22 and 23 and the source electrode by a gate voltage supplied to the gate electrode 21. An active pattern (not shown) for forming a conductive channel between the 22 and the drain electrode 23 is included.

In this case, the common electrode 8 and the pixel electrode 18 for generating the transverse electric field are alternately arranged in the direction parallel to the data line 17 in the pixel region. In this case, the pixel electrode 18 is electrically connected to the drain electrode 23 through a contact hole 40 formed in a passivation layer (not shown), and the common electrode 8 is connected to the gate line 16. It is connected to the common line 8l arranged in parallel.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

3A to 3E are cross-sectional views sequentially illustrating a manufacturing process along line II-II ′ of the array substrate illustrated in FIG. 2.

As shown in FIG. 3A, a gate electrode 21 made of a conductive metal material, a common electrode 8, and a gate line (not shown) are formed on the array substrate 10 using a photolithography process (first mask process). Form.

Next, as shown in FIG. 3B, the gate insulating film 15a and the amorphous silicon thin film are sequentially formed on the entire surface of the array substrate 10 on which the gate electrode 21, the common electrode 8, and the gate line are formed. After depositing the n + amorphous silicon thin film, the active pattern made of the amorphous silicon thin film on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film using a photolithography process (second mask process). To form (24).

In this case, an n + amorphous silicon thin film pattern 25 patterned in the same shape as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 3C, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (third mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In addition, a data line 17 defining a pixel region is formed together with the gate line through the third mask process.

In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed between the active pattern 24 and the source / drain electrodes 22 and 23 by removing a predetermined region through the third mask process. An ohmic contact layer 25 'for ohmic contact is formed.

Next, as shown in FIG. 3D, a protective film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22, the drain electrode 23, and the data line 17 are formed, and then a photolithography process. Through the fourth mask process, a portion of the passivation layer 15b is removed to form a contact hole 40 exposing a portion of the drain electrode 23.

Finally, as shown in FIG. 3E, the contact hole 40 is formed by depositing a transparent conductive metal material on the entire surface of the array substrate 10 and then selectively patterning the same by using a photolithography process (a fifth mask process). The pixel electrode 18 is formed to be electrically connected to the drain electrode 23.

As described above, fabrication of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active pattern, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. It has the disadvantage of dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device in which an array substrate is manufactured by four mask processes.

Another object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device for improving the aperture ratio of a liquid crystal display panel.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, a method of manufacturing a transverse electric field type liquid crystal display device of the present invention comprises the steps of providing a first substrate divided into a pixel portion, a data pad portion and a gate pad portion; Forming a gate electrode, a gate line, and a first common electrode on the pixel portion of the first substrate; Forming a gate insulating film on the first substrate; Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate, and forming a data line crossing the gate line to define a pixel region; A first passivation layer made of an inorganic insulation layer, a second passivation layer made of an organic insulation layer, and a third passivation layer made of an inorganic insulation layer are formed on the first substrate, wherein the second passivation layer has a temperature before curing of the organic insulation layer. Forming at ° C .; Removing a portion of the first to third passivation layers to form a first contact hole exposing a portion of the drain electrode; Forming a pixel electrode line electrically connected to the drain electrode through the first contact hole, and forming a second common electrode, a third common electrode, and a pixel electrode which are alternately disposed in the pixel region to generate a transverse electric field; step; And bonding the first substrate and the second substrate to each other.

Hereinafter, a preferred embodiment of a method of manufacturing a transverse electric field type liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention. For convenience of description, one pixel including a gate pad part, a data pad part, and a thin film transistor of a pixel part is illustrated. Indicates.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

In this case, the present embodiment has been described using a transverse electric field type liquid crystal display as an example, but the present invention is not limited thereto, and the present invention may be applied to a twisted nematic liquid crystal display.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 according to an embodiment of the present invention, which are arranged vertically and horizontally on the array substrate 110 to define a pixel region. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 116 and the data line 117, and the common electrode 108a driving a liquid crystal (not shown) by generating a transverse electric field in the pixel area. 108c and the pixel electrode 118 are alternately formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to form a first contact hole formed in a passivation layer (not shown). The pixel electrode line 118l and the pixel electrode 118 are electrically connected to each other via 140a.

As described above, the common electrodes 108a to 108c and the pixel electrodes 118 for generating the transverse electric field are alternately arranged in the pixel region.

In this case, the common electrodes 108a to 108c may connect the first and second common lines 108l disposed in parallel with the gate line 116 to the left and right of the pixel area, respectively. And a pixel area between the second common electrode 108b and the second common electrode 108b formed on the first common electrode 108a to overlap a portion of the first common electrode 108a. The third common electrode 108c is included.

In this case, the first common electrode 108a to the third common electrode 108c are connected to the second common line 108l 'disposed in a direction parallel to the gate line 116, and the second common The line 108l ′ is electrically connected to the first common line 108l of the upper portion through the second contact hole 140b formed in the gate insulating layer (not shown) and the passivation layer.

The first common electrode 108a is made of the same opaque conductive material as the common line 108l, and the second common electrode 108b and the third common electrode 108c are the pixel electrode 118 and the pixel. It may be made of the same transparent conductive material as the electrode line 118l.

In this case, a portion of the pixel electrode line 118l overlaps a portion of the first common line 108l below the gate insulating layer and the passivation layer to form a storage capacitor. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. In addition to maintaining the signal, the storage capacitor has effects such as stabilization of gray scale display and reduction of flicker and afterimage.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140c and 140d represent a third contact hole and a fourth contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the third contact hole 140c. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the fourth contact hole 140d.

In this case, as shown in FIG. 4, when the common electrodes 108a to 108c, the pixel electrodes 118, and the data lines 117 have a bent structure, liquid crystal molecules are arranged in two directions. By forming a two-domain, the viewing angle is further improved compared to the mono-domain. However, the present invention is not limited to the two-domain transverse electric field liquid crystal display device, and the present invention can be applied to the transverse electric field liquid crystal display device having a multi-domain structure of two or more domains. For reference, an IPS structure for forming a multi-domain of two or more domains is called an S-IPS (Super-IPS) structure.

In addition, when the common electrodes 108a to 108c, the pixel electrodes 118, and the data lines 117 are formed in a bent structure to form a multi-domain structure in which the driving directions of liquid crystal molecules are symmetrical, birefringence of liquid crystals is performed. The color shift phenomenon can be minimized by canceling the abnormal light due to the birefringence characteristic.

Here, in the transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention, a mask process is performed using a diffraction mask or a half-tone mask (hereinafter referred to as a half-tone mask when referring to a diffraction mask). By forming active patterns, source / drain electrodes, and data lines, array substrates can be fabricated using a total of four mask processes.

In addition, the transverse electric field type liquid crystal display device according to the embodiment of the present invention forms a protective film having a three-layer structure of an inorganic insulating film, an organic insulating film, and an inorganic insulating film. As such, an organic insulating film having a low dielectric constant is included in the protective film. As the opening ratio of the panel is improved and an inorganic insulating film is formed above and below the organic insulating film, problems such as an increase in off current of the thin film transistor by the organic insulating film and no liquid crystal injection are prevented. In particular, by treating the organic insulating film at a temperature before curing, it is possible to collectively etch the inorganic insulating film so that the aperture ratio can be improved without adding a mask, and the following method of manufacturing a transverse electric field type liquid crystal display device is described. It will be described in detail through.

5A through 5D are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate illustrated in FIG. 4, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

As shown in FIGS. 5A and 6A, the gate electrode 121, the gate line 116, the first common electrode 108a and the first portion of the pixel portion of the array substrate 110 made of a transparent insulating material such as glass may be used. A common line 108l is formed, and a gate pad line 116p is formed in the gate pad portion of the array substrate 110.

In this case, the first common line 108l is formed above and below the pixel area in a direction substantially parallel to the gate line 116, and the first common electrode 108a is formed on the left and right sides of the pixel area. Is formed in the upper and lower first common line (108l) is connected to each other.

In this case, the gate electrode 121, the gate line 116, the first common electrode 108a, the first common line 108l, and the gate pad line 116p are formed on the entire surface of the array substrate 110. After deposition, it is formed by selectively patterning through a photolithography process (first mask process).

Here, the first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and Low resistance opaque conductive materials such as molybdenum alloys can be used. In addition, the first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIGS. 5B and 6B, the gate electrode 121, the gate line 116, the first common electrode 108a, the first common line 108l, and the gate pad line 116p are formed. After forming the gate insulating film 115a, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film on the formed array substrate 110, the array substrate may be selectively removed by a photolithography process (second mask process). A source / drain electrode formed of the amorphous silicon thin film on the pixel portion of the pixel 110 and electrically connected to a source / drain region of the active pattern 124; 122, 123.

In addition, a data line 117 formed of the second conductive layer is formed on the data line of the array substrate 110 through the second mask process, wherein the data line 117 is the first common electrode. And overlap with a portion of the 108a.

In addition, a data pad line 117p formed of the second conductive layer is formed on the data pad portion of the array substrate 110 through the second mask process.

In this case, an ohmic contact layer 125n formed of the n + amorphous silicon thin film and patterned in the same form as the source / drain electrodes 122 and 123 is formed on the active pattern 124.

In addition, a lower portion of the data line 117 and the data pad line 117p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 117 and the data pad line 117p. The first amorphous silicon thin film pattern 120 ', the second n + amorphous silicon thin film pattern 125 ", and the second amorphous silicon thin film pattern 120" and the third n + amorphous silicon thin film pattern 125' "are formed.

The active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 according to the exemplary embodiment of the present invention are simultaneously formed in one mask process (second mask process) using a diffraction mask. The second mask process will now be described in detail with reference to the accompanying drawings.

7A to 7F are cross-sectional views illustrating a second mask process according to an exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 5B and 6B.

As shown in FIG. 7A, an array substrate 110 having the gate electrode 121, the gate line 116, the first common electrode 108a, the first common line 108l, and the gate pad line 116p is formed. A gate insulating film 115a, an amorphous silicon thin film 120, an n + amorphous silicon thin film 125 and a second conductive film 130 are formed on the entire surface.

In this case, the second conductive layer 130 may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line.

And, as shown in Figure 7b, after forming a photosensitive film 170 made of a photosensitive material such as photoresist on the array substrate 110, the through the diffraction mask 180 according to an embodiment of the present invention Light is selectively irradiated to the photosensitive film 170.

In this case, the diffraction mask 180 is applied to the first transmission region (I) and the slit pattern that transmits all the irradiated light is applied to the second transmission region (II) and all the irradiated light to transmit only a part of the light and block some. The blocking region III is provided to block the light, and only the light passing through the diffraction mask 180 is irradiated onto the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the diffraction mask 180 is developed, all light is blocked through the blocking region III and the second transmission region II, as shown in FIG. 7C. The first photoresist pattern 170a to the fifth photoresist pattern 170e having a predetermined thickness remain in a region where only a portion thereof is blocked or partially blocked, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the second conductive film 130 is exposed.

In this case, the first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III are formed thicker than the fifth photoresist pattern 170e formed through the second transmission region II. In addition, the photoresist film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto. It is okay.

Next, as shown in FIG. 7D, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second formed on the lower portion of the first photosensitive film pattern 170a to the fifth photosensitive film pattern 170e formed as described above are used as a mask. When the conductive film is selectively removed, an active pattern 124 made of the amorphous silicon thin film is formed on the pixel portion of the array substrate 110, and the second conductive layer is formed on the data line portion of the array substrate 110. The formed data line 117 is formed.

In addition, a data pad line 117p formed of the second conductive layer is formed in the data pad part of the array substrate 110.

In this case, the first n + amorphous silicon thin film pattern 125 ′ and the second conductive layer formed of the n + amorphous silicon thin film and the second conductive layer and patterned in the same shape as the active pattern 124, respectively, on the active pattern 124. The conductive film pattern 130 ′ is formed.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a to the fifth photoresist pattern 170e is performed, as illustrated in FIG. 7E, the second transmission region II is formed. The fifth photosensitive film pattern of is completely removed.

In this case, the first photoresist pattern to the fourth photoresist pattern correspond to the blocking region III by the sixth photoresist pattern 170a 'through the ninth photoresist pattern 170d' where the thickness of the fifth photoresist pattern is removed. Only the source electrode region and the drain electrode region and the upper portion of the data line 117 and the data pad line 117p remain.

Subsequently, as shown in FIG. 7F, a portion of the first n + amorphous silicon thin film pattern and the second conductive film pattern using the remaining sixth photoresist pattern 170a ′ through the ninth photoresist pattern 170d ′ as a mask. The source electrode 122 and the drain electrode 123 formed of the second conductive layer are formed in the pixel portion of the array substrate 110 by removing the?

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active pattern 124 and ohmic-contacting between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123. 125n is formed.

As described above, according to the exemplary embodiment of the present invention, the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 may be formed through one mask process by using a diffraction mask.

Subsequently, as shown in FIGS. 5C and 6C, the passivation layers 115b ′ to 115b are disposed on the entire surface of the array substrate 110 on which the active patterns 124, the source / drain electrodes 122 and 123, and the data lines 117 are formed. '").

In this case, the passivation layers 115b 'to 115b' "include the first passivation layer 115b 'made of an inorganic insulation layer such as silicon nitride and the second passivation layer 115b" made of an organic insulation layer such as photoacryl and the inorganic insulation layer. It is characterized by having a three-layer structure including a third protective film (115b '") made of.

As such, the first passivation layer 115b 'is formed of an inorganic insulating layer to protect the back channel of the active pattern 124, and the second passivation layer 115b "has a low dielectric constant such as photoacryl. By forming an organic insulating film having a structure, the data line 117 and the first common electrode 108a and the second common electrode to be described later can be overlapped to realize a high opening ratio structure.

In addition, a third passivation layer 115b '″ made of an inorganic insulation layer may be further formed on the organic insulation layer to solve the interfacial characteristics with the pixel electrode and the liquid crystal non-injection problem described later.

In this case, when the passivation layer is formed of only the organic insulation layer, the back channel portion of the lower portion of the organic insulation layer is exposed to the organic material to increase the off current, thereby deteriorating the electrical characteristics of the thin film transistor, and forming a pixel electrode on the organic insulation layer. As a result, the interface properties deteriorate and problems such as non-injection of the liquid crystal are generated.

However, the three-layered protective film in which the inorganic insulating film, the organic insulating film, and the inorganic insulating film are stacked as described above has a disadvantage in that it is impossible to collectively etch, thereby increasing the manufacturing cost as an additional mask process is required. The reason why the three-layered protective film could not be collectively etched in the conventional process is because the thickness of the organic insulating film is about 3 μm and the etching rate is low, thereby limiting the application of the dry etching process.

Accordingly, in the exemplary embodiment of the present invention, the organic insulating layer and the inorganic insulating layer thereon are deposited at a temperature at which the organic insulating layer is not completely cured, thereby increasing the etch rate of the organic insulating layer so that the organic etching layer can be easily etched by a dry etching process. As a result, the passivation layers 115b 'to 115b' "and the gate insulating layer 115a of the three-layer structure in which the inorganic insulating layer, the organic insulating layer, and the inorganic insulating layer are stacked are etched through the mask process, and the drain electrode 123, A first contact hole 140a, a second contact hole 140b, and a third contact hole 140c exposing portions of the first common line 108l, the data pad line 117p, and the gate pad line 116p, respectively. And the fourth contact hole 140d.

Hereinafter, the third mask process will be described in detail with reference to the accompanying drawings.

8A to 8E are cross-sectional views illustrating a third mask process according to an embodiment of the present invention in the gate pad portion of the array substrate shown in FIGS. 5C and 6C. A process of forming the fourth contact hole is shown as an example.

As shown in FIG. 8A, a first passivation layer 115b 'made of an inorganic insulation layer, a second passivation layer 115b ″ made of an organic insulation layer, and a third passivation layer 115b made of an inorganic insulation layer are sequentially formed on the array substrate 110. '").

In this case, when the second protective film 115b ″ is formed of photoacryl, the photoacryl is coated on the entire surface of the array substrate 110 on which the first protective film 115b 'is deposited, and then the photoacryl is cured. Soft bake is carried out at a temperature of about 230 ° C. or less (eg, about 90 ° C. to about 150 ° C.), in which the first bake is included in the organic insulating film, and thus, Proceed to remove any solvents that may affect.

Thereafter, an inorganic insulating film is deposited on the entire surface of the array substrate 110 on which the second passivation layer 115b ″ is formed at a temperature of less than 150 ° C., for example, about 90 ° C. to 150 ° C., to form the third passivation layer 115b '″. Will form.

Next, as shown in FIG. 8B, a photoresist pattern 270 made of photoresist is formed on the array substrate 110 on which the passivation layers 115b 'to 115b' ″ are formed.

In this case, the photoresist pattern 270 is patterned to expose a portion of the third passivation layer 115b ′ ″ above the gate pad line 116p to form a fourth contact hole in the gate pad portion.

Subsequently, as shown in FIGS. 8C and 8D, the first passivation layer 115b 'to the third passivation layer 115b' ″ and the gate insulating layer 115a below the photoresist pattern 270 are used as a mask. Remove some.

Here, dry etching may be applied to etching the first passivation layer 115b 'to the third passivation layer 115b' ″ and the gate insulating layer 115a, and the dry etching process may be performed at a vacuum degree of 70 to 200 mT and 1000 to 1300 W. The gas ratio of SF ₆ and O ₂ may be about 1: 0.05 ~ 1 (preferably 1: 0.1) under RF power of (Radio frequency power).

As described above, the etching rate of the photoacryl in the case of performing only the first bake is about 7000 mW / min in the dry etching process condition, but when the second bake is performed at 230 ° C., the first bake is about 50 mW / min. It can be seen that the etching rate of the photoacryl is very small as compared with the case where only the progress was made. That is, in the case of the present invention, by treating the photoacryl at a temperature before curing, the etch rate of the photoacryl can be increased, thereby enabling collective etching with the inorganic insulating layer.

In this case, when the gate insulating film 115a, the first passivation film 115b ', the second passivation film 115b ", and the third passivation film 115b'" are formed to have a thickness of about 5000 mV, 1000 mV, 2.5 µm and 1000 mV, respectively. For example, dry etching is performed on the third passivation layer 115b '″ and the second passivation layer 115b ″ in four steps, and the first passivation layer (5th or 6th step) is performed. 115b ') and a portion of the thickness of the gate insulating film 115a, for example, about 3000 kPa, are removed.

Subsequently, as illustrated in FIG. 8E, the fourth contact hole 140d exposing a portion of the data pad line 116p by removing a portion of the gate insulating layer 115a remaining as the mask using the photoresist pattern 270 as a mask. ).

In this case, the dry etching process may be performed at a gas ratio of SF ₆ and O ₂ of 1: 2 to 5 (preferably 1: 3.5) under a vacuum degree of 70 to 200 mT and an RF power of 1000 to 1300 W. An etching rate of the photoacryl is greater than an etching rate (about 3000 μs / min), thereby forming a fourth contact hole 140d having a lateral shape as illustrated.

In this case, the dotted line illustrated in the drawing indicates side surfaces of the photoresist pattern, the gate insulating layer, and the protective layer before the width is reduced by the dry etching process illustrated in FIG. 8C.

Next, as shown in FIGS. 5D and 6D, the array substrate 110 having the three-layered protective layers 115b 'to 115b' ″ and the first contact holes 140a to fourth contact holes 140d are formed. A third conductive film formed of a transparent conductive material on the entire surface thereof, and then selectively patterned using a photolithography process (fourth mask process) to electrically connect with the drain electrode 123 through the first contact hole 140a. A pixel electrode line 118l is formed to be connected to each other, and a second common line 108l 'is formed to be electrically connected to the first common line 108l through the second contact hole 140b.

In addition, by selectively patterning the third conductive layer through the fourth mask process, the second common electrode 108b, the third common electrode 108c, and the pixel electrode disposed alternately in the pixel region to generate a transverse electric field. 118 and a data pad electrode 127p electrically connected to the data pad line 117p and the gate pad line 116p through the third contact hole 140c and the fourth contact hole 140d, respectively. And a gate pad electrode 126p.

In this case, the second common electrode 108b and the third common electrode 108c are connected to the second common line 108l ', and the pixel electrode 118 is connected to the pixel electrode line 118l. .

In addition, the third conductive layer may be formed of indium tin oxide (ITO) or indium-zinc- to form the second common electrode 108b, the third common electrode 108c, and the pixel electrode 118. It includes a transparent conductive material having excellent transmittance such as indium zinc oxide (IZO).

In this case, before the deposition of the third conductive film, a second baking process for curing the second protective film 115b ″ made of the photoacryl may be performed, and the second baking process may be performed at 200 to 250 ° C. (preferably 230 It may proceed at a temperature of about ℃) and after the completion of the array substrate 110 may be.

In this case, when the three-layered protective film 115b 'to 115b' ″ in which the organic insulating film is stacked is applied as in the exemplary embodiment of the present invention, the second common electrode 108b may have a lower portion of the first common electrode 108a. The first common electrode 108a overlaps a portion of the upper data line 117 so that the aperture ratio of the liquid crystal display panel is substantially improved.

The array substrate according to the embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the color filter substrate includes light through the thin film transistor, the gate line, and the data line. Black matrix to prevent leakage and color filter for red, green and blue color are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

As described above, the embodiment of the present invention describes an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern, for example. However, the present invention is not limited thereto, and the present invention provides a polycrystalline silicon thin film as the active pattern. The same applies to the polysilicon thin film transistors used.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the method of manufacturing the transverse electric field type liquid crystal display device according to the present invention provides the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the method of manufacturing a transverse electric field type liquid crystal display device according to the present invention includes an organic insulating film having a low dielectric constant when forming a protective film, thereby improving the aperture ratio of the liquid crystal display panel and collectively combining the organic insulating film together with an inorganic insulating film. By etching, the number of masks can be reduced.

Claims

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion;

Forming a gate electrode, a gate line, and a first common electrode on the pixel portion of the first substrate;

Forming a gate insulating film on the first substrate;

Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate, and forming a data line crossing the gate line to define a pixel region;

A first passivation layer made of an inorganic insulation layer, a second passivation layer made of an organic insulation layer, and a third passivation layer made of an inorganic insulation layer are formed on the first substrate, wherein the second passivation layer has a temperature before curing of the organic insulation layer. Forming at ° C .;

Removing a portion of the first to third passivation layers to form a first contact hole exposing a portion of the drain electrode;

Forming a pixel electrode line electrically connected to the drain electrode through the first contact hole, and forming a second common electrode, a third common electrode, and a pixel electrode which are alternately disposed in the pixel region to generate a transverse electric field; step; And

A method of manufacturing a transverse electric field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate.

The transverse electric field liquid crystal display of claim 1, further comprising forming a first common line formed in a pixel portion of the first substrate and disposed in a direction parallel to the gate line. Method of manufacturing the device.

3. The method of claim 2, further comprising forming a second contact hole exposing a portion of the first common line by removing partial regions of the gate insulating layer and the first to third passivation layers. Method of manufacturing a transverse electric field liquid crystal display device.

4. The method of claim 3, further comprising forming a second common line electrically connected to the first common line through the second contact hole.

The method of claim 4, wherein the second common electrode and the third common electrode are connected to the second common line.

The method of claim 2, wherein the first common electrode is connected to the first common line at left and right sides of the pixel area.

The method of claim 1, further comprising forming a data pad line on the data pad portion of the first substrate.

8. The transverse electric field liquid crystal of claim 7, further comprising removing a partial region of the first to third passivation layers to form a third contact hole exposing a portion of the data pad line. Method for manufacturing a display device.

The method of claim 8, further comprising forming a data pad electrode electrically connected to the data pad line through the third contact hole.

The method of claim 1, further comprising forming a gate pad line on the gate pad of the first substrate.

The method of claim 10, further comprising forming a fourth contact hole exposing a portion of the gate pad line by removing partial regions of the gate insulating layer and the first to third passivation layers. Method of manufacturing an electric field type liquid crystal display device.

12. The method of claim 11, further comprising forming a gate pad electrode electrically connected to the gate pad line through the fourth contact hole.

The method of claim 1, wherein the data line overlaps a portion of the first common electrode.

The method of claim 1, wherein the second common electrode is formed to overlap a portion of the first common electrode.

The method of claim 1, wherein the first to third common electrodes, the pixel electrode, and the data line are formed to have a bent structure.

The method of claim 1, wherein the first protective film and the third protective film are formed of an inorganic insulating film such as a silicon nitride film.

The method of manufacturing a transverse electric field liquid crystal display device according to claim 1, wherein the second protective film is formed of an organic insulating film such as photoacrylic.

The horizontal field type liquid crystal display device of claim 1, further comprising: curing the organic insulating layer by heat-treating the array substrate at a temperature of 200 ° C. to 250 ° C. before forming the pixel electrode. Way.

The method of claim 1, wherein the gate insulating layer and the first to third passivation layers are selectively removed through a dry etching process.

20. The method of claim 19, wherein the dry etching process is performed under a vacuum degree of 70 to 200 mT and an RF power of 1000 to 1300 W.

The method of claim 19 or 20, wherein in the dry etching process, the primary etching process in which the gas ratio of SF ₆ and O ₂ is 1: 0.05 to 1 and the gas ratio of SF ₆ and O ₂ 1: 2. A method of manufacturing a transverse electric field type liquid crystal display device, comprising a secondary etching process performed in the range of ˜5.