KR20090016340A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A liquid crystal display device and a manufacturing method thereof are provided to manufacture an array substrate without the tail of an active pattern by performing a mask process four times. A liquid crystal display device comprises the followings: a gate electrode(221) and gate line(216) formed by the first conductive film on the first substrate; a data line(217) which is formed so as to be separated in each pixel region by being cut down at a part through which the gate line passes; the first insulating layer formed on the first substrate; an active pattern which is formed in an island type in a state that the first insulating layer is interposed at the upper portion of the gate electrode; and a source electrode and drain electrode(223) which are formed by the second conductive film on the first substrate.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same. More particularly, the liquid crystal display device and its fabrication method which reduce the number of masks, simplify the manufacturing process and improve yield, and do not have a tail of an active pattern. It is about a method.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 using a photolithography process (first mask process).

Next, as shown in FIG. 2B, the first insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed. The active pattern 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same shape as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 2C, a conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (third mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process, thereby forming an ohmic − between the active pattern 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25 'is formed.

Next, as shown in FIG. 2D, a second insulating film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process (fourth mask). The contact hole 40 exposing a part of the drain electrode 23 is formed by removing a part of the second insulating layer 15b through the process).

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned by using a photolithography process (a fifth mask process) through the contact hole 40. The pixel electrode 18 electrically connected to the drain electrode 23 is formed.

As described above, fabrication of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active pattern, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. There is a downside to dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

At this time, by forming the active pattern and the source / drain electrodes in a single mask process using a diffraction mask, a technique for manufacturing an array substrate using a total of four mask processes has been developed.

However, the liquid crystal display of the structure uses a diffraction mask to pattern the active pattern and the source / drain electrodes through two etching processes, so that the active pattern protrudes around the bottom of the source electrode, the drain electrode, and the data line. Will remain.

The active pattern is made of a pure amorphous silicon thin film, and the protruding active pattern is exposed to the backlight of the lower portion, so that photocurrent is generated by the backlight. At this time, due to the minute flickering of the backlight light, the amorphous silicon thin film reacts finely, and the activation and deactivation states are repeated, thereby causing a change in the photocurrent. The photocurrent component is coupled with a signal flowing to a neighboring pixel electrode to distort the movement of the liquid crystal located in the pixel electrode. As a result, wavy noise in which wavy thin lines appear on the screen of the liquid crystal display is generated.

In addition, the active pattern positioned below the data line may protrude a predetermined distance to both sides of the data line, thereby decreasing the aperture ratio of the liquid crystal display device as the opening area of the pixel portion is eroded by the protruding distance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which produce a tailless array substrate of an active pattern in four mask processes.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can realize high brightness by enlarging the opening area and at the same time not generating wave noise.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display of the present invention comprises a gate electrode and a gate line formed of a first conductive film on the first substrate; A data line formed of the first conductive layer and formed to be cut at a portion through which the gate line passes and separated from each pixel area; A first insulating film formed on the first substrate; An active pattern formed in an island shape with the first insulating film interposed on the gate electrode; A source electrode and a drain electrode formed of a second conductive film on the first substrate; A connection line formed of the second conductive layer and connecting the separated data lines to each other through a contact hole formed by removing a portion of the first insulating layer; A pixel electrode formed of a third conductive film in the pixel region; A second insulating layer formed on the first substrate and exposing the pixel electrode; And a second substrate bonded to and opposed to the first substrate.

In addition, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate divided into a pixel portion, a data pad portion and a gate pad portion; Forming a gate electrode and a gate line on the pixel portion of the first substrate through a first mask process; Defining a pixel area crossing the gate line by using the first mask process, and forming a data line which is cut at a portion where the gate line passes and is separated from each pixel area; Forming a first insulating film on the first substrate; Forming an island-type active pattern with the first insulating layer interposed on the gate electrode through a second mask process, and forming an n + amorphous silicon thin film pattern on the active pattern; Removing a partial region of the first insulating layer using the second mask process to form a first contact hole exposing portions of both ends of the separated data line; Forming a source electrode, a drain electrode, and a pixel electrode in a pixel portion of the first substrate through a third mask process, and forming a connection line connecting the separated data lines to each other through the first contact hole; Forming a second insulating film on the first substrate; Removing a portion of the second insulating layer through a fourth mask process to expose a portion of the pixel electrode, the data pad electrode, and the gate pad electrode; And bonding the first substrate and the second substrate to each other.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention provide an effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the liquid crystal display and the method of manufacturing the same according to the present invention do not have a tail of the active pattern, and thus there is no signal interference of the data line, and the aperture ratio increases by the tail width of the active pattern.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention does not generate wave noise provides an effect that can produce a high-quality liquid crystal display device.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged vertically and horizontally on the array substrate 110 to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

Although not shown in the drawing, a gate pad electrode and a data pad electrode electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110. The scan signal and the data signal applied from the driving circuit unit are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line and the data pad line, respectively, and the gate pad line and the data pad line are the gate pad line and the data pad line. Scan signals and data signals are applied from the driving circuit unit through gate pad electrodes and data pad electrodes electrically connected to the lines, respectively.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. .

Here, the present invention describes a thin film transistor having a “U” shape in which the source electrode 122 has a “U” shape, but the present invention is a form of the source electrode 122, that is, a thin film transistor. It is not limited to the channel form of.

In this case, the gate line 116 and the data line 117 according to the first embodiment of the present invention are formed of the same conductive material through the same mask process, and the data line 117 is the gate line 116. ) Is cut at the passing part and has a separated structure.

The data line 117 separated by the gate line 116 is connected to each other through the first contact hole 140a and the connection line 127 formed in the first insulating layer (not shown). In addition, a part of the source electrode 122 forms a part of the connection line 127 to be electrically connected to the separated data line 117 through the first contact hole 140a, and the drain electrode A portion of 123 extends toward the pixel region to constitute the pixel electrode 118.

As such, the source electrode 122, the drain electrode 123, and the connection line 127 are formed of the same transparent conductive material as the pixel electrode 118 through the same mask process.

In addition, the active pattern according to the first embodiment of the present invention is formed of an amorphous silicon thin film, and is formed in an island shape only on the gate electrode 121 so that the off current of the thin film transistor can be reduced. do.

In this case, a portion of the gate line 116 positioned at the front end may overlap the portion of the pixel electrode 118 on the upper portion of the gate line 116 to form a storage capacitor Cst. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. In general, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is input and is leaked. Disappear. Therefore, in order to maintain the applied voltage, the storage capacitor Cst needs to be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stability of gray scale display and reduction of flicker and afterimage in addition to signal retention.

Here, in the first embodiment of the present invention, the gate line 116 and the data line 117 are simultaneously formed in one mask process, and the pixel electrode 118 and the source electrode 122 are formed in another mask process. By simultaneously forming the drain electrode 123, the array substrate 110 may be manufactured through a total of four mask processes.

In this case, as the gate line 116 and the data line 117 are formed at the same time, the data line 117 of the present invention has a structure in which the gate line 116 is cut and separated. In the first embodiment of the present invention, when the pixel electrode 118 is formed, the separated data lines 117 are connected to each other by using the connection line 127, which is described in detail through the manufacturing method of the following liquid crystal display device. Explain.

4A through 4D are cross-sectional views sequentially illustrating a manufacturing process along line III-III ′ of the array substrate illustrated in FIG. 3, illustrating a process of manufacturing an array substrate of a pixel portion including a data line portion on the left side and a turn on the right side. As shown, a process of manufacturing an array substrate of a data pad portion and a gate pad portion is shown.

5A to 5C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

As shown in FIGS. 4A and 5A, the gate electrode 121, the gate line 116, and the data line 117 are formed in the pixel portion of the array substrate 110 made of a transparent insulating material such as glass.

In addition, a data pad line 117p and a gate pad line 116p are formed in each of the data pad portion and the gate pad portion of the array substrate 110.

In this case, the data line 117 according to the first exemplary embodiment of the present invention is formed on the same layer as the gate line 116, and thus is cut at a portion through which the gate line 116 passes and separated for each pixel. It has a structure.

In this case, the gate electrode 121, the gate line 116, the data line 117, the data pad line 117p and the gate pad line 116p deposit a first conductive layer on the entire surface of the array substrate 110. It is formed by selectively patterning through a photolithography process (first mask process).

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), or the like. The same low resistance opaque conductive material can be used. In addition, the first conductive film may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

As the data line 117 according to the first exemplary embodiment of the present invention is formed on the lowermost layer of the same array substrate 110 as the gate line 116, the tail of the active pattern made of an amorphous silicon thin film under the data line 117 is formed. There is no signal interference with the data line 117 due to the tail of the active pattern. For reference, the tail of the active pattern is formed under the data line in the process of forming the active pattern, the source / drain electrode, and the data line by using a diffraction mask in a single mask process, and is smaller than the width of the data line. As a result of having a wide width, signal interference of the data line and a decrease in aperture ratio are caused.

Next, as shown in FIGS. 4B and 5B, an array substrate on which the gate electrode 121, the gate line 116, the data line 117, the data pad line 117p and the gate pad line 116p are formed. A first insulating film 115a, an amorphous silicon thin film, and an n + amorphous silicon thin film are deposited on the entire surface of the 110 and then selectively removed through a photolithography process (a second mask process). The first contact hole 140a and the second contact forming an active pattern 124 made of a silicon thin film and simultaneously exposing portions of the data line 117, the data pad line 117p, and the gate pad line 116p, respectively. The hole 140b and the third contact hole 140c are formed.

In this case, the first contact hole 140a is formed at both ends of the data line 117 separated for each pixel, and a connection line to be formed through a third mask process, which will be described later, opens the first contact hole 140a. By connecting the separated data lines 117 to each other, data signals are transmitted to all pixels.

The n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 remains on the active pattern 124.

Here, the active pattern 124 according to the first embodiment of the present invention is formed in an island shape only on the gate electrode 121 with the first insulating layer 115a therebetween, and the active pattern 124 The first contact hole 140a to the third contact hole 140c may be a mask process using a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask). The second mask process is simultaneously formed. The second mask process will be described in detail with reference to the accompanying drawings.

6A to 6F are cross-sectional views illustrating in detail the second mask process illustrated in FIGS. 4B and 5B.

As shown in FIG. 6A, the gate electrode 121, the gate line 116, the data line 117, the data pad line 117p and the gate pad line 116p are formed on the entire surface of the array substrate 110. 1 The insulating film 115a, the amorphous silicon thin film 120, and the n + amorphous silicon thin film 125 are formed.

6B, after forming a photoresist film 170 made of a photoresist such as photoresist on the entire surface of the array substrate 110, the photoresist film 170 is formed through a half-tone mask 180. Selectively irradiates light.

At this time, the half-tone mask 180 used in the first embodiment of the present invention has a first transmission region (I) for transmitting all of the irradiated light and a second transmission region (II) for transmitting only part of the light and blocking part thereof; A blocking region III for blocking all irradiated light is provided, and only the light passing through the half-tone mask 180 is irradiated to the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the half-tone mask 180 is developed, as shown in FIG. 6C, all of the light passes through the blocking region III and the second transmission region II. The first photoresist pattern 170a and the second photoresist pattern 170b having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the n + amorphous silicon thin film 125 is exposed.

In this case, the first photoresist pattern 170a formed in the blocking region III is thicker than the second photoresist pattern 170b formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use it.

Next, as illustrated in FIG. 6D, the first photoresist film pattern 170a and the second photoresist film pattern 170b formed as described above are used as masks, and the first insulating film 115a and the amorphous silicon thin film formed thereunder are used. When the 120 and the n + amorphous silicon thin film 125 are selectively removed, the first contact hole 140a exposing a part of the data line 117 of the pixel region, the data pad line 117p and the gate pad line A second contact hole 140b and a third contact hole 140c exposing a part of 116p are respectively formed.

Subsequently, when an ashing process of removing portions of the first photoresist pattern 170a and the second photoresist pattern 170b is performed, as illustrated in FIG. 6E, the second transmission region II is formed. The second photosensitive film pattern of is completely removed.

In this case, the first photoresist pattern is a third photoresist pattern 170a 'from which the thickness of the second photoresist pattern is removed and remains only in the active pattern region corresponding to the blocking region III.

Thereafter, as shown in FIG. 6F, the amorphous silicon thin film and the n + amorphous silicon thin film are removed by using the remaining third photoresist pattern 170a ′ as a mask, thereby forming the amorphous silicon on the gate electrode 121. An island-type active pattern 124 formed of a thin film is formed.

In this case, an n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 remains on the active pattern 124.

As such, the active pattern 124 according to the first embodiment of the present invention provides an advantage that the off current of the thin film transistor is reduced as the island pattern is formed only on the gate electrode 124.

Next, as illustrated in FIGS. 4C and 5C, after depositing a second conductive film on the entire surface of the array substrate 110 on which the active pattern 124 is formed, the photolithography process (third mask process) is used. The source electrode 122, the drain electrode 123, and the pixel electrode 118 formed of the second conductive layer are formed in the pixel portion of the array substrate 110 by removing a partial region of the second conductive layer.

The data pad line and the gate pad part of the array substrate 110 may be formed of the second conductive layer through the third mask process, and the data pad line may be formed through the second contact hole and the third contact hole, respectively. A data pad electrode 127p and a gate pad electrode 126p electrically connected to the 117p and the gate pad line 116p are formed.

In addition, the data line part may be formed of the second conductive layer through the third mask process, and may be disposed between the data lines 117 separated by the gate line 116 through the first contact hole 140a. A connection line 127 for connecting is formed.

As such, the source electrode 122, the drain electrode 123, and the connection line 127 are formed of the same second conductive layer as the pixel electrode 118 through the same third mask process.

In this case, a portion of the pixel electrode 118 overlaps a portion of the gate line 116 positioned at the front end with the first insulating layer 115a therebetween to form a storage capacitor Cst.

In addition, in the n + amorphous silicon thin film pattern formed on the active pattern 124, a predetermined region is removed through the third mask process, thereby forming an ohmic − between the active pattern 124 and the source / drain electrodes 122 and 123. An ohmic contact layer 125n to contact is formed.

The second conductive layer may be formed of indium to form the source electrode 122, the drain electrode 123, the connection line 127, the data pad electrode 127p, the gate pad electrode 126p, and the pixel electrode 118. Transparent conductive materials having excellent transmittance, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As shown in FIG. 4D, after forming the second insulating film 115b on the entire surface of the array substrate 110, a part of the second insulating film 115b is formed by using a photolithography process (fourth mask process). Selectively removes the pixel electrode 118 of the pixel to form an open hole H exposing the data pad electrode 127p and a part of the gate pad electrode 126p.

As described above, in the first embodiment of the present invention, the connection line 127 for connecting the source electrode 122, the drain electrode 123, and the separated data line 117 may be formed such as indium tin oxide. As the resistance is formed of a transparent conductive material that is relatively large compared to a low resistance conductive material such as aluminum or molybdenum, signal delay may occur in data signal transmission of the data line 117.

In the liquid crystal display according to the second embodiment of the present invention, the signal delay of the data line can be prevented by forming a source electrode, a drain electrode, and a connection line in a two-layer structure of a transparent conductive layer and a low resistance conductive layer. The liquid crystal display device of the second embodiment and a manufacturing method thereof will be described in detail.

7 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention, in which a source electrode, a drain electrode, and a connection line have a two-layer structure of a transparent conductive layer and a low resistance conductive layer. Except for the above, the structure is the same as that of the array substrate of the first embodiment.

As shown in the figure, a gate line 216 and a data line 217 are formed on the array substrate 210 of the second embodiment to be arranged vertically and horizontally on the array substrate 210 to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed.

Although not shown in the drawing, a gate pad electrode and a data pad electrode electrically connected to the gate line 216 and the data line 217 are formed in an edge region of the array substrate 210. The scan signal and the data signal applied from the driving circuit unit are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit part and are connected to the corresponding gate pad line and the data pad line, respectively, and the gate pad line and the data pad line are the gate pad line and the data pad line. Scan signals and data signals are applied from the driving circuit unit through gate pad electrodes and data pad electrodes electrically connected to the lines, respectively.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the pixel electrode 218. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

In this case, the gate line 216 and the data line 217 according to the second embodiment of the present invention are formed of the same conductive material through the same mask process, and the data line 217 is the gate line 216. ) Is cut at the passing part and has a separated structure.

The data line 217 separated by the gate line 216 is connected to each other through the first contact hole 240a and the connection line 227 formed in the first insulating layer (not shown). In this case, the source electrode 222, the drain electrode 223 and the connection line 227 according to the second embodiment of the present invention is made of a low-resistance conductive material such as molybdenum, and indium-tin-oxide and A source electrode pattern (not shown), a drain electrode pattern (not shown), and a connection line formed of the same transparent conductive material and patterned in the same form as the source electrode 222, the drain electrode 223, and the connection line 227, respectively. A pattern (not shown) is formed.

In this case, the source electrode 222 and a part of the source electrode pattern may form a part of the connection line 227 and the connection line pattern, respectively, and the separated data line 217 through the first contact hole 240a. Electrically connected portions of the drain electrode pattern extend toward the pixel region to form the pixel electrode 218.

As such, the source electrode, the source electrode pattern, the drain electrode, the drain electrode pattern, the connection line, and the connection line pattern are formed through the same mask process of forming the pixel electrode 218, among which the source electrode pattern and the drain electrode. The pattern and the connection line pattern are formed of the same transparent conductive material as the pixel electrode 218.

In addition, the active pattern according to the second embodiment of the present invention is made of an amorphous silicon thin film as in the first embodiment, and is formed in an island shape only on the gate electrode 221, thereby reducing the off current of the thin film transistor. Can be reduced.

In this case, a portion of the gate line 216 positioned at the front end may overlap the portion of the pixel electrode 218 therebetween with the first insulating layer therebetween to form the storage capacitor Cst.

According to the second embodiment of the present invention, the gate line 216 and the data line 217 are simultaneously formed in one mask process, and the pixel electrode 218 and the source electrode 222 are processed in another mask process. By forming the source electrode pattern, the drain electrode 223 and the drain electrode pattern, and the connection line 227 and the connection line pattern at the same time, the array substrate 210 can be manufactured through a total of four mask processes.

In this case, as described above, as the gate line 216 and the data line 217 are formed at the same time, the data line 217 of the present invention has a structure separated from the gate line 216 by passing. According to the second embodiment of the present invention, when the pixel electrode 218 is formed, the separated data lines 217 are connected to each other by using the connection line 227 and the connection line pattern. It will be described in detail through the manufacturing method.

8A through 8D are cross-sectional views sequentially illustrating a manufacturing process along line VII-VII ′ of the array substrate illustrated in FIG. 7, illustrating a process of manufacturing an array substrate of a pixel portion including a data line portion on the left side and a turn on the right side. As a result, a process of manufacturing an array substrate of a data pad unit and a gate pad unit is shown.

9A to 9D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 7.

As shown in FIGS. 8A and 9A, the gate electrode 221, the gate line 216, and the data line 217 are formed in the pixel portion of the array substrate 210 made of a transparent insulating material such as glass.

In addition, a data pad line 217p and a gate pad line 216p are formed in each of the data pad portion and the gate pad portion of the array substrate 210.

In this case, the data line 217 according to the second exemplary embodiment of the present invention is formed on the same layer as the gate line 216. Thus, the data line 217 is cut at a portion through which the gate line 216 passes and separated for each pixel. It has a structure.

In this case, the gate electrode 221, the gate line 216, the data line 217, the data pad line 217p and the gate pad line 216p are deposited on the entire surface of the array substrate 210 after the first conductive layer is deposited. It is formed by selectively patterning through a photolithography process (first mask process).

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), or the like. The same low resistance opaque conductive material can be used. In addition, the first conductive film may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

As in the first embodiment described above, the data line 217 according to the second embodiment of the present invention is formed in the lowermost layer of the same array substrate 210 as the gate line 216, so that an amorphous silicon thin film is formed under the same. Since the tail of the active pattern is not present, there is no signal interference of the data line 217 by the tail of the active pattern.

Next, as shown in FIGS. 8B and 9B, an array substrate on which the gate electrode 221, the gate line 216, the data line 217, the data pad line 217p and the gate pad line 216p are formed. A first insulating film 215a, an amorphous silicon thin film, and an n + amorphous silicon thin film are deposited on the entire surface of the 210, and then selectively removed through a photolithography process (second mask process). The first contact hole 240a and the second contact forming an active pattern 224 made of a silicon thin film and simultaneously exposing portions of the data line 217, the data pad line 217p, and the gate pad line 216p, respectively. The hole 240b and the third contact hole 240c are formed.

In this case, the first contact hole 240a may be formed at both ends of the data line 217 separated for each pixel, and the first contact hole may include a connection line and a connection line pattern to be formed through a third mask process to be described later. By connecting the data lines 217 separated through the 240a to each other, the data signals are transmitted to all the pixels.

The n + amorphous silicon thin film pattern 225 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 224 remains on the active pattern 224.

The active pattern 224 according to the second embodiment of the present invention is formed in an island shape only on the gate electrode 221 with the first insulating layer 215a therebetween as in the first embodiment described above. The active pattern 224 and the first contact hole 240a to the third contact hole 240c are simultaneously formed in one mask process (second mask process) using a half-tone mask.

Next, as shown in FIGS. 8C and 9C, after the second conductive film and the third conductive film are deposited on the entire surface of the array substrate 210 on which the active pattern 224 is formed, a photolithography process (third mask process) is performed. A source electrode 222, a drain electrode 223, and a pixel electrode formed of the third conductive film in the pixel portion of the array substrate 210 by removing partial regions of the second conductive film and the third conductive film using the? A source electrode pattern 222 ', a drain electrode pattern 223', and a pixel electrode pattern 218 'formed of the second conductive film are formed at the same time as the second conductive film 218 is formed.

In addition, the data pad portion and the gate pad portion of the array substrate 210 may be formed of the second conductive layer through the third mask process, and the data pad line may be formed through the second contact hole and the third contact hole, respectively. A data pad electrode 227p and a gate pad electrode 226p electrically connected to the 217p and the gate pad line 216p are formed.

In this case, the data pad electrode 227p and the gate pad electrode 226p are formed of the third conductive layer and patterned in the same form as the data pad electrode 227p and the gate pad electrode 226p, respectively. The pattern 227p 'and the gate pad electrode pattern 226p' are formed.

In addition, the data line part includes the second conductive layer and the third conductive layer through the third mask process, respectively, and is separated by the gate line 216 through the first contact hole 240a. A connection line pattern 227 ′ and a connection line 227 are formed to connect the 217 to each other.

In addition, in the n + amorphous silicon thin film pattern formed on the active pattern 224, a predetermined region is removed through the third mask process to form an ohmic − between the active pattern 224 and the source / drain electrodes 222 and 223. The ohmic contact layer 225n to contact is formed.

The second conductive layer may include the source electrode pattern 222 ', the drain electrode pattern 223', the connection line pattern 227 ', the data pad electrode 227p, the gate pad electrode 226p, and the pixel electrode 218. And a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide.

In addition, the third conductive layer may include a low resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, chromium, molybdenum or molybdenum alloy to form the source electrode 222, the drain electrode 223, and the connection line 227. Contains substances.

As described above, according to the second embodiment of the present invention, the source electrode pattern 222 ′, the drain electrode pattern 223 ′, and the connection line pattern 227 ′ formed of a transparent conductive material are respectively formed as a low resistance opaque conductive material. The signal delay of the data line 217 can be prevented by forming the 222, the drain electrode 223, and the connection line 227.

In this case, as described above, the pixel electrode pattern 218 ′ and the data pad electrode formed of the opaque third conductive layer are respectively disposed on the pixel electrode 218, the data pad electrode 227p, and the gate pad electrode 226p. The pattern 227p 'and the gate pad electrode pattern 226p' remain.

Accordingly, as shown in FIGS. 8D and 9D, the second insulating film 215b is formed on the entire surface of the array substrate 210, and then the second insulating film ( A portion of 215b, the pixel electrode pattern, the data pad electrode pattern, and the gate pad electrode pattern are selectively removed to expose the pixel electrode 218 of the pixel, and the data pad electrode 227p and the gate pad electrode 226p. Open holes (H) to expose a portion of the.

In this case, a portion of the pixel electrode 218 overlaps a portion of the gate line 216 disposed at the front end with the first insulating layer 215a therebetween to form a storage capacitor Cst.

The array substrates of the first and second embodiments configured as described above are bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor, the gate line, and the data are attached to the color filter substrate. A black matrix is formed to prevent light leaking into the lines, and a color filter is formed to realize red, green, and blue colors.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

In the first and second embodiments, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern is described as an example, but the present invention is not limited thereto, and the present invention is not limited thereto. The same applies to the polysilicon thin film transistors used.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

4A to 4D are cross-sectional views sequentially illustrating a manufacturing process along line III-III ′ of the array substrate illustrated in FIG. 3.

5A to 5C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

6A to 6F are cross-sectional views specifically showing the second mask process shown in FIGS. 4B and 5B.

7 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

8A to 8D are cross-sectional views sequentially illustrating a manufacturing process along line VII-VII ′ of the array substrate illustrated in FIG. 7.

9A to 9D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 7.

** Explanation of symbols for main parts of drawings **

110,210: array substrate 116,216: gate line

117,217 data line 118,218 pixel electrode

121,221 gate electrode 122,222 source electrode

123,223 Drain electrode 124,224 Active pattern

127,227: connecting line

Claims (11)

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line on the pixel portion of the first substrate through a first mask process; Defining a pixel area crossing the gate line by using the first mask process, and forming a data line which is cut at a portion where the gate line passes and is separated from each pixel area; Forming a first insulating film on the first substrate; Forming an island-type active pattern with the first insulating layer interposed on the gate electrode through a second mask process, and forming an n + amorphous silicon thin film pattern on the active pattern; Removing a partial region of the first insulating layer using the second mask process to form a first contact hole exposing portions of both ends of the separated data line; Forming a source electrode, a drain electrode, and a pixel electrode in a pixel portion of the first substrate through a third mask process, and forming a connection line connecting the separated data lines to each other through the first contact hole; Forming a second insulating film on the first substrate; Removing a portion of the second insulating layer through a fourth mask process to expose a portion of the pixel electrode, the data pad electrode, and the gate pad electrode; And And attaching the first substrate and the second substrate to each other. The method of claim 1, further comprising forming a data pad line on the data pad portion of the first substrate using the first mask process, and forming a gate line on the gate pad portion of the first substrate. Method of manufacturing a liquid crystal display device, characterized in that. The method of claim 2, wherein a portion of the first insulating layer is removed by using the second mask process to form a second contact hole exposing a portion of the data pad line, and exposing a portion of the gate pad line. A method for manufacturing a liquid crystal display device, further comprising the step of forming a third contact hole. The method of claim 3, wherein a data pad electrode is formed to be electrically connected to the data pad line through the second contact hole using the third mask process, and is electrically connected to the gate pad line through the third contact hole. And forming a gate pad electrode to be connected with each other. 2. The source electrode pattern, the drain electrode pattern, and the connection line of claim 1, wherein the source electrode pattern, the drain electrode, and the connection line are respectively patterned under the source electrode, the drain electrode, and the connection line through the third mask process. The method of manufacturing a liquid crystal display device, further comprising the step of forming a pattern. The method of claim 1, further comprising forming an ohmic contact layer to ohmic-contact between the active pattern and the source / drain electrodes by removing a portion of the n + amorphous silicon thin film pattern using the third mask process. Method of manufacturing a liquid crystal display device comprising a. A gate electrode and a gate line formed of a first conductive film on the first substrate; A data line formed of the first conductive layer and formed to be cut at a portion through which the gate line passes and separated from each pixel area; A first insulating film formed on the first substrate; An active pattern formed in an island shape with the first insulating film interposed on the gate electrode; A source electrode and a drain electrode formed of a second conductive film on the first substrate; A connection line formed of the second conductive layer and connecting the separated data lines to each other through a contact hole formed by removing a portion of the first insulating layer; A pixel electrode formed of a third conductive film in the pixel region; A second insulating layer formed on the first substrate and exposing the pixel electrode; And And a second substrate bonded to and opposed to the first substrate. 8. The liquid crystal display device according to claim 7, wherein the second conductive film and the third conductive film are made of substantially the same conductive material. 8. The source electrode pattern, the drain electrode pattern and the connection of claim 7, wherein the source electrode, the drain electrode, and the connection line are formed of the third conductive layer, respectively. Liquid crystal display further comprising a line pattern. 10. The liquid crystal display device according to claim 9, wherein the second conductive film is made of a low resistance opaque conductive material, and the third conductive film is made of a transparent conductive material. 8. The liquid crystal display device of claim 7, further comprising an ohmic contact layer formed on the active pattern to ohmic contact between the active pattern and the source / drain electrodes.

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