KR20100084205A - Organic light emitting display device - Google Patents

Abstract

PURPOSE: An organic light emitting displaying device is provided to minimize the effect of IR-drop which is proportionally increased to the area of a panel by widening the area of a Bus electrode. CONSTITUTION: Transistors are formed in a first substrate. Sub-pixels are formed in a second substrate. A spacer(125) is formed in the sub-pixels, and upper electrodes, which are included in the sub-pixels, are protruded to electrically connect with a source electrode or a drain electrode. The sub-pixels include a bank layer and Bus electrode(122). The bank layer defines the opening areas of the sub-pixels. The Bus electrodes are located on the lower side of the bank layer and are adjacent to the boundary of the opening area.

Description

Organic Light Emitting Display Device

Embodiments of the present invention relate to an organic light emitting display device.

The organic light emitting display device used in the organic light emitting display device is a self-light emitting device having a light emitting layer formed between two electrodes positioned on a substrate.

The organic light emitting display includes a top emission type, a bottom emission type, or a dual emission type according to a direction in which light is emitted. According to the driving method, it is divided into a passive matrix type and an active matrix type.

In the organic light emitting display device, when a scan signal, a data signal, and a power are supplied to a plurality of subpixels arranged in a matrix form, the selected subpixels emit light to display an image.

Some conventional organic light emitting display devices have a structure in which a transistor and an organic light emitting diode are formed on a first substrate and a second substrate, and the first substrate and the second substrate are adhesively sealed with an adhesive member. Such a structure uses spacers for electrical connection between a transistor formed on the first substrate and an organic light emitting diode positioned on the second substrate.

On the other hand, the organic light emitting display device formed by separating the elements into the first substrate and the second substrate as described above needs to be improved because the display quality should be improved while reducing the resistance of the electrode to which power is supplied.

Embodiments of the present invention to solve the above-mentioned problems of the background art provide an organic light emitting display device that can satisfy display quality and reliability when manufacturing a large area display device by improving luminance and reducing power consumption.

Embodiments of the present invention as a means for solving the above problems, the first substrate formed with transistors; A second substrate on which sub pixels are formed; And spacers formed in the subpixels and protruding so that the upper electrodes included in the subpixels are electrically connected to the source electrode or the drain electrode of the transistors, wherein the subpixels include: a bank layer defining opening regions of the subpixels; The present invention provides an organic light emitting display device including bus electrodes disposed under a bank layer and adjacent to boundary lines of an opening area.

In the bus electrodes, regions corresponding to the spacers may be removed.

The subpixels may have wider opening regions of the blue subpixels than the opening regions of the green and red subpixels.

The subpixels may have the same opening regions of the green and red subpixels.

The spacers included in the blue subpixels among the spacers may be positioned at the center of one side of the blue subpixels, and the spacers included in the green and red subpixels of the spacers may be positioned at the left and right sides of the green and red subpixels, respectively. .

The subpixels may include lower electrodes formed on the second substrate, the bus electrodes formed on the lower electrodes, a bank layer formed on the lower electrodes and exposing a portion of the lower electrodes, and formed on the bank layer. And partition walls defining regions of the sub pixels, organic light emitting layers formed on the lower electrodes, and upper electrodes formed on the organic light emitting layers, and the upper electrodes are formed for each sub pixel by the partition walls. Can be.

Spacers may be formed on the bank layer to adjoin the partition walls.

The partitions may have a larger top area than the bottom area.

The transistors may include contact electrodes disposed on the transistors and connected to source or drain electrodes of the transistors, and upper electrodes formed on the spacers may contact the contact electrodes, respectively.

The spacers may be narrower in top area than bottom area.

Embodiments of the present invention have an effect of providing an organic light emitting display device that can satisfy display quality and reliability when manufacturing a large area display device by improving luminance and reducing power consumption.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is a schematic plan view of an organic light emitting display device according to an embodiment of the present invention.

As shown in FIG. 1, an organic light emitting display device according to an exemplary embodiment of the present invention may include panels 110 and 140 having a display area AA and a non-display area NA. The panels 110 and 140 face the first substrate 110 and the first substrate 110 on which the transistors and the power electrodes are formed, and the second substrate 140 on which the subpixels are formed in the display area AA is attached to the adhesive member. By sealing.

The first substrate 110 may be formed of a light transmissive or non-transparent material, and the second substrate 140 may be formed of a light transmissive material. Materials of the first and second substrates 110 and 140 include glass, metal, ceramic, or plastic (polycarbonate resin, acrylic resin, vinyl chloride resin, polyethylene terephthalate resin, polyimide resin, polyester resin, epoxy resin, Silicone resins, fluorocarbon resins, and the like).

The driving unit 160 and the pad unit 170 for supplying driving signals to the panels 110 and 140 may be positioned on the first substrate 110. The driver 160 may include a data driver and a scan driver for supplying a data signal and a scan signal to elements formed in the panels 110 and 140. The data driver may receive a horizontal synchronization signal and an image data signal from an external source and generate a data signal by referring to the horizontal synchronization signal. The scan driver may receive a vertical synchronization signal from the outside and generate a scan signal and a control signal with reference to the vertical synchronization signal. The data driver and the scan driver included in the driver 160 may be separately located on the first substrate 110. The pad unit 170 is connected to an external circuit board to transmit various signals supplied from the outside to the driver 160 and the panels 110 and 140.

Hereinafter, the circuit configuration of the subpixel will be described.

2 is an exemplary circuit configuration of a subpixel.

Referring to FIG. 2, the subpixel may include a switching transistor S1, a first capacitor Cbst, a second capacitor Cst, a driving transistor T1, and an organic light emitting diode D.

In the switching transistor S1, a gate electrode is connected to the scan line SCAN, and one end thereof is connected to the data line DATA. One end of the first capacitor Cbst is connected to the other end of the switching transistor S1 and the other end thereof is connected to the first node A. One end of the second capacitor Cst is connected to the first node A, and the other end thereof is connected to the third node C and the second power line VSS. The driving transistor T1 has a gate electrode connected to the first node A, one end connected to the second node B, and the other end connected to the third node C and the second power line VSS. In the organic light emitting diode D, an anode is connected to the first power line VDD, and a cathode is connected to the second node B.

In the organic light emitting display device according to an exemplary embodiment of the present invention, the switching transistor S1, the driving transistor T1, the first capacitor Cbst, the second capacitor Cst, and the like included in the subpixel include the first substrate 110. ) May be formed on the second substrate 140, and the organic light emitting diode D may be formed on the second substrate 140. In some cases, the first capacitor Cbst may be omitted.

The panel 110 and 140 having such a subpixel structure, when a data signal and a scan signal are supplied from the data driver and the scan port, the cathode of the organic light emitting diode D and the source electrode or drain electrode of the driving transistor T1. As the driving current flows through the second node B connecting the organic light emitting diode D to emit light, the image can be expressed.

Hereinafter, the subpixel formed in the panel will be described.

3 is a plan view of a sub-pixel.

Referring to FIG. 3, a blue subpixel SP1, a green subpixel SP2 and a red subpixel SP3 are formed in a matrix in the panel. The subpixels SP1, SP2, and SP3 formed in the panel have a wider opening area OPN of the blue subpixels SP1 than the opening areas OPN of the green and red subpixels SP2 and SP3. Can be formed. The openings OPN of the green and red subpixels SP2 and SP3 may be formed in the same manner. When the subpixels SP1, SP2, and SP3 are formed in this manner, the influence may be minimized due to the difference in luminous efficiency caused by the organic light emitting material included in the blue, green, and red subpixels SP1, SP2, and SP3. It is not limited to this.

The subpixels SP1, SP2, and SP3 formed in the panel are defined by the partitions 124, and the cathode of the organic light emitting diode is formed by the spacers 125 formed in the subpixels SP1, SP2, and SP3. And a source electrode or a drain electrode of the driving transistor are connected. The spacers included in the blue subpixels among the spacers 125 may be positioned at the center of one side of the blue subpixels SP1, and the spacers included in the green and red subpixels SP2 and SP3 may be green and red. The left and right sides of the subpixels SP2 and SP3 may be positioned.

Bus electrodes 122 are formed in regions adjacent to boundary lines of the opening regions OPN of the subpixels SP1, SP2, and SP3. The bus electrodes 122 are used as auxiliary electrodes for reducing the resistance of the lower electrode electrically connected to the first power supply line VDD as an electrode for minimizing a current drop caused by a resistance. These bus electrodes 122 are formed on the lower front surface of the bank layer defining the opening regions OPN, or as shown, except for the region formed on the lower front surface of the bank layer and corresponding to the spacers 125. It can be formed to occupy all areas.

Hereinafter, the structure of the subpixel will be described in more detail with reference to FIG. 4.

4 and 5 are cross-sectional views of the subpixel illustrated in FIG. 3, and FIG. 6 is a structural diagram of the organic light emitting layer. In FIG. 4, the bus electrodes 122 are formed on the lower front surface of the bank layer defining the opening area OPN. In FIG. 5, the bus electrodes 122 define the opening area OPN. It is shown that is formed on the lower front surface of the bank layer and occupies all regions except the region corresponding to the spacer 125.

4 and 5, a gate electrode 102 may be formed on the first substrate 110. The gate electrode 102 is a gate electrode metal of a transistor formed on the first substrate 110. The gate electrode 102 is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be made of any one or alloys thereof. In addition, the gate electrode 102 is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multilayer formed of any one or an alloy thereof. In addition, the gate electrode 102 may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The first insulating layer 103 may be positioned on the gate electrode 102. The first insulating layer 103 may be, but is not limited to, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof.

The active layer 104 may be positioned on the first insulating layer 103. The active layer 104 may include amorphous silicon or polycrystalline silicon crystallized therefrom. Although not shown, the active layer 104 may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with P-type or N-type impurities. In addition, the active layer 104 may include an ohmic contact layer to lower the contact resistance.

The source electrode 105 and the drain electrode 106 may be positioned on the active layer 104. One of the source electrode 105 and the drain electrode 106 may be disposed to face the lower electrode of the capacitor formed on the first substrate 110 to form a capacitor. The source electrode 105 and the drain electrode 106 may be formed of a single layer or multiple layers. When the source electrode 105 and the drain electrode 106 have a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and It may be made of any one or an alloy thereof selected from the group consisting of copper (Cu). On the other hand, when the source electrode 105 and the drain electrode 106 are multiple layers, the double layer of molybdenum / aluminum-neodymium and the triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

The second insulating layer 107 may be positioned on the source electrode 105 and the drain electrode 106. The second insulating layer 107 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating film 107 may be a passivation film or a planarization film.

The contact electrode 109 connected to the source electrode 105 or the drain electrode 106 of the transistor may be positioned on the second insulating layer 107.

As described above, the transistor positioned on the first substrate 110 is a batam gate electrode type. However, the transistor located on the first substrate 110 is not limited thereto and may also be formed as a top gate type.

The lower electrode 121 may be positioned on the second substrate 140. The lower electrode 121 receives power from the first power line VDD. The lower electrode 121 may be selected as an anode, and the lower electrode 121 selected as an anode may be indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or AZO (ZnO doped Al2O3). ) May be formed of any one, but is not limited thereto.

The bus electrode 122 may be positioned on the lower electrode 121. The bus electrode 122 is formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Can be done. The bus electrode 122 serves as an auxiliary electrode of the lower electrode 121.

Bank layers 123a and 123b may be positioned on the lower electrode 121 and the bus electrode 122. The bank layers 123a and 123b may have an opening area OPN exposing a portion of the lower electrode 121. The bank layers 123a and 123b may include an organic material such as benzocyclobutene (BCB) resin, acrylic resin, or polyimide resin.

On the bank layers 123a and 123b, barrier ribs 124 defining regions of sub-pixels may be located. The partition wall 124 may then be formed to provide process convenience when forming the organic light emitting layer and the upper electrode, which may be formed in an inverted taper shape with a narrower base area than the top area.

The spacer 125 may be positioned on the bank layer 123b to be adjacent to the partition wall 124. The spacer 125 may have a smaller top area than the bottom area. The spacer 125 may be formed of an organic material, an inorganic material, or an organic / inorganic composite, but is not limited thereto.

The organic emission layer 127 may be positioned on the lower electrode 121 exposed through the openings of the bank layers 123a and 123b. The organic light emitting layer 127 may be formed by being divided into regions of the subpixels by the partition 124.

Referring to FIG. 6, the organic light emitting layer 127 may include a hole injection layer 127a, a hole transport layer 127b, a light emitting layer 127c, an electron transport layer 127d, and an electron injection layer 127e.

The hole injection layer 127a may play a role of smoothly injecting holes. CuPc (cupper phthalocyanine), PEDOT (poly (3,4) -ethylenedioxythiophene), PANI (polyaniline), and NPD (N, N-dinaphthyl) -N, N'-diphenyl benzidine) may be composed of any one or more selected from the group consisting of, but is not limited thereto.

The hole transport layer 127b serves to facilitate the transport of holes, NPD (N, N-dinaphthyl-N, N'-diphenyl benzidine), TPD (N, N'-bis- (3-methylphenyl) -N , N'-bis- (phenyl) -benzidine), s-TAD and MTDATA (4,4 ', 4 "-Tris (N-3-methylphenyl-N-phenyl-amino) -triphenylamine) It may be made of one or more, but is not limited thereto.

The emission layer 127c may include materials emitting red, green, blue, and white light and may be formed using phosphorescent or fluorescent materials.

When the light emitting layer 127c is red, it includes a host material including CBP (carbazole biphenyl) or mCP (1,3-bis (carbazol-9-yl), and PIQIr (acac) (bis (1-phenylisoquinoline) acetylacetonate Phosphorescent light containing a dopant including any one or more selected from the group consisting of iridium), PQIr (acac) (bis (1-phenylquinoline) acetylacetonate iridium), PQIr (tris (1-phenylquinoline) iridium) and PtOEP (octaethylporphyrin platinum) It may be made of a material, alternatively may be made of a fluorescent material including PBD: Eu (DBM) 3 (Phen) or perylene, but is not limited thereto.

When the light emitting layer 127c is green, it may include a host material including CBP or mCP, and may be made of a phosphor including a dopant material including Ir (ppy) 3 (fac tris (2-phenylpyridine) iridium). And, alternatively, it may be made of a fluorescent material including Alq3 (tris (8-hydroxyquinolino) aluminum), but is not limited thereto.

When the light emitting layer 127c is blue, the light emitting layer 127c may include a host material including CBP or mCP and may be formed of a phosphor including a dopant material including (4,6-F2ppy) 2Irpic. Alternatively, it may be made of a fluorescent material including any one selected from the group consisting of spiro-DPVBi, spiro-6P, distilbenzene (DSB), distriarylene (DSA), PFO-based polymer and PPV-based polymer, but It is not limited.

The electron transport layer 127d serves to facilitate electron transport, and may be made of any one or more selected from the group consisting of Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq, and SAlq. However, the present invention is not limited thereto.

The electron injection layer 127e serves to facilitate the injection of electrons, and may be Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq or SAlq, but is not limited thereto.

Herein, the present invention is not limited to FIG. 6, and at least one of the hole injection layer 127a, the hole transport layer 127b, the electron transport layer 127d, and the electron injection layer 127e may be omitted.

The upper electrode 128 may be positioned on the organic emission layer 127. The upper electrode 128 may be selected as a cathode, and the upper electrode 128 selected as the cathode may use an opaque and highly reflective material such as aluminum (Al). The upper electrode 128 may be positioned to cover the top of the organic emission layer 127 and the surface of the spacer 125 by the partition 124. The upper electrode 128 formed to cover the surface of the spacer 125 is in contact with the contact electrode 109 as the first substrate 110 and the second substrate 140 are vacuum-bonded.

Hereinafter, the structure of the bus electrode according to the comparative example and the embodiment will be described with reference to FIG. 7.

7 is a view for explaining the structure of the bus electrode according to the comparative example and the embodiment.

(A) of FIG. 7 shows a comparative example, and (b) shows an Example.

According to the experiment, the comparative example of (a) and the example of (b) showed no significant difference in terms of power consumption and luminance in terms of IR drop when the display device was manufactured with a small panel as a target. However, when the size of the panel was gradually produced as a large target, the comparative example of (a) and the example of (b) showed a large difference in terms of power consumption and luminance in terms of IR drop. As a result, it can be seen that the comparative example of (a) and the embodiment of (b) can exhibit the above difference in terms of power consumption and luminance in proportion to the area occupied by the bus electrode 122.

Therefore, as the area of the bus electrode 122 is increased, the influence of IR drop that is increased in proportion to the panel area when the power supplied from the first power line VDD is transferred to the lower electrode can be minimized.

Embodiments of the present invention have the effect of providing a large area organic light emitting display device capable of minimizing the effects of IR Drop by increasing the area of the bus electrode. In addition, the embodiment of the present invention has the effect of providing an organic light emitting display device that can improve the display quality and reliability by improving the brightness and power consumption.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is a schematic plan view of an organic light emitting display device according to an embodiment of the present invention;

2 is an exemplary circuit configuration of a subpixel.

3 is a plan view of a subpixel;

4 and 5 are cross-sectional views of the subpixel shown in FIG.

6 is a structural diagram of an organic light emitting layer.

7 is a view for explaining the structure of a bus electrode according to a comparative example and an embodiment.

<Explanation of symbols on main parts of the drawings>

110: first substrate 103: first insulating film

104: active layer 105: source electrode

106: drain electrode 107: second insulating film

121: lower electrode 122: bus electrode

124: partition 125: spacer

127: organic light emitting layer 128: upper electrode

140: second substrate

Claims (10)

A first substrate on which transistors are formed; A second substrate on which sub pixels are formed; And And spacers formed in the subpixels and protruding so that upper electrodes included in the subpixels are electrically connected to a source electrode or a drain electrode of the transistors, The subpixels, A bank layer defining opening regions of the subpixels; And a bus electrode disposed under the bank layer and adjacent to boundary lines of the opening regions. The method of claim 1, The bus electrodes, And an area corresponding to the spacers is removed. The method of claim 1, The subpixels, An organic light emitting display device, wherein the openings of the blue subpixels are wider than the openings of the green and red subpixels. The method of claim 1, The subpixels, An organic light emitting display device, wherein the openings of the green and red subpixels are formed in the same manner. The method of claim 1, Spacers included in the blue subpixels of the spacers are located at the center of one side of the blue subpixels, The spacers included in the green and red subpixels of the spacers are positioned at left and right sides of the green and red subpixels, respectively. The method of claim 1, The subpixels, Lower electrodes formed on the second substrate; The bus electrodes formed on the lower electrodes; The bank layer formed on the lower electrodes and exposing a portion of the lower electrodes; Barrier ribs formed on the bank layer and defining regions of the subpixels; Organic emission layers formed on the lower electrodes; The upper electrodes formed on the organic emission layers, The upper electrodes, The organic light emitting display device of claim 1, wherein the barrier ribs are formed in the sub-pixels. The method of claim 6, The spacers, And an organic light emitting display device disposed on the bank layer to be adjacent to the partition walls. The method of claim 6, The partitions, An organic light emitting display device, characterized in that the upper area is larger than the bottom area. The method of claim 1, The transistors include contact electrodes disposed on the transistors and connected to source or drain electrodes of the transistors, And the upper electrodes formed on the spacers contact the contact electrodes, respectively. The method of claim 1, The spacers, An organic light emitting display device, characterized in that the upper area is narrower than the bottom area.

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