KR20100067388A - Organic light emitting display device - Google Patents

Abstract

Embodiments of the present invention include a first substrate on which a transistor is formed; A second substrate on which subpixels are formed; Barrier ribs formed around the subpixel to define an area of the subpixel; The present invention provides an organic light emitting display device including a spacer formed in a subpixel and surrounding at least one surface of the subpixel and protruding so that an upper electrode included in the subpixel is electrically connected to a source or a drain of the transistor.

Description

Organic Light Emitting Display Device

Embodiments of the present invention relate to an organic light emitting display device.

An organic light emitting display device used in an organic light emitting display device is a self-light emitting device having a light emitting layer formed between two electrodes positioned on a substrate.

The organic light emitting display includes a top emission type, a bottom emission type, or a dual emission type according to a direction in which light is emitted. According to the driving method, it is divided into a passive matrix type and an active matrix type.

In the organic light emitting display device, when a scan signal, a data signal, and a power are supplied to a plurality of subpixels arranged in a matrix form, the selected subpixels emit light to display an image.

Some conventional organic light emitting display devices have a structure in which a transistor and an organic light emitting diode are formed on a first substrate and a second substrate, and the first substrate and the second substrate are adhesively sealed with an adhesive member. Such a structure uses spacers for electrical connection between a transistor formed on the first substrate and an organic light emitting diode positioned on the second substrate.

On the other hand, the organic light emitting display device formed by separating the device into the first substrate and the second substrate as described above, there is a need to continue the research to improve the durability of the panel and the electrical contact between the electrode using the spacer.

Embodiments of the present invention for solving the above-described problems of the background art provide an organic light emitting display device that can enhance durability of a panel so as to absorb or withstand an impact. In addition, an embodiment of the present invention to provide an organic light emitting display device that can lower the resistance by improving the contact structure between the electrodes.

Embodiments of the present invention by means of the above-mentioned problem solving means, the first substrate with a transistor formed; A second substrate on which subpixels are formed; Barrier ribs formed around the subpixel to define an area of the subpixel; The present invention provides an organic light emitting display device including a spacer formed in a subpixel and surrounding at least one surface of the subpixel and protruding so that an upper electrode included in the subpixel is electrically connected to a source or a drain of the transistor.

The spacer may be formed to surround the entire surface of the subpixel.

The spacer may be formed to surround three surfaces of the subpixel.

The transistor includes a contact electrode disposed on the transistor and connected to a source or a drain of the transistor, and the contact electrode may be formed such that the upper electrode formed on the spacer is in surface contact.

The spacer may include a first spacer positioned at one side of the sub pixel and protruding in a columnar shape, and a second spacer protruding in contact with the first spacer and surrounding at least one surface of the sub pixel.

The subpixel includes a lower electrode formed on the second substrate, a bank layer formed on the lower electrode and exposing a portion of the lower electrode, an organic emission layer formed on the lower electrode, and an upper electrode formed on the organic emission layer. The upper electrode may be formed to be divided for each sub pixel by the partition wall.

The partition wall may be formed on the bank layer.

The spacer may be formed on the bank layer so as to be adjacent to the partition wall.

Embodiment of the present invention, there is an effect to provide an organic light emitting display device that can enhance the durability of the panel to absorb or withstand the impact. In addition, the embodiment of the present invention has an effect of providing an organic light emitting display device that can lower the contact resistance by improving the contact structure between the electrodes.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is a schematic plan view of an organic light emitting display device according to an embodiment of the present invention.

As shown in FIG. 1, an organic light emitting display device according to an exemplary embodiment of the present invention may include panels 110 and 140 having a display area AA and a non-display area NA. The panels 110 and 140 face the first substrate 110 and the first substrate 110 on which the transistors and the power electrodes are formed, and the second substrate 140 on which the subpixels are formed in the display area AA is attached to the adhesive member. By sealing.

The first substrate 110 may be formed of a light transmissive or non-transparent material, and the second substrate 140 may be formed of a light transmissive material. Materials of the first and second substrates 110 and 140 include glass, metal, ceramic, or plastic (polycarbonate resin, acrylic resin, vinyl chloride resin, polyethylene terephthalate resin, polyimide resin, polyester resin, epoxy resin, Silicone resins, fluorocarbon resins, and the like).

The driving unit 160 and the pad unit 170 for supplying driving signals to the panels 110 and 140 may be positioned on the first substrate 110. The driver 160 may include a data driver and a scan driver for supplying a data signal and a scan signal to elements disposed on the panels 110 and 140. The data driver may receive a horizontal synchronization signal and an image data signal from an external source and generate a data signal by referring to the horizontal synchronization signal. The scan driver may receive a vertical synchronization signal from the outside and generate a scan signal and a control signal with reference to the vertical synchronization signal. The data driver and the scan driver included in the driver 160 may be separately located on the first substrate 110. The pad unit 170 is connected to an external circuit board to transmit various signals supplied from the outside to the driver 160 and the panels 110 and 140.

Hereinafter, the circuit configuration of the subpixel will be described.

2 is an exemplary circuit configuration of a subpixel.

Referring to FIG. 2, the subpixel may include a switching transistor S1, a first capacitor Cbst, a second capacitor Cst, a driving transistor T1, and an organic light emitting diode D.

The switching transistor S1 has a gate connected to the scan line SCAN and one end connected to the data line DATA. One end of the first capacitor Cbst is connected to the other end of the switching transistor S1 and the other end thereof is connected to the first node A. One end of the second capacitor Cst is connected to the first node A, and the other end thereof is connected to the third node C and the second power line VSS. The driving transistor T1 has a gate connected to the first node A, one end connected to the second node B, and the other end connected to the third node C and the second power line VSS. In the organic light emitting diode D, an anode is connected to the first power line VDD, and a cathode is connected to the second node B.

In the organic light emitting display device according to an exemplary embodiment of the present invention, the switching transistor S1, the driving transistor T1, the first capacitor Cbst, the second capacitor Cst, and the like included in the subpixel include the first substrate 110. ) May be formed on the second substrate 140, and the organic light emitting diode D may be formed on the second substrate 140. In some cases, the first capacitor Cbst may be omitted.

The panel 110 and 140 having such a subpixel structure may connect the cathode of the organic light emitting diode D to the source or drain of the driving transistor T1 when a data signal and a scan signal are supplied from the data driver and the scan driver. As the driving current flows through the second node B, the organic light emitting diode D emits light, thereby displaying an image.

Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described in more detail with reference to a cross-sectional view of the panel.

3 is a cross-sectional view of a panel according to an embodiment of the present invention, Figure 4 is a structural diagram of an organic light emitting layer.

Referring to FIG. 3, a first gate 102a positioned in the display area AA and a second gate 102b positioned in the non-display area NA may be formed on the first substrate 110. The first gate 102a may be a gate metal of a transistor formed on the first substrate 110, and the second gate 102b may be a gate metal connected to a power line formed on the first substrate 110. In addition, the gate metal constituting the lower electrode of the capacitor may be further positioned on the first substrate 110. The first gate 102a and the second gate 102b include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper. It may be made of any one or an alloy thereof selected from the group consisting of (Cu). In addition, the first gate 102a and the second gate 102b include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). And it may be a multilayer consisting of any one or an alloy thereof selected from the group consisting of copper (Cu). In addition, the first gate 102a and the second gate 102b may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The first insulating layer 103 may be positioned on the first gate 102a and the second gate 102b. The first insulating layer 103 may be, but is not limited to, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof.

The active layer 104 may be positioned on the first insulating layer 103. The active layer 104 may include amorphous silicon or polycrystalline silicon crystallized therefrom. Although not shown, the active layer 104 may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with P-type or N-type impurities. In addition, the active layer 104 may include an ohmic contact layer to lower the contact resistance.

The source 105 and the drain 106 may be positioned on the active layer 104. One of the source 105 and the drain 106 may be disposed to face the lower electrode of the capacitor formed on the first substrate 110 to constitute the capacitor. The source 105 and the drain 106 may consist of a single layer or multiple layers. Molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (if the source 105 and drain 106 are single layers) Cu) may be made of any one or an alloy thereof selected from the group consisting of. Alternatively, when the source 105 and the drain 106 are multiple layers, they may be made of a double layer of molybdenum / aluminum-neodymium, or a triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum.

The second insulating layer 107 may be positioned on the source 105 and the drain 106. The second insulating layer 107 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating film 107 may be a passivation film or a planarization film.

The first contact electrode 109a connected to the source 105 or the drain 106 of the transistor may be positioned on the second insulating layer 107. In addition, a second contact electrode 109b connected to the second gate 102b may be positioned on the second insulating layer 107. The first contact electrode 109a may be located in the display area AA, and the second contact electrode 109b may be located in the non-display area NA.

In the above, as an example, the transistor located on the first substrate 110 is a batam gate type. However, the transistor located on the first substrate 110 is not limited thereto and may also be formed as a top gate type.

The lower electrode 121 may be positioned on the second substrate 140. The lower electrode 121 may be selected as an anode, and the lower electrode 121 selected as an anode may be indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or AZO (ZnO doped Al2O3). It may be formed of any one, but is not limited thereto.

The auxiliary electrode 122 may be positioned on the lower electrode 121. The auxiliary electrode 122 may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). have.

Bank layers 123a, 123b, and 123c may be disposed on the lower electrode 121 and the auxiliary electrode 122. The bank layers 123a, 123b, and 123c may include organic materials such as benzocyclobutene (BCB) resin, acrylic resin, or polyimide resin. The bank layers 123a and 123b may have openings exposing portions of the lower electrode 121 on the display area AA and the non-display area NA.

On the bank layers 123a and 123b, barrier ribs 124 defining regions of sub-pixels may be located. The partition wall 124 may then be formed to provide process convenience when forming the organic light emitting layer and the upper electrode, which may be formed in an inverted taper shape with a narrower base area than the top area.

Meanwhile, the auxiliary electrode 122 described above may be positioned under the partition wall 124 formed on the bank layers 123a and 123b having openings to define the area of the subpixel. In other words, the auxiliary electrode 122 may be positioned to overlap the region where the partition wall 124 is located.

The spacer 125 protruding to surround at least one surface of the subpixel may be positioned on the bank layer 123b. The spacer 125 may be formed of an organic material or an inorganic material, but is not limited thereto.

The protrusion 126 may be located on the bank layer 123c. The protrusion 126 may be located in the non-display area NA.

The organic emission layer 127 may be positioned on the lower electrode 121 exposed through the openings of the bank layers 123a and 123b. The organic emission layer 127 may be formed to be divided by the sub-pixel region AA by the partition wall 124.

Referring to FIG. 2, the organic light emitting layer 127 may include a hole injection layer 127a, a hole transport layer 127b, a light emitting layer 127c, an electron transport layer 127d, and an electron injection layer 127e.

The hole injection layer 127a may play a role of smoothly injecting holes. CuPc (cupper phthalocyanine), PEDOT (poly (3,4) -ethylenedioxythiophene), PANI (polyaniline), and NPD (N, N-dinaphthyl) -N, N'-diphenyl benzidine) may be composed of any one or more selected from the group consisting of, but is not limited thereto.

The hole transport layer 127b serves to facilitate the transport of holes, NPD (N, N-dinaphthyl-N, N'-diphenyl benzidine), TPD (N, N'-bis- (3-methylphenyl) -N , N'-bis- (phenyl) -benzidine), s-TAD and MTDATA (4,4 ', 4 "-Tris (N-3-methylphenyl-N-phenyl-amino) -triphenylamine) It may be made of one or more, but is not limited thereto.

The emission layer 127c may include materials emitting red, green, blue, and white light and may be formed using phosphorescent or fluorescent materials.

When the light emitting layer 127c is red, it includes a host material including CBP (carbazole biphenyl) or mCP (1,3-bis (carbazol-9-yl), and PIQIr (acac) (bis (1-phenylisoquinoline) acetylacetonate Phosphorescent light containing a dopant including any one or more selected from the group consisting of iridium), PQIr (acac) (bis (1-phenylquinoline) acetylacetonate iridium), PQIr (tris (1-phenylquinoline) iridium) and PtOEP (octaethylporphyrin platinum) It may be made of a material, alternatively may be made of a fluorescent material including PBD: Eu (DBM) 3 (Phen) or perylene, but is not limited thereto.

When the light emitting layer 127c is green, it may include a host material including CBP or mCP, and may be made of a phosphor including a dopant material including Ir (ppy) 3 (fac tris (2-phenylpyridine) iridium). And, alternatively, it may be made of a fluorescent material including Alq3 (tris (8-hydroxyquinolino) aluminum), but is not limited thereto.

When the light emitting layer 127c is blue, the light emitting layer 127c may include a host material including CBP or mCP and may be formed of a phosphor including a dopant material including (4,6-F2ppy) 2Irpic. Alternatively, it may be made of a fluorescent material including any one selected from the group consisting of spiro-DPVBi, spiro-6P, distilbenzene (DSB), distriarylene (DSA), PFO-based polymer and PPV-based polymer, but It is not limited.

The electron transport layer 127d serves to facilitate electron transport, and may be made of any one or more selected from the group consisting of Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq, and SAlq. However, the present invention is not limited thereto.

The electron injection layer 127e serves to facilitate the injection of electrons, and may be Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq or SAlq, but is not limited thereto.

Here, the present invention is not limited to FIG. 4, and at least one of the hole injection layer 127a, the hole transport layer 127b, the electron transport layer 127d, and the electron injection layer 127e may be omitted.

Upper electrodes 128a and 128b may be disposed on the organic emission layer 127. The upper electrodes 128a and 128b may be selected as cathodes, and the upper electrodes 128a and 128b selected as cathodes may be made of an opaque and highly reflective material such as aluminum (Al). The first upper electrode 128a of the upper electrodes 128a and 128b may be positioned to cover the top of the organic emission layer 127 and the surface of the spacer 125 positioned in the display area AA. 128b may be positioned to cover the surface of the protrusion 126 positioned in the non-display area NA.

That is, the upper electrodes 128a and 128b are formed by the partition wall 124 and the first upper electrode 128a positioned inside the display area AA and the second upper electrode 128b positioned within the non-display area NA. ) Can be formed separately. Accordingly, the upper electrodes 128a and 128b may be separated by the partition 124 for each region of the subpixel.

As such, the first upper electrode 128a formed to cover the surface of the spacer 125 and the second upper electrode 128b formed to cover the surface of the protrusion 126 may be formed of the first substrate 110 and the second substrate 140. ) Is brought into contact with the first contact electrode 109a and the second contact electrode 109b, respectively.

Hereinafter, the structure of the spacer according to the embodiment of the present invention will be described in more detail.

5 is a structural diagram of a spacer and a contact electrode according to a first embodiment of the present invention.

FIG. 5A is a plan view of a subpixel formed on the second substrate 140, and FIG. 5B is a plan view of a transistor formed on the first substrate 110. FIG.

Referring to FIG. 5A, a spacer 125 is formed inside the subpixel to surround the entire surface of the emission area EA. The partition wall 124 is formed outside the spacer 125. Referring to FIG. 5B, a first contact electrode 109a is formed on the transistor to be in surface contact with the spacer 125. In an embodiment, the spacer 125 is positioned on one side of the subpixel and is in contact with the first spacer 125a and the first spacer 125a protruding in a columnar shape, and the second spacer protruding to surround the front surface of the subpixel ( 125b) may be formed.

6 and 7 are structural diagrams of a spacer and a contact electrode according to a second embodiment of the present invention.

6 and 7 (a) are plan views of sub-pixels formed on the second substrate 140, and FIGS. 6 and 7 (b) are plan views of transistors formed on the first substrate 110.

6 and 7 (a), the spacer 125 is formed to surround a part of three surfaces of the emission area EA, or the spacer 125 is formed to surround three surfaces. The partition wall 124 is formed outside the spacer 125. 6 and 7 (b), the first contact electrode 109a is formed on the transistor to be in surface contact with the spacer 125. The spacer 125 is positioned on one side of the subpixel and is in contact with the first spacer 125a and the first spacer 125a protruding in the form of a column, and the second spacer protruding to surround a part or three surfaces of three surfaces of the subpixel. 125b).

8 is a structural diagram of a spacer and a contact electrode according to a third embodiment of the present invention.

FIG. 8A is a plan view of a subpixel formed on the second substrate 140, and FIG. 8B is a plan view of a transistor formed on the first substrate 110.

Referring to FIG. 8A, a spacer 125 is formed inside the subpixel to surround three surfaces of the emission area EA. The partition wall 124 is formed outside the spacer 125. Referring to FIG. 8B, the first contact electrode 109a is formed on the transistor to be in surface contact with the spacer 125. In an embodiment, the spacer 125 is positioned on one side of the subpixel and is in contact with the first spacer 125a and the first spacer 125a protruding in the form of a column, and the second spacer protruding to surround three surfaces of the subpixel. It may be formed by being divided into (125b).

As described above, the first upper electrode 128a is formed on the upper surface of the spacer 125 described in the first to third embodiments. Accordingly, the first upper electrode 128a and the first contact electrode 109a vacuum the first substrate 110 and the second substrate 140 by the spacer 125 protruding to surround at least one surface of the subpixel. When bonding, the electrical connection is made in the form of surface contact.

Therefore, the organic light emitting display device according to the embodiment of the present invention can enhance the durability of the panel to absorb or withstand the impact when an impact is applied from the outside. In addition, since the first upper electrode 128a and the first contact electrode 109a are provided in surface contact, the contact resistance between the electrodes can be lowered.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is a schematic plan view of an organic light emitting display device according to an embodiment of the present invention;

2 is an exemplary circuit configuration of a subpixel.

3 is a cross-sectional view of a panel according to an embodiment of the present invention.

4 is a structural diagram of an organic light emitting layer.

5 is a structural diagram of a spacer and a contact electrode according to a first embodiment of the present invention;

6 and 7 are structure diagrams of a spacer and a contact electrode according to a second embodiment of the present invention.

8 is a structural diagram of a spacer and a contact electrode according to a third embodiment of the present invention;

<Explanation of symbols on main parts of the drawings>

110: first substrate 103: first insulating film

104: active layer 105: source

106: drain 107: second insulating film

121: lower electrode 122: metal electrode

124: partition 125: spacer

126: protrusion 127: organic light emitting layer

Claims (9)

A first substrate on which a transistor is formed; A second substrate on which subpixels are formed; Barrier ribs formed around the subpixel to define an area of the subpixel; And a spacer formed in the subpixel and surrounding at least one surface of the subpixel and protruding so that an upper electrode included in the subpixel is electrically connected to a source or a drain of the transistor. The method of claim 1, The spacer, And an organic light emitting display device surrounding the entire surface of the subpixel. The method of claim 1, The spacer, And an organic light emitting display device surrounding the three surfaces of the subpixels. The method according to any one of claims 1 to 3, The transistor includes a contact electrode disposed on the transistor and connected to a source or a drain of the transistor, The contact electrode, And an upper electrode formed on the spacer so as to be in surface contact. The method according to any one of claims 1 to 3, The spacer, A first spacer positioned at one side of the sub-pixel and protruding in a pillar shape; And a second spacer in contact with the first spacer and protruding to surround at least one surface of the sub-pixel. The method according to any one of claims 1 to 3, The spacer, A first spacer positioned at one side of the sub-pixel and protruding in a pillar shape; And a second spacer which is in contact with the first spacer and protrudes to surround at least one surface of the sub-pixel. The method of claim 1, The sub pixel is, A lower electrode formed on the second substrate; A bank layer formed on the lower electrode and exposing a portion of the lower electrode; An organic light emitting layer formed on the lower electrode; The upper electrode formed on the organic light emitting layer, The upper electrode, And an organic light emitting display device, each of which is divided by the partition wall. The method of claim 7, wherein The partition wall, And an organic light emitting display device formed on the bank layer. The method of claim 7, wherein The spacer, And an organic light emitting display device disposed on the bank layer to be adjacent to the partition wall.

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