KR20100077617A - Method for forming titanium nitride and method for forming buried gate - Google Patents

Method for forming titanium nitride and method for forming buried gate Download PDF

Info

Publication number
KR20100077617A
KR20100077617A KR1020080135616A KR20080135616A KR20100077617A KR 20100077617 A KR20100077617 A KR 20100077617A KR 1020080135616 A KR1020080135616 A KR 1020080135616A KR 20080135616 A KR20080135616 A KR 20080135616A KR 20100077617 A KR20100077617 A KR 20100077617A
Authority
KR
South Korea
Prior art keywords
titanium nitride
solution
nitride film
forming
film
Prior art date
Application number
KR1020080135616A
Other languages
Korean (ko)
Inventor
노승재
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080135616A priority Critical patent/KR20100077617A/en
Publication of KR20100077617A publication Critical patent/KR20100077617A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure

Abstract

The present invention is to provide a method for manufacturing a semiconductor device having a buried gate that can prevent the occurrence of deep phenomena when the buried gate is formed by stacking a titanium nitride film and a tungsten film, the semiconductor device manufacturing method of the present invention is a trench in the substrate Forming; Forming a gate insulating film on a surface of the trench; Alternately dipping the substrate on which the gate insulating film is formed into a first solution containing titanium ions (TiCl 4 solution) and a second solution containing nitrogen ions (ZnN solution) to form a titanium nitride film; Forming a tungsten film filling the trench on the titanium nitride film; Recessing the tungsten film and the titanium nitride film to form a buried gate; And forming an interlayer insulating film gap-filling the buried gate, wherein the present invention is a titanium nitride film having a very small grain size and a very thin crystal grain size by a chemical method of dipping alternately using a TiCl 4 solution and a ZnN solution. Can be formed. In particular, the process can be easily completed by simply alternately dipping into a solution in a short time, and is easy to control the thickness of the titanium nitride film by controlling the number of dipping times.

Description

Titanium nitride film formation method and buried gate manufacturing method using the same {METHOD FOR FORMING TITANIUM NITRIDE AND METHOD FOR FORMING BURIED GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a titanium nitride film and a method for manufacturing a semiconductor device having a buried gate.

In recent years, the manufacturing process of semiconductor devices such as DRAM has been developed in the direction of increasing the integration level to 40 nm or less. Recently, various methods for securing reliability and integration of semiconductor devices by applying buried gates or buried wordlines have been attempted. The buried gate (or buried word line) can significantly reduce the parasitic capacitance between the word line and the bit line by embedding the gate in the semiconductor substrate. Accordingly, applying the buried gate has an advantage of greatly improving the sensing margin of the memory device.

1A and 1B illustrate a method of forming a buried gate according to the prior art, and FIG. 1C is a photograph of a core phenomenon according to the prior art.

Referring to FIG. 1A, an isolation layer 12 is formed on the semiconductor substrate 11 to define an active region through a STI (Shalow Trench Isolation) process.

Subsequently, a trench 14 in which the buried gate is to be formed is formed through an etching process using the hard mask layer 13 as an etching barrier. In this case, the trench 14 may be formed by etching not only the active region but also the device isolation layer 12.

Subsequently, after the gate insulating film 15 is formed on the sidewalls and the bottom surface of the trench 14, the titanium nitride film TiN 16 is disposed on the entire surface of the semiconductor substrate 11 to fill the trench 14 on the gate insulating film 15. And tungsten films W and 17 are laminated.

As shown in FIG. 1B, after the planarization process such as chemical mechanical polishing (CMP) is performed until the surface of the hard mask layer 13 is exposed, the etching back process is continued. The tungsten film 17 and the titanium nitride film 16 are recessed. As a result, a buried gate 100 in which a part of the trench 14 is buried is formed. The buried gate 100 has a double layer structure of a titanium nitride film 16 and a tungsten film 17.

Subsequently, after the interlayer insulating film 18 is gap-filled, a planarization process such as chemical mechanical polishing (CMP) is performed until the surface of the hard mask film 13 is exposed.

In the prior art, when a tungsten film is deposited without a titanium nitride film at the time of forming a buried gate, an adhesion problem occurs. Therefore, a tungsten film 17 is deposited on the titanium nitride film 16.

However, in the related art, referring to the reference numeral 'S' and FIG. 1C of FIG. 1A, a seam phenomenon in which the tungsten film is not buried well occurs when the titanium nitride film 16 and the tungsten film 17 are stacked. .

Since the core phenomenon is a critical factor in the development of semiconductor devices in terms of the characteristics and resistance of the buried gate, it is a problem that must be improved for the development of highly integrated semiconductor devices.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and has an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent the occurrence of core phenomenon when forming a buried gate by stacking a titanium nitride film and a tungsten film.

Another object of the present invention is to provide a method of forming a titanium nitride film having a very small grain size.

Titanium nitride film forming method of the present invention for achieving the above object is characterized in that it uses a unit cycle to alternate the step of dipping in a first solution containing titanium ions and a second solution containing nitrogen ions The first solution is a solution in which TiCl 4 is dissolved in a solvent, and the second solution is a solution in which ZnN is dissolved in a solvent.

In addition, the buried gate manufacturing method of the present invention comprises the steps of forming a trench in the substrate; Forming a gate insulating film on a surface of the trench; Alternately dipping the substrate on which the gate insulating film is formed into a first solution containing titanium ions and a second solution containing nitrogen ions to form a titanium nitride film; Forming a tungsten film filling the trench on the titanium nitride film; Recessing the tungsten film and the titanium nitride film to form a buried gate; And forming an interlayer insulating film gap-filling the buried gate.

The present invention described above can form a very thin titanium nitride film having a very small grain size by chemically dipping alternately using a TiCl 4 solution and a ZnN solution. In particular, the process can be easily completed by simply alternately dipping into a solution in a short time, and is easy to control the thickness of the titanium nitride film by controlling the number of dipping times.

Accordingly, the buried space of the tungsten film which is subsequently buried after the deposition of the titanium nitride film can be sufficiently secured, thereby preventing the seam.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

In the present invention, a titanium nitride film and a tungsten film are stacked to apply a chemical bond to prevent deep phenomenon when forming a buried gate. That is, the grain size of the titanium nitride film (Grain size) is made much smaller than the conventional to ensure sufficient space for the tungsten film is buried.

2A is a process flowchart illustrating a method of forming a titanium nitride film according to an embodiment of the present invention.

As shown in FIG. 2A, the titanium nitride film is formed by alternately dipping a substrate into a first solution containing titanium ions and a second solution containing nitrogen (N) ions.

More specifically, the titanium nitride film forming method will be described below.

First, the substrate is dipped in the first solution containing titanium ions (S201). Here, the first solution may be a solution containing titanium ions, a solution in which TiCl 4 is dissolved in a solvent (TiCl 4 solution).

Next, the substrate is dipped in the second solution containing nitrogen ions (S202). The second solution may be a solution in which ZnN is dissolved in a solvent (ZnN solution) as a solution in which nitrogen ions are dissolved.

Next, the substrate is dried (S203). Argon (Ar) gas may be used when drying the substrate.

Thereafter, the step (S204) of removing byproducts generated during the process may be further performed (S204). As a method of removing by-products, sonication may be used.

As described above, the unit cycle is performed from step S201 to step S204, and the unit cycle is repeatedly performed to further stack the TiN film to form a titanium nitride film having a predetermined thickness. The thickness of the titanium nitride film can be controlled by increasing or decreasing the number of cycles of the unit cycle.

The titanium nitride film formed by such a method has a very small grain size compared to the titanium nitride film formed by the general CVD method and the sputtering method, and thus a titanium nitride film having a very thin thickness can be obtained.

Figure 2b is a view comparing the grain size of the titanium nitride film according to the embodiment of the present invention and the titanium nitride film by the conventional CVD method, it can be seen that the crystal grain size is significantly smaller than the titanium nitride film by the conventional CVD method.

In addition, since the titanium nitride film is formed by repeatedly dipping in a solution containing Ti ions and N ions, there is no particle issue. Therefore, defects caused by particles can be prevented.

In addition, since the number of dipping can be adjusted, the thickness of the titanium nitride film can be easily controlled, and the film can be uniformly formed with excellent step coverage. In particular, the process can be easily completed by dipping the wafer into the ion solution in a very short time.

As described above, the present invention can be deposited without any core during the subsequent tungsten film deposition by depositing a titanium nitride film having a small grain size.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to the present invention.

As shown in FIG. 3A, the device isolation layer 22 is formed on the semiconductor substrate 21 through a shadow trench isolation (STI) process. In this case, the device isolation layer 22 may include an oxide film such as a high density plasma oxide film (HDP oxide) and a spin-on insulating film (SOD). The active region 23 is defined by the device isolation layer 22. In the semiconductor substrate 21, a cell region and a peripheral circuit region are defined.

Subsequently, a trench 25 in which the buried gate is to be formed is formed through an etching process using the hard mask layer 24 as an etching barrier. In this case, the trench 25 may be formed by etching not only the active region 23 but also the device isolation layer 22. Typically, since the gate has a line type, the trench 25 is also in the form of a line, and the trench forms a line that crosses the active region 23 and the device isolation layer 22 at the same time by the line of the trench 25. 25 is formed. However, since the etching selectivity between the active region 23 and the device isolation layer 22 is different, as the etching proceeds more toward the device isolation layer 22, the depth of the trench 25 may be deeper in the device isolation layer 22. . For example, the depth of the trench formed in the active region 23 is 1000-1500 kPa, and the depth of the trench formed in the device isolation film 22 is 1500-2000 kPa.

An etching process for forming the trench 25 uses the hard mask film 24 as an etching barrier, and the hard mask film 24 is patterned by a photoresist pattern (not shown). The hard mask layer 24 is preferably a material having a high selectivity when etching the semiconductor substrate 21. For example, the hard mask film 24 includes a structure in which an oxide film and a nitride film are laminated, with an oxide film of 30 to 100 GPa and a nitride film of 100 to 500 GPa.

In the case where the hard mask film 24 is applied, the photoresist pattern may be stripped after the trench 25 is formed.

As shown in FIG. 3B, a gate insulating film 26 is formed on sidewalls and bottom surfaces of the trench 25. The gate insulating layer 26 may be formed by oxidizing the surface of the trench 25. In the oxidation process of the trench surface, a thermal oxidation method may be applied in the same manner as a conventional method of forming a gate insulating film. A silicon oxide film is formed by the oxidation process. Since the semiconductor substrate 21 is a silicon substrate, a silicon oxide film (Si x O y ) is formed by an oxidation process.

Subsequently, a titanium nitride film 27 and a tungsten film 28 are stacked on the entire surface of the gate insulating film 26 to fill the trench 25.

The method of forming the titanium nitride film 27 follows the method shown in FIG. That is, the titanium nitride film is formed by alternately dipping the substrate into the first solution containing titanium ions and the second solution containing nitrogen (N) ions.

Referring to FIG. 2 again, the titanium nitride film forming method will be described in detail as follows.

First, the substrate is dipped in the first solution containing titanium ions (S201). Here, the first solution may be a solution containing titanium ions, and a solution in which TiCl 4 is dissolved in a solvent.

Next, the substrate is dipped in the second solution containing nitrogen ions (S202). Here, the second solution may be a solution in which ZnN is dissolved in a solvent as a solution in which nitrogen ions are dissolved.

Next, the substrate is dried (S203). Argon (Ar) gas can be used when drying the substrate.

Thereafter, the step of removing by-products generated during the process may be performed (S204). As a method of removing by-products, sonication may be used.

As described above, after the titanium nitride film 27 is formed, the tungsten film 28 is deposited. Since the titanium nitride film 27 is formed with a very small grain size and thinly formed, sufficient space is secured when the tungsten film 28 is deposited. Therefore, no deep phenomenon occurs.

As shown in FIG. 3C, a planarization process such as chemical mechanical polishing (CMP) is performed until the surface of the hard mask layer 24 is exposed. Thereafter, the tungsten film and the titanium nitride film are recessed through an etchback process. Accordingly, the buried gate 200 is formed to fill a portion of the trench 25, the buried gate 200 has a double layer structure of the titanium nitride film 27 and tungsten film 28.

As shown in FIG. 3D, an interlayer insulating layer 29 may be formed to gapfill the buried gate 200. The interlayer insulating film 29 includes an oxide film having excellent gap fill characteristics. For example, the interlayer insulating film 29 is formed of a spin-on insulating film SOD made of polysilazane.

The interlayer insulating layer 29 may have a planarization process such as chemical mechanical polishing (CMP) until the surface of the hard mask layer 24 is exposed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1A and 1B illustrate a buried gate forming method according to the prior art.

Figure 1c is a photograph taken a deep phenomenon according to the prior art.

Figure 2a is a process flow diagram illustrating a method of forming a titanium nitride film according to an embodiment of the present invention.

Figure 2b is a view comparing the grain size of the titanium nitride film and the titanium nitride film by the conventional CVD method according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

24: hard mask film 25: trench

26 gate insulating film 27 titanium nitride film

28 tungsten film 29 interlayer insulating film

Claims (10)

A unit cycle is used to alternate between dipping the first solution containing titanium ions and dipping the second solution containing nitrogen ions. Titanium nitride film formation method. The method of claim 1, The first solution is a titanium nitride film forming method using a solution of TiCl 4 dissolved in a solvent. The method of claim 1, The second solution is a titanium nitride film forming method using a solution in which ZnN dissolved in a solvent. The method of claim 1, The unit cycle is a titanium nitride film forming method comprising the step of dipping in the first solution, the dipping in the second solution, and by-products removing step. The method of claim 4, wherein The by-product removal step, the titanium nitride film forming method using sonication (Sonication). Forming a trench in the substrate; Forming a gate insulating film on a surface of the trench; Alternately dipping the substrate on which the gate insulating film is formed into a first solution containing titanium ions and a second solution containing nitrogen ions to form a titanium nitride film; Forming a tungsten film filling the trench on the titanium nitride film; Recessing the tungsten film and the titanium nitride film to form a buried gate; And Forming an interlayer insulating film gap-filling an upper portion of the buried gate A semiconductor device manufacturing method comprising a. The method of claim 6 Forming the titanium nitride film, A method of manufacturing a semiconductor device comprising repeating a unit cycle including dipping into the first solution, dipping into the second solution, and removing by-products. The method of claim 7, wherein The by-product removal step, the semiconductor device manufacturing method using sonication (Sonication). The method of claim 6, The first solution is a semiconductor device manufacturing method using a solution of TiCl 4 dissolved in a solvent. The method of claim 6, The second solution is a semiconductor device manufacturing method using a solution in which ZnN dissolved in a solvent.
KR1020080135616A 2008-12-29 2008-12-29 Method for forming titanium nitride and method for forming buried gate KR20100077617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080135616A KR20100077617A (en) 2008-12-29 2008-12-29 Method for forming titanium nitride and method for forming buried gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080135616A KR20100077617A (en) 2008-12-29 2008-12-29 Method for forming titanium nitride and method for forming buried gate

Publications (1)

Publication Number Publication Date
KR20100077617A true KR20100077617A (en) 2010-07-08

Family

ID=42638945

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080135616A KR20100077617A (en) 2008-12-29 2008-12-29 Method for forming titanium nitride and method for forming buried gate

Country Status (1)

Country Link
KR (1) KR20100077617A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9178039B2 (en) 2012-12-06 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9178039B2 (en) 2012-12-06 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor device

Similar Documents

Publication Publication Date Title
US8592326B2 (en) Method for fabricating an inter dielectric layer in semiconductor device
KR101003496B1 (en) Semiconductor device having recess gate and isolation structure and method for fabricating the same
US8445369B2 (en) Method for fabricating semiconductor device
US8455343B2 (en) Semiconductor device with buried gate and method for fabricating the same
KR20060125063A (en) Method of manufacturing a semiconductor device
US20090004839A1 (en) Method for fabricating an interlayer dielectric in a semiconductor device
US7566924B2 (en) Semiconductor device with gate spacer of positive slope and fabrication method thereof
JP4064732B2 (en) Semiconductor device
KR20100077603A (en) Semiconductor device with buried gate and method for fabricating the same
KR101046727B1 (en) Method of manufacturing buried gate of semiconductor device
US8563432B2 (en) Method for forming through silicon via structure
KR20100077617A (en) Method for forming titanium nitride and method for forming buried gate
KR20120045484A (en) Method for manufacturing buried gate in semiconductor device
US9123579B2 (en) 3D memory process and structures
KR101090371B1 (en) Method for manufacturing semiconductor device with buried gate
KR20100079797A (en) Semiconductor device with buried gate and method for fabricating the same
KR101102052B1 (en) Semiconductor device and method for forming it
KR100868925B1 (en) Method for forming the Isolation Layer of Semiconductor Device
KR100875656B1 (en) Semiconductor device and method for manufacturing the same
KR20080055162A (en) Method of manufacturing semiconductor device
KR100569523B1 (en) A method for forming a bit line of a semiconductor device
KR20110047880A (en) Method for forming buried gate in semiconductor device
KR100519645B1 (en) Method for fabricating gate electrode of semiconductor device
KR100545699B1 (en) Method for forming plug for capacitor contact of semiconductor device
KR100792433B1 (en) Method for manufacturing a semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination