KR20100079797A - Semiconductor device with buried gate and method for fabricating the same - Google Patents
Semiconductor device with buried gate and method for fabricating the same Download PDFInfo
- Publication number
- KR20100079797A KR20100079797A KR1020080138372A KR20080138372A KR20100079797A KR 20100079797 A KR20100079797 A KR 20100079797A KR 1020080138372 A KR1020080138372 A KR 1020080138372A KR 20080138372 A KR20080138372 A KR 20080138372A KR 20100079797 A KR20100079797 A KR 20100079797A
- Authority
- KR
- South Korea
- Prior art keywords
- recess
- gate
- film
- insulating film
- buried gate
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 34
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 26
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 239000012792 core layer Substances 0.000 abstract 1
- 230000008569 process Effects 0.000 description 20
- 230000003647 oxidation Effects 0.000 description 18
- 238000007254 oxidation reaction Methods 0.000 description 18
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000003064 anti-oxidating effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920001709 polysilazane Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
SUMMARY OF THE INVENTION The present invention provides a semiconductor device having a buried gate capable of preventing buried defects such as voids and shims, and a method of manufacturing the same. Forming a recess; Forming a gate conductive film (ALD Ru) on the entire surface of the substrate by using atomic layer deposition (ALD) until the recesses are gap-filled; Recessing the gate conductive layer to form a buried gate partially filling the recess; And forming an interlayer insulating film gap-filling the rest of the recess on the buried gate, wherein the present invention described above uses a core layer deposition method (ALD) to deposit a gate conductive film to be used as a buried gate. In addition, since the buried gate is a ruthenium film by the atomic layer deposition method, it is very advantageous in terms of device even in the recess of a small line width due to the low sheet resistance of the ruthenium film.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a buried gate and a method of manufacturing the same.
In recent years, the manufacturing process of memory devices such as DRAM and flash memory has been developed in the direction of increasing the degree of integration. Recently, various methods for securing reliability and integration of memory devices by applying buried gates have been attempted. The buried gate can significantly reduce the parasitic capacitance between the gate and the bit line by embedding the gate in the semiconductor substrate. Accordingly, applying the buried gate has an advantage of greatly improving the sensing margin of the memory device.
1A illustrates a semiconductor device having a buried gate according to the related art.
Referring to FIG. 1A, an
In the prior art of FIG. 1A, the gate conductive layer is deposited using chemical vapor deposition (CVD) on the entire surface until the recess is filled to form the buried gate, and then the chemical mechanical polishing and the recess etch back are sequentially I'm going.
However, the prior art has a problem in that defects such as voids and seams occur during deposition of a gate conductive film filling the recesses as the line width of the recesses gradually decreases as the memory device is highly integrated.
1B and 1C illustrate a problem according to the prior art.
As shown in FIG. 1B, a problem occurs in that the shim S and the void V occur when the gate
Second, when TiN is applied, the electrical sheet resistance (Rs) is high, which deteriorates the characteristics of the memory device, which is very disadvantageous in terms of reliability.
Third, in the case of TiN, since oxidation occurs well, abnormal oxidation occurs in the subsequent oxidation process, which acts as a defect source.
SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device having a buried gate capable of preventing buried defects such as voids and shims, and a manufacturing method thereof.
The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of: forming a recess by etching the substrate using the hard mask film as an etch barrier; Forming a gate conductive film on the entire surface of the substrate by atomic layer deposition (ALD) until the recesses are gap-filled; Recessing the gate conductive layer to form a buried gate partially filling the recess; And forming an interlayer insulating film gap-filling the rest of the recess on the buried gate, wherein the gate conductive film includes a ruthenium film (ALD Ru) deposited by atomic layer deposition. Do it.
In addition, the semiconductor device of the present invention includes a substrate in which an active region is defined by an element isolation film; A recess formed by etching the active region and the device isolation layer; A gate insulating film formed on the recess surface; A buried gate made of ruthenium film material partially filling the recess on the gate insulating film; And an interlayer insulating film formed on the buried gate.
The present invention described above has an effect of preventing seams and voids by depositing a gate conductive film used as a buried gate using atomic layer deposition (ALD).
In addition, since the buried gate is a ruthenium film by the atomic layer deposition method, it is very advantageous in terms of device even in the recess of a small line width due to the low sheet resistance of the ruthenium film. In addition, since the ruthenium film is resistant to oxidation, there is no need to perform an oxidation prevention process, which has advantages in terms of process simplification.
Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
The present invention is to prevent the generation of voids and seams in the recess by applying an ALD (Atomic Layer Deposition) deposition method, unlike the conventional deposition method by the CVD method.
In addition, by applying a ruthenium film as a buried gate material, the sheet resistance of the ruthenium film is very low compared to the titanium nitride film (lower than 1/10 level), which is advantageous in terms of device. In particular, since the ruthenium layer is a material that is etched by the oxygen chemistry (O 2 Chemistry), the peripheral materials (hard mask layer) has a sufficient selectivity for the oxygen chemistry. This has the advantage of ensuring sufficient process margin.
In addition, the ruthenium film does not generate any abnormal oxidation even when the gate oxidation process is performed in the situation where the interlayer insulating film is gap-filled. This has the advantage of reducing the number of process steps in terms of process set up.
2 is a diagram illustrating a structure of a semiconductor device having a buried gate according to an embodiment of the present invention.
Referring to FIG. 2, in the semiconductor device having a buried gate according to an embodiment of the present invention, the
The buried
According to FIG. 2, since the buried
3A to 3E are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2.
As shown in FIG. 3A, the
Subsequently, a
As described above, since the depth formed in the device isolation layer is deeper than the active region, the recess may serve as a saddle fin for the saddle pin transistor. On the other hand, when the depths of the recesses formed in the
An etching process for forming the
When the
As shown in FIG. 3B, a first
Subsequently, the gate
Preferably, the gate
As shown in FIG. 3C, a planarization process such as chemical mechanical polishing (CMP) is performed until the surface of the
Subsequently, the gate conductive layer is recessed through a recess etchback process. Accordingly, the gate conductive film in which a part of the
When the gate conductive film is a ruthenium film, the recess etch back process is performed using an oxygen-based gas such as oxygen (O 2 ) gas. As a result, it is possible to secure a selection ratio with the surrounding material (hard mask film). In particular, the oxide film is etched back with a selectivity to the surrounding oxide and nitride films.
As shown in FIG. 3D, the
The
Subsequently, the
As shown in FIG. 3E, the
Thereafter, a second
4A is a photograph of a ruthenium film embedded in a recess according to an embodiment of the present invention, and FIG. 4B is a photograph of a gate profile when an embodiment of the present invention is applied.
Referring to FIG. 4A, it can be seen that voids and seams do not occur at all when the ruthenium film is embedded in the recess.
Referring to FIG. 4B, it can be seen that the profile is very uniform since voids and shims do not occur.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
1A illustrates a semiconductor device having a buried gate according to the prior art.
1b and 1c illustrate a problem according to the prior art;
2 is a diagram illustrating a structure of a semiconductor device having a buried gate according to an embodiment of the present invention.
3A to 3E are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2.
Figure 4a is a photograph of the ruthenium film embedded in the recess in accordance with an embodiment of the present invention.
Figure 4b is a photograph taken a gate profile when the embodiment of the present invention is applied.
* Explanation of symbols for the main parts of the drawings
21
23: active area 24: hard mask film
25
27A: buried
Claims (8)
Priority Applications (1)
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KR1020080138372A KR20100079797A (en) | 2008-12-31 | 2008-12-31 | Semiconductor device with buried gate and method for fabricating the same |
Applications Claiming Priority (1)
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KR1020080138372A KR20100079797A (en) | 2008-12-31 | 2008-12-31 | Semiconductor device with buried gate and method for fabricating the same |
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KR20100079797A true KR20100079797A (en) | 2010-07-08 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20120012550A (en) * | 2010-08-02 | 2012-02-10 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
US8697519B2 (en) | 2011-10-18 | 2014-04-15 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor device which includes forming a silicon layer without void and cutting on a silicon monolayer |
-
2008
- 2008-12-31 KR KR1020080138372A patent/KR20100079797A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20120012550A (en) * | 2010-08-02 | 2012-02-10 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
US8697519B2 (en) | 2011-10-18 | 2014-04-15 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor device which includes forming a silicon layer without void and cutting on a silicon monolayer |
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