KR20100079797A - Semiconductor device with buried gate and method for fabricating the same - Google Patents

Semiconductor device with buried gate and method for fabricating the same Download PDF

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Publication number
KR20100079797A
KR20100079797A KR1020080138372A KR20080138372A KR20100079797A KR 20100079797 A KR20100079797 A KR 20100079797A KR 1020080138372 A KR1020080138372 A KR 1020080138372A KR 20080138372 A KR20080138372 A KR 20080138372A KR 20100079797 A KR20100079797 A KR 20100079797A
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South Korea
Prior art keywords
recess
gate
film
insulating film
buried gate
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KR1020080138372A
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Korean (ko)
Inventor
신창협
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주식회사 하이닉스반도체
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Priority to KR1020080138372A priority Critical patent/KR20100079797A/en
Publication of KR20100079797A publication Critical patent/KR20100079797A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor device having a buried gate capable of preventing buried defects such as voids and shims, and a method of manufacturing the same. Forming a recess; Forming a gate conductive film (ALD Ru) on the entire surface of the substrate by using atomic layer deposition (ALD) until the recesses are gap-filled; Recessing the gate conductive layer to form a buried gate partially filling the recess; And forming an interlayer insulating film gap-filling the rest of the recess on the buried gate, wherein the present invention described above uses a core layer deposition method (ALD) to deposit a gate conductive film to be used as a buried gate. In addition, since the buried gate is a ruthenium film by the atomic layer deposition method, it is very advantageous in terms of device even in the recess of a small line width due to the low sheet resistance of the ruthenium film.

Description

Semiconductor device with buried gate and manufacturing method {SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a buried gate and a method of manufacturing the same.

In recent years, the manufacturing process of memory devices such as DRAM and flash memory has been developed in the direction of increasing the degree of integration. Recently, various methods for securing reliability and integration of memory devices by applying buried gates have been attempted. The buried gate can significantly reduce the parasitic capacitance between the gate and the bit line by embedding the gate in the semiconductor substrate. Accordingly, applying the buried gate has an advantage of greatly improving the sensing margin of the memory device.

1A illustrates a semiconductor device having a buried gate according to the related art.

Referring to FIG. 1A, an isolation layer 12 is formed in an isolation region of a semiconductor substrate 11, and a recess 13 having a predetermined depth is formed in the semiconductor substrate 11. The gate insulating film 14 is formed on the surface of the recess 13. A buried gate 15 which partially fills the recess is formed on the gate insulating film, an oxide film 16 is formed on the buried gate 15, and an interlayer insulating film 17 which gap-fills the recess on the oxide film 16. ) Is formed.

In the prior art of FIG. 1A, the gate conductive layer is deposited using chemical vapor deposition (CVD) on the entire surface until the recess is filled to form the buried gate, and then the chemical mechanical polishing and the recess etch back are sequentially I'm going.

However, the prior art has a problem in that defects such as voids and seams occur during deposition of a gate conductive film filling the recesses as the line width of the recesses gradually decreases as the memory device is highly integrated.

1B and 1C illustrate a problem according to the prior art.

As shown in FIG. 1B, a problem occurs in that the shim S and the void V occur when the gate conductive film 15A is deposited. Such voids and shims are more severe with the use of chemical vapor deposition. In other words, the voids V and shims are generated because the chemical vapor deposition method is not densely deposited when buried in the narrow gap 13. As shown in FIG. 1C, the etching rate is different in the same space as the voids (see reference numeral 15B), as shown in FIG. 1C. It is difficult to obtain a flat profile, which affects the electrical characteristics of the memory device.

Second, when TiN is applied, the electrical sheet resistance (Rs) is high, which deteriorates the characteristics of the memory device, which is very disadvantageous in terms of reliability.

Third, in the case of TiN, since oxidation occurs well, abnormal oxidation occurs in the subsequent oxidation process, which acts as a defect source.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device having a buried gate capable of preventing buried defects such as voids and shims, and a manufacturing method thereof.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of: forming a recess by etching the substrate using the hard mask film as an etch barrier; Forming a gate conductive film on the entire surface of the substrate by atomic layer deposition (ALD) until the recesses are gap-filled; Recessing the gate conductive layer to form a buried gate partially filling the recess; And forming an interlayer insulating film gap-filling the rest of the recess on the buried gate, wherein the gate conductive film includes a ruthenium film (ALD Ru) deposited by atomic layer deposition. Do it.

In addition, the semiconductor device of the present invention includes a substrate in which an active region is defined by an element isolation film; A recess formed by etching the active region and the device isolation layer; A gate insulating film formed on the recess surface; A buried gate made of ruthenium film material partially filling the recess on the gate insulating film; And an interlayer insulating film formed on the buried gate.

The present invention described above has an effect of preventing seams and voids by depositing a gate conductive film used as a buried gate using atomic layer deposition (ALD).

In addition, since the buried gate is a ruthenium film by the atomic layer deposition method, it is very advantageous in terms of device even in the recess of a small line width due to the low sheet resistance of the ruthenium film. In addition, since the ruthenium film is resistant to oxidation, there is no need to perform an oxidation prevention process, which has advantages in terms of process simplification.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

The present invention is to prevent the generation of voids and seams in the recess by applying an ALD (Atomic Layer Deposition) deposition method, unlike the conventional deposition method by the CVD method.

In addition, by applying a ruthenium film as a buried gate material, the sheet resistance of the ruthenium film is very low compared to the titanium nitride film (lower than 1/10 level), which is advantageous in terms of device. In particular, since the ruthenium layer is a material that is etched by the oxygen chemistry (O 2 Chemistry), the peripheral materials (hard mask layer) has a sufficient selectivity for the oxygen chemistry. This has the advantage of ensuring sufficient process margin.

In addition, the ruthenium film does not generate any abnormal oxidation even when the gate oxidation process is performed in the situation where the interlayer insulating film is gap-filled. This has the advantage of reducing the number of process steps in terms of process set up.

2 is a diagram illustrating a structure of a semiconductor device having a buried gate according to an embodiment of the present invention.

Referring to FIG. 2, in the semiconductor device having a buried gate according to an embodiment of the present invention, the semiconductor substrate 21 in which the active region 23 is defined by the device isolation layer 22, and the active region and the device isolation layer are etched. Formed on the recess 25, the gate insulating film 26 formed on the recess surface, and the buried gate 27A and the buried gate 27A made of ruthenium film material which partially fill the recess on the gate insulating film 26. An interlayer insulating film 28A.

The buried gate 27A includes a ruthenium film formed by atomic layer deposition (ALD), and the interlayer insulating film 28A includes a spin-on insulating film SOD.

According to FIG. 2, since the buried gate 27A is a ruthenium film by an atomic layer deposition method, it is very advantageous in terms of device even in the recess of a small line width due to the low sheet resistance of the ruthenium film. In addition, since the ruthenium film is resistant to oxidation, an anti-oxidation film is not required separately, which has advantages in terms of process simplification.

3A to 3E are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2.

As shown in FIG. 3A, the device isolation layer 22 is formed on the semiconductor substrate 21 through a shadow trench isolation (STI) process. In this case, the device isolation layer 22 may include an oxide film such as a high density plasma oxide film (HDP oxide) and a spin-on insulating film (SOD). The active region 23 is defined by the device isolation layer 22. In the semiconductor substrate 21, a cell region and a peripheral circuit region are defined.

Subsequently, a recess 25 in which the buried gate is to be formed is formed through an etching process using the hard mask layer 24 as an etching barrier. In this case, the recess 25 may be formed by etching not only the active region 23 but also the device isolation layer 22. Typically, since the gate has a line type, the recess 25 is also a line type, and the line shape of the recess 25 simultaneously crosses the active region 23 and the device isolation layer 22 by the line shape. Of recesses 25 are formed. However, since the etching selectivity between the active region 23 and the device isolation layer 22 is different, the etching 25 may be more etched toward the device isolation layer 22, so that the depth of the recess 25 may be deeper in the device isolation layer 22. have. For example, the depth of the recess formed in the active region 23 is 1000 Å, and the depth of the recess formed in the device isolation film 22 is 1200 Å.

As described above, since the depth formed in the device isolation layer is deeper than the active region, the recess may serve as a saddle fin for the saddle pin transistor. On the other hand, when the depths of the recesses formed in the active region 23 and the device isolation layer 22 are the same, they may function as channels of the recess gates.

An etching process for forming the recess 25 uses the hard mask film 24 as an etching barrier, and the hard mask film 24 is patterned by a photoresist pattern (not shown). The hard mask layer 24 is preferably a material having a high selectivity when etching the semiconductor substrate 21. For example, the hard mask film 24 may include a structure in which an oxide film and a nitride film are stacked. The oxide film may be formed to have a thickness of 50 mW and the nitride film may be formed to be 800 mW.

When the hard mask film 24 is applied, the photoresist pattern may be stripped after the recess 25 is formed.

As shown in FIG. 3B, a first gate insulating film 26 for transistors in the cell region is formed on sidewalls and bottom surfaces of the recesses 25. The first gate insulating layer 26 may be formed by oxidizing the surface of the recess 25. The oxidation process of the recess surface can be applied to a thermal oxidation method in the same manner as a conventional method of forming a gate insulating film. A silicon oxide film is formed by the oxidation process. Since the semiconductor substrate 21 is a silicon substrate, a silicon oxide film (Si x O y ) is formed by an oxidation process.

Subsequently, the gate conductive film 27 is deposited on the entire surface of the semiconductor substrate 21 so as to fill the recess 25 on the first gate insulating film 26. In this case, the gate conductive layer 27 is deposited to have a thickness of 800 to 1000 GPa using atomic layer deposition (ALD). As described above, when the gate conductive film is deposited using the atomic layer deposition method, the generation of voids and seams can be suppressed.

Preferably, the gate conductive layer 27 includes a ruthenium layer (ALD Ru) deposited by atomic layer deposition. The ruthenium film has a sheet resistance lower than that of the titanium nitride film by 1/10, which is advantageous for high-speed operation, and the oxidation resistance is strong. Therefore, abnormal oxidation does not occur during the subsequent oxidation process.

As shown in FIG. 3C, a planarization process such as chemical mechanical polishing (CMP) is performed until the surface of the hard mask film 24 is exposed. That is, in the case where the hard mask film 24 is a nitride film, the polishing proceeds by allowing the nitride film to stop (Nitride just stop).

Subsequently, the gate conductive layer is recessed through a recess etchback process. Accordingly, the gate conductive film in which a part of the recess 25 is embedded is left, and the remaining gate conductive film becomes a buried gate 27A. The recess amount during the recess etchback is controlled to about 500 ms.

When the gate conductive film is a ruthenium film, the recess etch back process is performed using an oxygen-based gas such as oxygen (O 2 ) gas. As a result, it is possible to secure a selection ratio with the surrounding material (hard mask film). In particular, the oxide film is etched back with a selectivity to the surrounding oxide and nitride films.

As shown in FIG. 3D, the interlayer insulating film 28 is formed without forming an antioxidant film. The reason why the anti-oxidation film is not required in the present invention is that the buried gate 27A formed of the ruthenium film has a strong oxidation resistance against subsequent oxidation processes. Accordingly, the present invention can also obtain a process simplification effect.

The interlayer insulating film 28 is formed of an oxide film, and particularly includes an oxide film having excellent gap fill characteristics. For example, the interlayer insulating film 28 is formed of a spin-on insulating film SOD made of polysilazane as a raw material.

Subsequently, the interlayer insulating film 28 is planarized so that the surface of the hard mask film 24 is exposed by chemical mechanical polishing. At this time, when the hard mask film 24 is a nitride film, an excessive CMP (Over CMP) for further polishing the hard mask film 24 by about 200 to 300 GPa may be performed.

As shown in FIG. 3E, the hard mask film 24 is removed, and when the hard mask film is removed, the interlayer insulating film may be partially recessed. Accordingly, the interlayer insulating film may remain as shown at 28A.

Thereafter, a second gate insulating film 29 is formed to fabricate a transistor in the peripheral circuit region. The buried gate is not oxidized in the gate oxidation process for forming the second gate insulating layer 29.

4A is a photograph of a ruthenium film embedded in a recess according to an embodiment of the present invention, and FIG. 4B is a photograph of a gate profile when an embodiment of the present invention is applied.

Referring to FIG. 4A, it can be seen that voids and seams do not occur at all when the ruthenium film is embedded in the recess.

Referring to FIG. 4B, it can be seen that the profile is very uniform since voids and shims do not occur.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1A illustrates a semiconductor device having a buried gate according to the prior art.

1b and 1c illustrate a problem according to the prior art;

2 is a diagram illustrating a structure of a semiconductor device having a buried gate according to an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2.

Figure 4a is a photograph of the ruthenium film embedded in the recess in accordance with an embodiment of the present invention.

Figure 4b is a photograph taken a gate profile when the embodiment of the present invention is applied.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: active area 24: hard mask film

25 recess 26 gate insulating film

27A: buried gate 28A: interlayer insulating film

Claims (8)

Etching the substrate using the hard mask layer as an etch barrier to form a recess; Forming a gate conductive film on the entire surface of the substrate by atomic layer deposition (ALD) until the recesses are gap-filled; Recessing the gate conductive layer to form a buried gate partially filling the recess; And Forming an interlayer insulating film on the buried gate to gap-fill the rest of the recess A semiconductor device manufacturing method comprising a. The method of claim 1, Forming the buried gate, Chemically polishing (CMP) the gate conductive layer until the surface of the hard mask layer is exposed and planarized; And Recessing back the planarized gate conductive layer A semiconductor device manufacturing method comprising a. The method of claim 2, The gate conductive film includes a ruthenium film (ALD Ru) deposited by atomic layer deposition. The method of claim 3, And the recess etch back is carried out using an oxygen base gas. The method of claim 1, The interlayer insulating film includes a spin-on insulating film (SOD). A substrate in which an active region is defined by an isolation layer; A recess formed by etching the active region and the device isolation layer; A gate insulating film formed on the recess surface; A buried gate made of ruthenium film material partially filling the recess on the gate insulating film; And An interlayer insulating film formed on the buried gate A semiconductor device comprising a. The method of claim 6, And said buried gate includes a ruthenium film formed by atomic layer deposition. The method of claim 6, The interlayer insulating film includes a spin-on insulating film (SOD).
KR1020080138372A 2008-12-31 2008-12-31 Semiconductor device with buried gate and method for fabricating the same KR20100079797A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120012550A (en) * 2010-08-02 2012-02-10 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US8697519B2 (en) 2011-10-18 2014-04-15 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device which includes forming a silicon layer without void and cutting on a silicon monolayer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120012550A (en) * 2010-08-02 2012-02-10 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US8697519B2 (en) 2011-10-18 2014-04-15 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device which includes forming a silicon layer without void and cutting on a silicon monolayer

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