KR100569523B1 - A method for forming a bit line of a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, and in order to prevent deterioration of characteristics of a device due to voids in a bit line contact hole, a first interlayer on a semiconductor substrate having a bit line first contact plug. Forming an insulating film and forming a bit line contact hole exposing the bit line first contact plug using a bit line contact mask, and then depositing a conductive layer for the bit line on the entire surface including the bit line contact hole. By forming a hard mask layer of the HDP CVD method in a multilayer structure on the bit line conductive layer, it is possible to prevent the exposure of the voids formed in the bit line contact hole during the subsequent process, thereby preventing deterioration of device characteristics due to the exposure of the voids. It is possible to achieve a high integration of the semiconductor device accordingly.

Description

A method for forming a bit line of a semiconductor device

1A and 1B are cross-sectional schematics showing a bit line forming method according to the prior art.

2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

11: semiconductor substrate 13: first interlayer insulating film

15 diffusion barrier film 17 bit line contact hole

19: tungsten layer 21: hard mask layer, nitride film

23 oxide film, second interlayer insulating film

The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a technique for preventing a phenomenon in which a characteristic deterioration is caused during a formation process of a bit line due to miniaturization due to high integration of a semiconductor device.

DRAM, a semiconductor memory device, is formed of a unit cell with one transistor and a capacitor, and requires a bit line or a metal wiring to drive them.

The bit line is used as a passage when storing or reading data in the capacitor.

The bit line is formed of a conductive layer connected to the source junction region of the semiconductor substrate.

However, as semiconductor devices are highly integrated, the distance from neighboring devices is shortened, which causes a problem of deterioration of insulating properties from neighboring devices.

In order to minimize this, a hard mask layer is formed on the conductive layer for the bit line, preventing the damage of the bit line due to the subsequent process, and improving the insulating property with other layers, thereby enabling high integration of the semiconductor device.

1A and 1B are cross-sectional (SEM) photographs illustrating a method of forming a bit line of a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer defining an active region is formed on a semiconductor substrate. In this case, the device isolation layer is formed in a trench type.

Next, a stacked structure of a gate oxide film, a polyside layer, and a hard mask layer is formed on the semiconductor substrate, and the gate electrode is formed by etching the same by a photolithography process using a gate electrode mask.

A contact plug connected to the active region of the semiconductor substrate is formed between the gate electrodes.

The contact plug includes a bit line contact plug connected to the source junction region and a storage electrode contact plug connected to the drain junction region.

A laminated structure of a first interlayer insulating film and a diffusion barrier film is formed over the entire surface.

A photolithography process using a bit line contact mask is used to form a bit line contact hole exposing the bit line contact plug.

A tungsten layer serving as a bit line conductive layer is formed on the entire surface including the bit line contact hole.

A nitride film to be used as a hard mask layer for the bit line is formed on the tungsten layer by PE plasma enhanced chemical vapor deposition (PE CVD).

The hard mask layer, the tungsten layer and the diffusion barrier layer are etched by a photolithography process using a bit line mask to form a bit line.

However, as shown in FIG. 1A, a void is formed in the bit line contact hole, and an overhang is caused on the bit line contact hole.

In a subsequent process, an oxide film, which is a second interlayer insulating film, is formed on the entire surface by HDP CVD (high density plasma chemical vapor deposition).

Referring to FIG. 1B, the hard mask layer is exposed by planarizing etching of the oxide film, which is the second interlayer insulating film. Here, the planarization etching process is performed by the CMP method.

In this case, the hard mask layer is excessively etched and a void is exposed to the upper side of the bit line contact hole which is overhanged in FIG.

As described above, in the method of forming a bit line of a semiconductor device according to the related art, a tungsten layer, which is a conductive layer for a bit line, may be damaged through a void exposed as shown in ⓑ of FIG. 1B, thereby deteriorating device characteristics and reliability. As a result, there is a problem in that high integration of the semiconductor device is difficult.

The present invention is to solve the problems according to the prior art, by using a high density plasma chemical vapor deposition (HDP CVD) method to form a multi-layer hard mask layer to reduce the size of the void and the subsequent flattening etching process It is an object of the present invention to provide a method for forming a bit line of a semiconductor device that prevents the voids from being exposed and thus prevents deterioration of characteristics of the semiconductor device, and thereby enables high integration of the semiconductor device.

In order to achieve the above object, a method of forming a bit line of a semiconductor device according to the present invention,
Forming an interlayer insulating film on the semiconductor substrate;
Forming a bit line contact hole using a bit line contact mask;
Depositing a bit line conductive layer having a predetermined thickness on the entire surface including the bit line contact hole;

Forming a hard mask layer of a high density plasma chemical vapor deposition (HDP CVD) method to fill the bit line contact hole on the bit line conductive layer, and a second process of forming an interface with the first process of forming a nitride film Forming by repeating,

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The bit line conductive layer is a tungsten layer,

The hard mask layer is formed of a nitride film,

The hard mask layer is made of SiH4 30-70 sccm, NH4 40-150 sccm, N2 500-2000 sccm, He 100-500 sccm using a source power of 1000-5000 W and 1000-5000 W under a pressure of 2-5 mTorr. A first process of forming a nitride film with a bias power of 2000 W, and a flow rate of N2 500 to 2000 sccm, He 100 to 500 sccm into a reaction chamber to which a source power of 1000 to 5000 W and a bias power of 0 W are applied to the interface. Forming by repeating the second step of forming a.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a first interlayer insulating film 13 is formed on the semiconductor substrate 11.

The semiconductor substrate 11 includes a device isolation film (not shown), a gate electrode (not shown), a bit line contact plug (not shown) connected to a source junction region, and a storage electrode contact plug connected to a drain junction region (not shown). No) is formed.

A lamination structure of the first interlayer insulating film 13 and the diffusion barrier film 15 is formed on the entire surface.

A photolithography process using a bit line contact mask (not shown) forms a bit line contact hole 17 exposing the bit line contact plug.

A tungsten layer 19 serving as a bit line conductive layer is formed on the entire surface including the bit line contact hole 17.

A nitride film 21 to be used as a hard mask layer for bit lines is formed on the tungsten layer 19.

At this time, the nitride film 21 has a source power of 1000 to 5000 W at a pressure of 2 to 5 mTorr using a flow rate of SiH4 30 to 70 sccm, NH4 40 to 150 sccm, N2 500 to 2000 sccm, He 100 to 500 sccm. And a first process of forming a nitride film with a bias power of 1000 to 2000 W, and a reaction chamber to which a source power of 1000 to 5000 W and a bias power of 0 W are applied, and a flow rate of N2 500 to 2000 sccm and He 100 to 500 sccm. It is formed into a multilayer structure by using a multi-step HDP CVD (high density plasma chemical vapor deposition) method of repeating the second process of forming an interface by flowing. Here, the interface serves to suppress the growth of the void formed in the first step.

Next, the hard mask layer 21, the tungsten layer 19, and the diffusion barrier 15 are etched by a photolithography process using a bit line mask (not shown) to form bit lines.

An oxide film 23 as a second interlayer insulating film is formed on the entire surface by HDP CVD (high density plasma chemical vapor deposition).

Referring to FIG. 2B, the oxide layer 23, which is the second interlayer insulating layer, is planarized and etched to expose the nitride layer 21, which is the hard mask layer. Here, the planarization etching process is performed by the CMP method.

As described above, in the method of forming a bit line of a semiconductor device according to the present invention, a nitride film having a multi-layer structure is formed by using a multi-step HDP CVD method and used as a hard mask layer to reduce the size of voids in the bit line contact hole and subsequently planar etching It is possible to prevent the exposure of the void during the process, it is possible to prevent the occurrence of pinholes by forming the hard mask layer in a multi-stage, thereby preventing the deterioration of characteristics and improve the characteristics and reliability of the semiconductor device. .

Claims (4)

Forming an interlayer insulating film on the semiconductor substrate; Forming a bit line contact hole using a bit line contact mask; Depositing a bit line conductive layer having a predetermined thickness on the entire surface including the bit line contact hole; Forming a hard mask layer of a high density plasma chemical vapor deposition (HDP CVD) method to fill the bit line contact hole on the bit line conductive layer, and a second process of forming an interface with the first process of forming a nitride film Repeated Forming Process Bit line forming method of a semiconductor device comprising a. The method of claim 1, And the bit line conductive layer is a tungsten layer. The method of claim 1, And said hard mask layer is formed of a nitride film. The method of claim 1, The hard mask layer is made of SiH4 30-70 sccm, NH4 40-150 sccm, N2 500-2000 sccm, He 100-500 sccm using a source power of 1000-5000 W and 1000-5000 W under a pressure of 2-5 mTorr. A first process of forming a nitride film with a bias power of 2000 W, and a flow rate of N2 500 to 2000 sccm, He 100 to 500 sccm into a reaction chamber to which a source power of 1000 to 5000 W and a bias power of 0 W are applied to the interface. And forming a multilayer structure by using a multi-step HDP CVD method which repeats the second process of forming a film.

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