KR20050002364A - A method for forming a bit line of a semiconductor device - Google Patents

A method for forming a bit line of a semiconductor device Download PDF

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KR20050002364A
KR20050002364A KR1020030043741A KR20030043741A KR20050002364A KR 20050002364 A KR20050002364 A KR 20050002364A KR 1020030043741 A KR1020030043741 A KR 1020030043741A KR 20030043741 A KR20030043741 A KR 20030043741A KR 20050002364 A KR20050002364 A KR 20050002364A
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bit line
forming
line contact
sccm
layer
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KR1020030043741A
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KR100569523B1 (en
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김진웅
김한민
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of forming a bit line of a semiconductor device is provided to prevent a void from being exposed to the outside and to restrain the degradation of properties in the device by using a nitride layer of a multilayer structure as a hard mask layer. CONSTITUTION: A first interlayer dielectric(13) is formed on a semiconductor substrate(11) with a bit line contact plug. A bit line contact hole for exposing the bit line contact plug is formed in the first interlayer dielectric by using a bit line contact mask. A conductive layer(19) is formed along the entire surface of the resultant structure. A hard mask layer(21) made of nitride is formed on the conductive layer by using multi-step HDP CVDs(High Density Plasma Chemical Vapor Depositions). The hard mask layer is a multilayer structure.

Description

반도체소자의 비트라인 형성방법{A method for forming a bit line of a semiconductor device}A method for forming a bit line of a semiconductor device

본 발명은 반도체소자의 비트라인 형성방법에 관한 것으로, 특히 반도체소자의 고집적화에 따른 미세화로 인하여 비트라인의 형성공정시 특성 열화가 유발되는 현상을 방지할 수 있도록 하는 기술에 관한 것이다.The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a technique for preventing a phenomenon in which a characteristic deterioration is caused during a formation process of a bit line due to miniaturization due to high integration of a semiconductor device.

반도체 메모리 소자인 디램은 하나의 트랜지스터와 캐패시터로 단위 셀이 형성되고 이들을 구동하기 위하여 비트라인이나 금속배선 등을 필요로 하게 된다.DRAM, a semiconductor memory device, is formed of a unit cell with one transistor and a capacitor, and requires a bit line or a metal wiring to drive them.

상기 비트라인은 상기 캐패시터에 데이터를 저장하거나 읽을 때 통로로 용된다.The bit line serves as a passage when storing or reading data in the capacitor.

상기 비트라인 반도체기판의 소오스 접합영역에 접속되는 도전층으로 형성된다.And a conductive layer connected to the source junction region of the bit line semiconductor substrate.

그러나, 반도체소자가 고집적화됨에 따라 이웃하는 소자들과의 거리가 짧아지게 되고 그로 인하여 이웃하는 소자들과의 절연특성이 열화되는 문제점이 유발되었다.However, as semiconductor devices are highly integrated, the distance from neighboring devices is shortened, which causes a problem of deterioration of insulating properties from neighboring devices.

이를 최소화시키기 위하여 비트라인용 도전층의 상부에 하드마스크층을 형성하고 후속 공정으로 인한 비트라인 손상을 방지하고 타층과의 절연특성을 향상시킴으로써 반도체소자의 고집적화를 가능하게 하였다.In order to minimize this, a hard mask layer is formed on the conductive layer for the bit line, preventing the damage of the bit line due to the subsequent process, and improving the insulating property with other layers, thereby enabling high integration of the semiconductor device.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 비트라인 형성방법을 도시한 단면 셈사진이다.1A and 1B are cross-sectional schematics illustrating a bit line forming method of a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체기판 상에 활성영역을 정의하는 소자분리막을 형성한다. 이때, 상기 소자분리막은 트렌치형으로 형성한 것이다.Referring to FIG. 1A, an isolation layer defining an active region is formed on a semiconductor substrate. In this case, the device isolation layer is formed in a trench type.

그 다음, 상기 반도체기판 상부에 게이트산화막, 폴리사이드층 및 하드마스크층의 적층구조를 형성하고 이를 게이트전극 마스크를 이용한 사진식각공정으로 식각하여 게이트전극을 형성한다.Next, a stacked structure of a gate oxide film, a polyside layer, and a hard mask layer is formed on the semiconductor substrate, and the gate electrode is formed by etching the same by a photolithography process using a gate electrode mask.

상기 게이트전극 사이를 통하여 상기 반도체기판의 활성영역에 접속되는 콘택플러그를 형성한다.A contact plug is formed to be connected to the active region of the semiconductor substrate through the gate electrodes.

상기 랜딩 플러그는 소오스 접합영역에 접속되는 비트라인용 콘택플러그와 드레인 접합영역에 접속되는 저장전극용 랜딩 플러그로 구성된다.The landing plug includes a bit line contact plug connected to the source junction region and a storage electrode landing plug connected to the drain junction region.

전체표면상부에 제1층간절연막 및 확산방지막의 적층구조를 형성한다.A laminated structure of a first interlayer insulating film and a diffusion barrier film is formed over the entire surface.

비트라인 콘택마스크를 이용한 사진식각공정으로 상기 비트라인용 콘택플러그를 노출시키는 비트라인 콘택홀을 형성한다.A photolithography process using a bit line contact mask is used to form a bit line contact hole exposing the bit line contact plug.

상기 비트라인 콘택홀을 포함한 전체표면상부에 비트라인용 도전층인 텅스텐층을 일정두께 형성한다.A tungsten layer serving as a bit line conductive layer is formed on the entire surface including the bit line contact hole.

상기 텅스텐층 상부에 비트라인용 하드마스크층으로 사용될 질화막을 PE CVD ( plasma enhanced chemical vapor deposition ) 방법으로 형성한다.A nitride film to be used as a hard mask layer for the bit line is formed on the tungsten layer by PE plasma enhanced chemical vapor deposition (PE CVD).

비트라인 마스크를 이용한 사진식각공정으로 상기 하드마스크층, 텅스텐층 및 확산방지막을 식각하여 비트라인을 형성한다.The hard mask layer, the tungsten layer and the diffusion barrier layer are etched by a photolithography process using a bit line mask to form a bit line.

그러나, 상기 도 1a 에 도시된 ⓐ 와 같이 상기 비트라인 콘택홀 내에 보이드 ( void ) 가 형성되고 상기 비트라인 콘택홀의 상측에서 오버행이 유발된다.However, as shown in FIG. 1A, a void is formed in the bit line contact hole, and an overhang is caused on the bit line contact hole.

후속 공정으로 전체표면상부에 HDP CVD ( high density plasma chemical vapor deposition ) 방법으로 제2층간절연막인 산화막을 형성한다.In a subsequent process, an oxide film, which is a second interlayer insulating film, is formed on the entire surface by HDP CVD (high density plasma chemical vapor deposition).

도 1b를 참조하면, 상기 제2층간절연막인 산화막을 평탄화식각하여 상기 하드마스크층을 노출시킨다. 여기서, 상기 평탄화식각공정은 CMP 방법으로 실시한다.Referring to FIG. 1B, the hard mask layer is exposed by planarizing etching of the oxide film, which is the second interlayer insulating film. Here, the planarization etching process is performed by the CMP method.

이때, 상기 하드마스크층이 과도식각되고 상기 도 1a에서 오버행된 비트라인 콘택홀의 상측으로 ⓑ 와 같이 보이드가 노출되는 경우가 유발된다.In this case, the hard mask layer is excessively etched and a void is exposed to the upper side of the bit line contact hole which is overhanged in FIG.

상기한 바와 같이 종래기술에 따른 반도체소자의 비트라인 형성방법은, ⓑ 와 같이 노출되는 보이드를 통해 비트라인용 도전층인 텅스텐층이 손상될 수 있어 소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a bit line of a semiconductor device according to the related art, a tungsten layer, which is a conductive layer for a bit line, may be damaged through a void exposed as ⓑ, thereby degrading the characteristics and reliability of the device and thereby the semiconductor device. There is a problem that makes it difficult to integrate.

본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, HDP CVD ( high density plasma chemical vapor deposition ) 방법을 이용하여 다층의 하드마스크층을 형성하여 보이드의 크기를 감소시키고 후속 평탄화식각공정으로도 상기 보이드가 노출되지 않도록 하여 반도체소자의 특성 열화를 방지하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 비트라인 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems according to the prior art, by using a high density plasma chemical vapor deposition (HDP CVD) method to form a multi-layer hard mask layer to reduce the size of the void and the subsequent flattening etching process It is an object of the present invention to provide a method for forming a bit line of a semiconductor device that prevents the voids from being exposed and thus prevents deterioration of characteristics of the semiconductor device, and thereby enables high integration of the semiconductor device.

도 1a 및 도 1b 는 종래기술에 따른 비트라인 형성방법을 도시한 단면 셈사진.1A and 1B are cross-sectional schematics showing a bit line forming method according to the prior art.

도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 비트라인 형성방법을 제공한 단면도.2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11 : 반도체기판 13 : 제1층간절연막11: semiconductor substrate 13: first interlayer insulating film

15 : 확산방지막 17 : 비트라인 콘택홀15 diffusion barrier film 17 bit line contact hole

19 : 텅스텐층 21 : 하드마스크층, 질화막19: tungsten layer 21: hard mask layer, nitride film

23 : 산화막, 제2층간절연막23 oxide film, second interlayer insulating film

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 비트라인 형성방법은,In order to achieve the above object, a method of forming a bit line of a semiconductor device according to the present invention,

비트라인 콘택플러그가 구비되는 반도체기판 상에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on a semiconductor substrate provided with a bit line contact plug;

비트라인 콘택마스크를 이용하여 상기 비트라인 콘택플러그를 노출시키는 비트라인 콘택홀을 형성하는 공정과,Forming a bit line contact hole exposing the bit line contact plug by using a bit line contact mask;

상기 비트라인 콘택홀을 포함한 전체표면상부에 비트라인용 도전층을 증착하는 공정과,Depositing a conductive layer for bit lines on the entire surface including the bit line contact holes;

상기 비트라인용 도전층 상에 HDP CVD 방법의 하드마스크층을 다층구조로 형성하는 공정을 포함하는 것과,Forming a hard mask layer of an HDP CVD method in a multilayer structure on the bit line conductive layer;

상기 비트라인용 도전층은 텅스텐층인 것과,The bit line conductive layer is a tungsten layer,

상기 하드마스크층은 질화막으로 형성하는 것과,The hard mask layer is formed of a nitride film,

상기 하드마스크층은 SiH4 30∼70 sccm, NH4 40∼150 sccm, N2 500∼2000 sccm, He 100 ~ 500 sccm 의 유량을 이용하여 2 ~ 5 mTorr 의 압력하에서 1000∼5000 W 의 소오스 전력 및 1000∼2000 W 의 바이어스 전력으로 질화막을 형성하는 제1공정과, 1000∼5000 W 의 소오스 전력 및 0 W 의 바이어스 전력이 인가되는 반응실로 N2 500∼2000 sccm, He 100 ~ 500 sccm의 유량을 플로우시켜 계면을 형성하는 제2공정을 반복 실시하여 형성하는 것을 특징으로 한다.The hard mask layer is made of SiH4 30-70 sccm, NH4 40-150 sccm, N2 500-2000 sccm, He 100-500 sccm using a source power of 1000-5000 W and 1000-5000 W under a pressure of 2-5 mTorr. A first process of forming a nitride film with a bias power of 2000 W, and a flow rate of N2 500 to 2000 sccm, He 100 to 500 sccm into a reaction chamber to which a source power of 1000 to 5000 W and a bias power of 0 W are applied to the interface. Forming by repeating the second step of forming a.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 비트라인 형성방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 반도체기판(11) 상에 제1층간절연막(13)을 형성한다.Referring to FIG. 2A, a first interlayer insulating film 13 is formed on the semiconductor substrate 11.

상기 반도체기판(11)은 소자분리막(도시안됨), 게이트전극(도시안됨), 소오스 접합영역에 접속되는 비트라인용 콘택플러그(도시안됨)와 드레인 접합영역에 접속되는 저장전극용 콘택플러그(도시안됨)가 형성된 것이다.The semiconductor substrate 11 includes a device isolation film (not shown), a gate electrode (not shown), a bit line contact plug (not shown) connected to a source junction region, and a storage electrode contact plug connected to a drain junction region (not shown). No) is formed.

전체표면상부에 제1층간절연막(13) 및 확산방지막(15)의 적층구조를 형성한다.A lamination structure of the first interlayer insulating film 13 and the diffusion barrier film 15 is formed on the entire surface.

비트라인 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 비트라인용콘택플러그를 노출시키는 비트라인 콘택홀(17)을 형성한다.The bit line contact hole 17 exposing the bit line contact plug is formed by a photolithography process using a bit line contact mask (not shown).

상기 비트라인 콘택홀(17)을 포함한 전체표면상부에 비트라인용 도전층인 텅스텐층(19)을 일정두께 형성한다.A tungsten layer 19 serving as a bit line conductive layer is formed on the entire surface including the bit line contact hole 17.

상기 텅스텐층(19) 상부에 비트라인용 하드마스크층으로 사용될 질화막(21)을 형성한다.A nitride film 21 to be used as a hard mask layer for bit lines is formed on the tungsten layer 19.

이때, 상기 질화막(21)은 SiH4 30∼70 sccm, NH4 40∼150 sccm, N2 500∼2000 sccm, He 100 ~ 500 sccm 의 유량을 이용하여 2 ~ 5 mTorr 의 압력하에서 1000∼5000 W 의 소오스 전력 및 1000∼2000 W 의 바이어스 전력으로 질화막을 형성하는 제1공정과, 1000∼5000 W 의 소오스 전력 및 0 W 의 바이어스 전력이 인가되는 반응실로 N2 500∼2000 sccm, He 100 ~ 500 sccm의 유량을 플로우시켜 계면을 형성하는 제2공정을 반복 실시하는 다단계의 HDP CVD ( high density plasma chemical vapor deposition ) 방법을 이용하여 다층구조로 형성한다. 여기서, 상기 계면은 첫째 단계에서 형성되는 보이드의 성장을 억제하는 역할을 한다.At this time, the nitride film 21 has a source power of 1000 to 5000 W at a pressure of 2 to 5 mTorr using a flow rate of SiH4 30 to 70 sccm, NH4 40 to 150 sccm, N2 500 to 2000 sccm, He 100 to 500 sccm. And a first process of forming a nitride film with a bias power of 1000 to 2000 W, and a reaction chamber to which a source power of 1000 to 5000 W and a bias power of 0 W are applied, and a flow rate of N2 500 to 2000 sccm and He 100 to 500 sccm. It is formed into a multilayer structure by using a multi-step HDP CVD (high density plasma chemical vapor deposition) method of repeating the second process of forming an interface by flowing. Here, the interface serves to suppress the growth of the void formed in the first step.

그 다음, 비트라인 마스크(도시안됨)를 이용한 사진식각공정으로 상기 하드마스크층(21), 텅스텐층(19) 및 확산방지막(15)을 식각하여 비트라인을 형성한다.Next, the hard mask layer 21, the tungsten layer 19, and the diffusion barrier 15 are etched by a photolithography process using a bit line mask (not shown) to form bit lines.

전체표면상부에 HDP CVD ( high density plasma chemical vapor deposition ) 방법으로 제2층간절연막인 산화막(23)을 형성한다.An oxide film 23 as a second interlayer insulating film is formed on the entire surface by HDP CVD (high density plasma chemical vapor deposition).

도 2b를 참조하면, 상기 제2층간절연막인 산화막(23)을 평탄화식각하여 상기 하드마스크층인 질화막(21)을 노출시킨다. 여기서, 상기 평탄화식각공정은 CMP 방법으로 실시한다.Referring to FIG. 2B, the oxide layer 23, which is the second interlayer insulating layer, is planarized and etched to expose the nitride layer 21, which is the hard mask layer. Here, the planarization etching process is performed by the CMP method.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 비트라인 형성방법은, 다단계의 HDP CVD 방법으로 다층구조의 질화막을 형성하여 하드마스크층으로 사용함으로써 비트라인 콘택홀 내의 보이드 크기를 감소시켜 후속 평탄화식각공정시 보이드의 노출을 방지할 수 있고, 상기 하드마스크층을 다단계로 형성하여 핀홀의 유발을 방지할 수 있어 그에 따른 특성 열화를 방지하고 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of forming a bit line of a semiconductor device according to the present invention, a nitride film having a multi-layer structure is formed by using a multi-step HDP CVD method and used as a hard mask layer to reduce the size of voids in the bit line contact hole and subsequently planar etching. It is possible to prevent the exposure of the void during the process, it is possible to prevent the occurrence of pinholes by forming the hard mask layer in a multi-stage, thereby preventing the deterioration of characteristics and improve the characteristics and reliability of the semiconductor device. .

Claims (4)

비트라인 콘택플러그가 구비되는 반도체기판 상에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on a semiconductor substrate provided with a bit line contact plug; 비트라인 콘택마스크를 이용하여 상기 비트라인 콘택플러그를 노출시키는 비트라인 콘택홀을 형성하는 공정과,Forming a bit line contact hole exposing the bit line contact plug by using a bit line contact mask; 상기 비트라인 콘택홀을 포함한 전체표면상부에 비트라인용 도전층을 증착하는 공정과,Depositing a conductive layer for bit lines on the entire surface including the bit line contact holes; 상기 비트라인용 도전층 상에 고밀도 플라즈마 화학기상증착 ( HDP CVD ) 방법의 하드마스크층을 다층구조로 형성하는 공정을 포함하는 반도체소자의 비트라인 형성방법.And forming a hard mask layer of a high density plasma chemical vapor deposition (HDP CVD) method in a multilayered structure on the bit line conductive layer. 제 1 항에 있어서,The method of claim 1, 상기 비트라인용 도전층은 텅스텐층인 것을 특징으로 하는 반도체소자의 비트라인 형성방법.And the bit line conductive layer is a tungsten layer. 제 1 항에 있어서,The method of claim 1, 상기 하드마스크층은 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.And said hard mask layer is formed of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 하드마스크층은 SiH4 30∼70 sccm, NH4 40∼150 sccm, N2 500∼2000 sccm, He 100 ~ 500 sccm 의 유량을 이용하여 2 ~ 5 mTorr 의 압력하에서 1000∼5000 W 의 소오스 전력 및 1000∼2000 W 의 바이어스 전력으로 질화막을 형성하는 제1공정과, 1000∼5000 W 의 소오스 전력 및 0 W 의 바이어스 전력이 인가되는 반응실로 N2 500∼2000 sccm, He 100 ~ 500 sccm의 유량을 플로우시켜 계면을 형성하는 제2공정을 반복 실시하는 다단계의 HDP CVD ( high density plasma chemical vapor deposition ) 방법을 이용하여 다층구조로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.The hard mask layer is made of SiH4 30-70 sccm, NH4 40-150 sccm, N2 500-2000 sccm, He 100-500 sccm using a source power of 1000-5000 W and 1000-5000 W under a pressure of 2-5 mTorr. A first process of forming a nitride film with a bias power of 2000 W, and a flow rate of N2 500 to 2000 sccm, He 100 to 500 sccm into a reaction chamber to which a source power of 1000 to 5000 W and a bias power of 0 W are applied to the interface. And forming a multilayer structure by using a multi-step HDP CVD method which repeats the second process of forming a film.
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KR20200047292A (en) * 2018-10-23 2020-05-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Slot contacts and method forming same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200047292A (en) * 2018-10-23 2020-05-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Slot contacts and method forming same
US10943829B2 (en) 2018-10-23 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Slot contacts and method forming same
US11532518B2 (en) 2018-10-23 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Slot contacts and method forming same

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