KR100545699B1 - Method for forming plug for capacitor contact of semiconductor device - Google Patents

Method for forming plug for capacitor contact of semiconductor device Download PDF

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KR100545699B1
KR100545699B1 KR1019990066437A KR19990066437A KR100545699B1 KR 100545699 B1 KR100545699 B1 KR 100545699B1 KR 1019990066437 A KR1019990066437 A KR 1019990066437A KR 19990066437 A KR19990066437 A KR 19990066437A KR 100545699 B1 KR100545699 B1 KR 100545699B1
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plug
forming
polysilicon
diffusion barrier
polysilicon plug
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KR1019990066437A
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Korean (ko)
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KR20010059058A (en
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오찬권
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

본 발명은 반도체 제조 기술에 관한 것으로, 리세스된 폴리실리콘 플러그 구조를 형성함에 있어서, 확산방지막 증착 공정을 용이하게 할 수 있는 반도체 소자의 캐패시터 콘택용 플러그 형성방법을 제공하는데 그 목적이 있다. 본 발명의 특징적인 반도체 소자의 캐패시터 콘택용 플러그 형성방법은, 소정의 하부층 상에 층간절연막을 형성하는 제1 단계; 상기 층간절연막을 선택 식각하여 캐패시터 콘택홀을 형성하는 제2 단계; 상기 제3 단계를 마친 전체 구조 상부에 폴리실리콘막을 형성하는 제3 단계; 화학적·기계적 연마법을 사용하여 상기 콘택홀 내에 폴리실리콘 플러그를 형성하는 제4 단계; 상기 폴리실리콘 플러그를 습식 식각하여 리세스된 폴리실리콘 플러그를 형성하는 제5 단계; 및 상기 제5 단계 수행 후, 상기 콘택홀의 나머지 부분에 확산방지막을 매립하는 제6 단계를 포함하여 이루어진다. 즉, 본 발명은 폴리실리콘 증착후 CMP를 실시함으로써 갈라짐(seam)이 제거된 1차 폴리실리콘 플러그를 얻고, 이후 1차 폴리실리콘 플러그의 일부를 습식 식각하여 균일하게 리세스된 2차 폴리실리콘 플러그를 형성한 다음, 확산방지막을 콘택홀의 나머지 부분에 매립하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and to provide a method for forming a plug for a capacitor contact of a semiconductor device which can facilitate a diffusion barrier film deposition process in forming a recessed polysilicon plug structure. A method of forming a plug for a capacitor contact of a semiconductor device of the present invention includes a first step of forming an interlayer insulating film on a predetermined lower layer; Selectively etching the interlayer insulating layer to form a capacitor contact hole; A third step of forming a polysilicon film on the entire structure after the third step; A fourth step of forming a polysilicon plug in the contact hole using a chemical mechanical polishing method; Wet etching the polysilicon plug to form a recessed polysilicon plug; And a sixth step of embedding the diffusion barrier in the remaining portion of the contact hole after performing the fifth step. That is, the present invention obtains a primary polysilicon plug from which seam is removed by performing CMP after polysilicon deposition, and then a second recessed polysilicon plug uniformly recessed by wet etching a part of the primary polysilicon plug. After forming the film, the diffusion barrier is embedded in the rest of the contact hole.

콘택 플러그, 리세스된 폴리실리콘 플러그, 확산방지막, 갈라짐Contact Plug, Recessed Polysilicon Plug, Diffusion Barrier, Split

Description

반도체 소자의 캐패시터 콘택용 플러그 형성방법{A method of forming plug for capacitor contact} A method of forming plug for capacitor contact             

도 1a 및 도 1b는 종래기술에 따른 캐패시터 콘택용 플러그 형성 공정도.1A and 1B show a process for forming a plug for a capacitor contact according to the prior art;

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 캐패시터 콘택용 플러그 형성 공정도.2A to 2C are diagrams illustrating a plug forming process for a capacitor contact according to an exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 하부층 21 : 층간절연막20: lower layer 21: interlayer insulating film

22 : 반사방지막 23 : 폴리실리콘막22: antireflection film 23: polysilicon film

23a : 폴리실리콘 플러그 23b : 리세스된 폴리실리콘 플러그23a: polysilicon plug 23b: recessed polysilicon plug

24 : 확산방지막24: diffusion barrier

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 캐패시터 콘택용 플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming a plug for a capacitor contact of a semiconductor device.

반도체 소자의 고집적화에 따라 디자인 룰(design rule)의 축소가 가속되고 있으며, 이에 따라 층간의 수직 배선을 위한 콘택홀의 단차비(aspect ratio)가 증가고 있다. 이러한 콘택홀의 단차비 증가는 콘택 매립 물질의 매립 특성을 악화시켜 보이드(void) 등의 열화를 초래하게 되며, 이러한 콘택 매립 물질의 매립 특성을 고려하여 매립 특성이 우수한 폴리실리콘을 플러그 물질로 사용하고 있다.As semiconductor devices become more integrated, reduction of design rules is accelerating, and accordingly, the aspect ratio of contact holes for vertical interconnection between layers is increasing. Increasing the step ratio of the contact hole deteriorates the embedding characteristics of the contact embedding material, resulting in deterioration of voids, etc. In consideration of the embedding characteristics of the contact filling material, polysilicon having excellent filling characteristics is used as a plug material. have.

한편, 고유전체 캐패시터나 강유전체 캐패시터는 하부 전극(스토리지 노드)이 금속으로 형성되며, 유전체 특성을 개선하기 위한 후속 열처리 공정시 산소 침투를 대비하여 리세스형 폴리실리콘 플러그와 함께 확산방지막을 적용하고 있다.On the other hand, in the high dielectric capacitor or ferroelectric capacitor, the lower electrode (storage node) is formed of a metal, and a diffusion barrier is applied together with a recessed polysilicon plug in preparation for oxygen penetration in a subsequent heat treatment process to improve dielectric properties. .

첨부된 도면 도 1a 및 도 1b는 종래기술에 따른 캐패시터 콘택용 플러그 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A and 1B illustrate a process of forming a plug for a capacitor contact according to the prior art, which will be described below with reference to the drawing.

종래기술에 따른 캐패시터 콘택용 플러그 형성 공정은, 우선 도 1a에 도시된 바와 같이 모스 트랜지스터, 비트라인 등을 포함하는 소정의 하부층(10) 상에 비트라인과 캐패시터의 절연을 위한 층간절연막(11) 및 반사방지막(12)을 증착하고, 이를 선택 식각하여 캐패시터 콘택홀을 형성한 다음, 전체 구조 상부에 도핑된 폴리실리콘막(13)을 증착하여 콘택홀을 매립한다.In the plug forming process for a capacitor contact according to the related art, first, as shown in FIG. 1A, an interlayer insulating film 11 for insulating a bit line and a capacitor on a predetermined lower layer 10 including a MOS transistor, a bit line, and the like is shown. And an anti-reflection film 12 is deposited, and selectively etched to form a capacitor contact hole, and then a doped polysilicon film 13 is deposited on the entire structure to fill the contact hole.

다음으로, 도 1b에 도시된 바와 같이 폴리실리콘막(13)의 에치백(etchback) 공정을 실시하여 리세스형 폴리실리콘 플러그(13a)를 형성한 다음, 확산방지막(14)을 증착하여 콘택홀의 나머지 부분을 매립하고, 확산방지막(14)의 화학적·기계적 연마(CMP) 공정을 실시하여 층간절연막(11) 상부의 확산방지막(14)을 제거한다.Next, as illustrated in FIG. 1B, an etchback process of the polysilicon film 13 is performed to form a recessed polysilicon plug 13a, and then a diffusion barrier 14 is deposited to form a contact hole. The remaining portion is buried and the diffusion barrier 14 is subjected to a chemical and mechanical polishing (CMP) process to remove the diffusion barrier 14 on the interlayer insulating film 11.

그런데, 상기와 같은 종래기술은 리세스형 폴리실리콘 플러그(13a)를 형성하기 위한 폴리실리콘막(13)의 에치백을 진행할 때 폴리실리콘막(13) 증착시 형성된 갈라짐(seam)(A)에 의해 폴리실리콘 플러그(13a)의 중앙 부분에서 식각 속도가 빨라진다. However, the above-described conventional technique is applied to cracks (A) formed during deposition of the polysilicon film 13 when the polysilicon film 13 is etched back to form the recessed polysilicon plug 13a. This speeds up the etching rate at the central portion of the polysilicon plug 13a.

이러한 현상은 500Å 정도의 폴리실리콘 플러그(13a) 리세스 프로파일을 확보하기 위한 과도 식각에 의해 더욱 심화되어 후속 확산방지막(14) 증착시 증착 타겟을 증가시켜야 하는 문제점을 유발한다.This phenomenon is further exacerbated by excessive etching to secure the recess profile of the polysilicon plug 13a of about 500 Å, which causes a problem of increasing the deposition target during subsequent deposition of the diffusion barrier 14.

일반적으로, 확산방지막(14)으로는 Ti, TiN, TiAIN, TiSiN, TaN, WN, TiSi2 등을 사용하며, 스퍼터링법으로 증착하는데, 상기와 같은 폴리실리콘 플러그(13a)가 형성된 콘택홀의 나머지 부분을 완전히 매립하기 위해서는 2000Å 이상의 두께로 증착하는 것을 요구한다. 이러한 확산방지막(14)의 증착을 위해서는 웨이퍼 1장당 20분 이상의 증착시간이 요구되며, 한 단계의 증착으로 충분한 매립 특성을 얻기 힘들기 때문에 이를 여러 번 반복하여 증착하게 된다. 이와 같은 장시간의 스퍼터링은 기판에 스트레스(stress)를 가하게 되어 소자 특성을 열화시키는 결과를 초래한다.In general, as the diffusion barrier 14, Ti, TiN, TiAIN, TiSiN, TaN, WN, TiSi 2 , and the like are deposited by sputtering, and the rest of the contact hole in which the polysilicon plug 13a is formed as described above is used. In order to completely fill the film, it is required to deposit a thickness of 2000Å or more. In order to deposit the diffusion barrier 14, a deposition time of 20 minutes or more per wafer is required, and since it is difficult to obtain sufficient embedding characteristics by one step of deposition, the deposition is repeated several times. Such long sputtering causes stress on the substrate, resulting in deterioration of device characteristics.

본 발명은 리세스된 폴리실리콘 플러그 구조를 형성함에 있어서, 확산방지막 증착 공정을 용이하게 할 수 있는 반도체 소자의 캐패시터 콘택용 플러그 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a plug for a capacitor contact of a semiconductor device, which may facilitate a diffusion barrier film deposition process in forming a recessed polysilicon plug structure.

상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 캐패시터 콘택용 플러그 형성방법은, 소정의 하부층 상에 층간절연막을 형성하는 제1 단계; 상기 층간절연막을 선택 식각하여 캐패시터 콘택홀을 형성하는 제2 단계; 상기 제3 단계를 마친 전체 구조 상부에 폴리실리콘막을 형성하는 제3 단계; 화학적·기계적 연마법을 사용하여 상기 콘택홀 내에 폴리실리콘 플러그를 형성하는 제4 단계; 상기 폴리실리콘 플러그를 습식 식각하여 리세스된 폴리실리콘 플러그를 형성하는 제5 단계; 및 상기 제5 단계 수행 후, 상기 콘택홀의 나머지 부분에 확산방지막을 매립하는 제6 단계를 포함하여 이루어진다.SUMMARY OF THE INVENTION In order to solve the above technical problem, a method of forming a plug for a capacitor contact of a semiconductor device according to the present invention may include a first step of forming an interlayer insulating film on a predetermined lower layer; Selectively etching the interlayer insulating layer to form a capacitor contact hole; A third step of forming a polysilicon film on the entire structure after the third step; A fourth step of forming a polysilicon plug in the contact hole using a chemical mechanical polishing method; Wet etching the polysilicon plug to form a recessed polysilicon plug; And a sixth step of embedding the diffusion barrier in the remaining portion of the contact hole after performing the fifth step.

즉, 본 발명은 폴리실리콘 증착후 CMP를 실시함으로써 갈라짐(seam)이 제거된 1차 폴리실리콘 플러그를 얻고, 이후 1차 폴리실리콘 플러그의 일부를 습식 식각하여 균일하게 리세스된 2차 폴리실리콘 플러그를 형성한 다음, 확산방지막을 콘택홀의 나머지 부분에 매립하는 기술이다.That is, the present invention obtains a primary polysilicon plug from which seam is removed by performing CMP after polysilicon deposition, and then a second recessed polysilicon plug uniformly recessed by wet etching a part of the primary polysilicon plug. After forming the film, the diffusion barrier is embedded in the rest of the contact hole.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 캐패시터 콘택용 플러그 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2C illustrate a process of forming a plug for a capacitor contact according to an exemplary embodiment of the present invention, which will be described below with reference to the drawings.

본 실시예에 따른 캐패시터 콘택용 플러그 형성 공정은, 우선 도 2a에 도시 된 바와 같이 모스 트랜지스터, 비트라인 등을 포함하는 소정의 하부층(20) 상에 비트라인과 캐패시터의 절연을 위한 층간절연막(21) 및 반사방지막(22)을 증착하고, 이를 선택 식각하여 캐패시터 콘택홀을 형성한 다음, 전체 구조 상부에 도핑된 폴리실리콘막(23)을 증착하여 콘택홀을 매립한다. 이때, 반사방지막(22)은 저압화학기상증착법 또는 플라즈마화학기상증착법을 사용하여 SiON, Si-리치(5∼20%) SiON을 300∼700℃에서 200∼1000Å 두께로 증착하며, 폴리실리콘막(23)은 도핑된 폴리실리콘막을 400∼1200℃에서 50∼500Å 두께로 증착한다.In the plug forming process for a capacitor contact according to the present embodiment, first, as shown in FIG. 2A, an interlayer insulating film 21 for insulating a bit line and a capacitor is formed on a predetermined lower layer 20 including a MOS transistor, a bit line, and the like. ) And the anti-reflection film 22 are deposited, and selectively etched to form a capacitor contact hole, and then the doped polysilicon film 23 is deposited on the entire structure to fill the contact hole. At this time, the anti-reflection film 22 deposits SiON and Si-rich (5-20%) SiON at 200-1000 Å thickness at 300-700 ° C. using low pressure chemical vapor deposition or plasma chemical vapor deposition. 23) deposits a doped polysilicon film at a thickness of 50 to 500 mm3 at 400 to 1200 ° C.

다음으로, 도 2b에 도시된 바와 같이 폴리실리콘막(23)의 CMP 공정을 실시한다. 이때, CMP 공정은 반사방지막(22)을 연마정지막으로 하여 수행함으로써 콘택홀을 완전히 매립하는 폴리실리콘 플러그(23a)가 형성되도록 한다. 이때, CMP 공정은 50∼500nm 입자 크기를 가지는 실리카, 세리아, 알루미나 계열 슬러리를 pH 5∼11로 유지시키면서 진행하며, CMP 후 형성된 폴리실리콘 플러그(23a)에는 상기 도 2a에 도시된 갈라짐(A)이 나타나지 않는다.Next, as shown in FIG. 2B, a CMP process of the polysilicon film 23 is performed. In this case, the CMP process is performed by using the anti-reflection film 22 as the polishing stop film so that the polysilicon plug 23a filling the contact hole is completely formed. At this time, the CMP process is carried out while maintaining a silica, ceria, alumina-based slurry having a particle size of 50 ~ 500nm at pH 5 ~ 11, the polysilicon plug (23a) formed after the CMP crack (A) shown in Figure 2a Does not appear.

계속하여, 도 2c에 도시된 바와 같이 질산, 불산 및 초산의 혼합 용액을 식각제로 사용하여 폴리실리콘 플러그(23a)를 400∼1000Å 타겟으로 리세싱한다. 이때, 균일하게 리세스된 폴리실리콘 플러그(23b)를 얻을 수 있다. 이어서, 전체 구조 상부에 확산방지막(24)을 증착하고, 반사방지막(22)을 연마정지막으로 하여 CMP 공정을 실시함으로써 안정된 캐패시터 콘택용 플러그 구조를 형성할 수 있다. 이때, 확산방지막(24)은 Ti, TiN, TiAIN, TiSiN, TaN, WN, TiSi2 등을 단일막으로 또는 적층 구조로 사용하여 400∼2000Å 두께로 증착하며, CMP 공정은 50∼500nm 입 자 크기를 가지는 실리카, 세리아, 알루미나 계열 슬러리를 H202, FeNO3과 같은 산화제로 pH 2∼6으로 유지시키면서 진행한다.Subsequently, as shown in FIG. 2C, the polysilicon plug 23a is recessed to a 400 to 1000 GPa target using a mixed solution of nitric acid, hydrofluoric acid and acetic acid as an etchant. At this time, the polysilicon plug 23b uniformly recessed can be obtained. Subsequently, the diffusion barrier film 24 is deposited over the entire structure, and the CMP process is performed by using the anti-reflection film 22 as the polishing stop film to form a stable capacitor contact plug structure. At this time, the diffusion barrier 24 is deposited to a thickness of 400 ~ 2000Å by using Ti, TiN, TiAIN, TiSiN, TaN, WN, TiSi 2, etc. as a single film or a laminated structure, CMP process 50 ~ 500nm particle size Silica, ceria, and alumina-based slurry having the proceeds while maintaining the pH 2 to 6 with an oxidizing agent such as H 2 O 2 , FeNO 3 .

상기한 바와 같이 본 발명은 폴리실리콘 증착후 CMP를 실시함으로써 갈라짐(seam)이 제거된 1차 폴리실리콘 플러그를 얻고, 이후 1차 폴리실리콘 플러그의 일부를 습식 식각하여 균일하게 리세스된 2차 폴리실리콘 플러그를 형성한 다음, 확산방지막을 콘택홀의 나머지 부분에 매립한다. 이로 인하여 리세스 깊이의 조절이 용이하고, 확산방지막의 원-스텝(one step) 증착이 가능하여 기판에 가해지는 스트레스를 감소시킬 수 있으며, 확산방지막 증착을 용이하게 하고, 그 증착 시간을 1/4 정도로 감소시킬 수 있다.As described above, the present invention obtains the primary polysilicon plug from which seam has been removed by performing CMP after polysilicon deposition, and then uniformly recessed secondary poly by wet etching part of the primary polysilicon plug. After the silicon plug is formed, the diffusion barrier is embedded in the rest of the contact hole. This makes it easy to control the depth of the recess, to enable one-step deposition of the diffusion barrier, to reduce the stress on the substrate, to facilitate the deposition of the diffusion barrier, and to reduce the deposition time by 1 /. Can be reduced to four.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 폴리실리콘 플러그의 리세스 깊이의 조절이 용이하고, 확산방지막의 원-스텝 증착이 가능하여 기판에 가해지는 스트레스를 감소시킴으로써 소자 특성을 개선하는 효과가 있으며, 확산방지막 증착을 용이하게 하고 증착 시간을 감소시킴으로써 공정 안정화 및 단가 절감(cost down)이라는 이중 효과를 얻을 수 있다.According to the present invention, the recess depth of the polysilicon plug can be easily controlled, the one-step deposition of the diffusion barrier can be performed, and the stress on the substrate can be reduced, thereby improving device characteristics, and the diffusion barrier can be easily deposited. In this case, the dual effect of process stabilization and cost down can be achieved.

Claims (5)

소정의 하부층 상에 층간절연막을 형성하는 제1 단계;A first step of forming an interlayer insulating film on a predetermined lower layer; 상기 층간절연막을 선택 식각하여 캐패시터 콘택홀을 형성하는 제2 단계;Selectively etching the interlayer insulating layer to form a capacitor contact hole; 상기 제3 단계를 마친 전체 구조 상부에 폴리실리콘막을 형성하는 제3 단계;A third step of forming a polysilicon film on the entire structure after the third step; 화학적·기계적 연마법을 사용하여 상기 콘택홀 내에 폴리실리콘 플러그를 형성하는 제4 단계;A fourth step of forming a polysilicon plug in the contact hole using a chemical mechanical polishing method; 상기 폴리실리콘 플러그를 습식 식각하여 리세스된 폴리실리콘 플러그를 형성하는 제5 단계; 및Wet etching the polysilicon plug to form a recessed polysilicon plug; And 상기 제5 단계 수행 후, 상기 콘택홀의 나머지 부분에 확산방지막을 매립하는 제6 단계A sixth step of embedding the diffusion barrier in the remaining portion of the contact hole after performing the fifth step; 를 포함하여 이루어진 반도체 소자의 캐패시터 콘택용 플러그 형성방법.Plug formation method for a capacitor contact of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제4 단계는,The fourth step, 50∼500nm 입자 크기를 가지는 실리카, 세리아, 알루미나 계열 슬러리 중 어느 하나를 사용하며, 산도(pH) 5∼11로 유지시키면서 진행하는 것을 특징으로 하는 반도체 소자의 캐패시터 콘택용 플러그 형성방법.A method of forming a plug for a capacitor contact of a semiconductor device, wherein any one of silica, ceria, and alumina-based slurries having a particle size of 50 to 500 nm is used, and is maintained at an acidity (pH) of 5 to 11. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제5 단계에서,In the fifth step, 상기 폴리실리콘 플러그가 400∼1000Å만큼 리세스되는 것을 특징으로 하는 반도체 소자의 캐패시터 콘택용 플러그 형성방법.And the polysilicon plug is recessed by 400 to 1000 Å. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제6 단계는,The sixth step, 상기 제5 단계를 마친 전체 구조 상부에 확산방지막을 400∼2000Å 두께로 증착하는 제7 단계와,A seventh step of depositing a diffusion barrier layer on the entire structure after the fifth step with a thickness of 400 to 2000 Å; 상기 확산방지막의 화학적·기계적 연마를 실시하는 제8 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 콘택용 플러그 형성방법.And forming an eighth step of chemically and mechanically polishing the diffusion barrier layer. 제4항에 있어서,The method of claim 4, wherein 상기 제8 단계의 상기 화학적·기계적 연마는,The chemical and mechanical polishing of the eighth step, 50∼500nm 입자 크기를 가지는 실리카, 세리아, 알루미나 계열 슬러리 중 어느 하나를 사용하며, 산도(pH) 2∼6으로 유지시키면서 진행하는 것을 특징으로 하는 반도체 소자의 캐패시터 콘택용 플러그 형성방법.A method for forming a capacitor contact plug for a semiconductor device, wherein any one of silica, ceria, and alumina-based slurries having a particle size of 50 to 500 nm is used, and is maintained at an acidity (pH) of 2 to 6.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10107227A (en) * 1996-07-30 1998-04-24 Internatl Business Mach Corp <Ibm> Manufacture of insulated gate field-effect transistor
KR19990005449A (en) * 1997-06-30 1999-01-25 김영환 Semiconductor memory device and manufacturing method thereof
JPH1174488A (en) * 1997-06-30 1999-03-16 Texas Instr Inc <Ti> Integrated circuit capacitor and memory
KR20010059188A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a contact plug of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10107227A (en) * 1996-07-30 1998-04-24 Internatl Business Mach Corp <Ibm> Manufacture of insulated gate field-effect transistor
KR19990005449A (en) * 1997-06-30 1999-01-25 김영환 Semiconductor memory device and manufacturing method thereof
JPH1174488A (en) * 1997-06-30 1999-03-16 Texas Instr Inc <Ti> Integrated circuit capacitor and memory
KR20010059188A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a contact plug of semiconductor device

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