JP4987796B2 - Manufacturing method of semiconductor device - Google Patents

Description

    The present invention relates to a method for manufacturing a semiconductor device having a silicon nitride film or a silicon oxide film.

Along with the trend of high integration and miniaturization, in next-generation semiconductor devices, an interlayer insulating film (SiO ₂ film) having a connection hole with a finer and higher aspect ratio is formed and connected on this interlayer insulating film. It is possible to form a silicon nitride film that is homogeneous and has good coverage in the hole, and is embedded in accordance with the design value in the polishing process by chemical mechanical polishing (CMP) of the next silicon nitride film. Process technology capable of realizing a surface with high shape and flatness is essential.

  This type of technique is used, for example, when forming an element structure as shown in FIG. FIG. 37 shows a cross section of a MOS transistor of a DRAM cell cut in a direction perpendicular to the channel length direction.

In the figure, reference numeral 681 denotes a silicon substrate, and a drain diffusion layer 682 is formed on the surface of the silicon substrate 681. On the silicon substrate 681, an interlayer insulating film (SiO ₂ film) 685 having a contact hole 683 for the drain diffusion layer 682 and a wiring groove 684 connected to the drain diffusion layer 682 via the contact hole 683 is formed.

  A buried wiring 686 made of tungsten is formed inside the contact hole 683 and the wiring groove 684. A silicon nitride film 687 is formed on the side wall of the contact hole 683 and the wiring groove 684 where the embedded wiring 686 is embedded.

  Here, the embedded wiring 686 is formed in the entire interior with respect to the contact hole 683, but the wiring groove 684 is formed only to a midway depth. A silicon nitride film 688 is embedded in a portion not embedded by the embedded wiring 686.

  This type of silicon nitride film 688 is called a cap insulating film. The purpose of the cap insulating film is to prevent a short circuit between the lower capacitor electrode 689 and the embedded wiring 686 formed thereon.

The cap insulating film is formed when a contact hole for a capacitor, that is, a connection hole for connecting the lower capacitor electrode to the n ⁺ type source diffusion layer is formed in the interlayer insulating film (SiO ₂ film) 685 by RIE (Reactive Ion Etching). Used as a mask. For this purpose, a silicon nitride film 688 having a selective ratio is used for the cap insulating film.

  On the bottom surface of the contact hole 683, a Ti / TiN laminated film 690 is formed as a barrier metal film so that the drain diffusion layer 682 and the buried wiring 686 do not react with each other in a subsequent heat process.

  When the wiring trench 684 has an aspect ratio of 1 or more, a silicon nitride film (DCS-) is formed by a low pressure chemical vapor deposition method (LPCVD method), which is a CVD method with good step coverage using dichlorosilane (DCS) as a Si raw material. SiN film) 688 was formed.

  However, the forming method described above has the following problems.

The polishing rate by CMP of the interlayer insulating film (SiO ₂ film) 685 with respect to the DCS-SiN film 688 (polishing rate of the interlayer insulating film 685 / polishing rate of the DCS-SiN film 688) is about 30 and not high.

  Therefore, in the step of removing the excess DCS-SiN film 688 outside the wiring trench 684 by CMP, the interlayer insulating film 685 does not function as a polishing stop surface, and the DCS-SiN film 688 is excessively polished.

  As a result, as shown in FIG. 38, the thickness of the DCS-SiN film 688 becomes thinner than the design value, so that the leakage current between the embedded wiring 686 and the lower capacitor electrode 689 increases or the breakdown voltage decreases. Problems occur.

  Further, when the contact hole of the capacitor is opened by etching, the DCS-SiN film 688 is used as a mask. However, when excessive polishing as described above occurs, in the worst case, as shown in FIG. This causes a problem that the embedded wiring 686 and the lower capacitor electrode 689 are short-circuited.

  In recent years, demands for higher integration and higher speed of semiconductor devices are increasing. In order to realize these requirements, reduction in the size and miniaturization between elements and element dimensions are being promoted, while the resistance of the embedded wiring is reduced and the parasitic capacitance is reduced.

  For example, in a DRAM, the progress of high integration is remarkable, and in order to form a contact hole, it is necessary to form a narrow step shape with a large aspect ratio.

  For this reason, for example, in a DRAM, a silicon nitride film (SiN film) having a high selection ratio has been used as an etching stopper film for RIE of an interlayer insulating film (TEOS oxide film or the like) when forming a contact hole. .

  The SiN film used as this kind of etching stopper film (RIE stopper film) needs to have a sufficiently high RIE selectivity relative to a silicon oxide film such as a BPSG film or a TEOS film. Furthermore, with the high integration and miniaturization of elements, it is necessary to uniformly and uniformly cover narrow stepped shapes with more severe aspects.

  In order to satisfy these requirements, as a RIE stopper film at the time of forming a contact hole, a relatively dense SiN formed by LPCVD at about 780 ° C. using dichlorosilane (DCS) and ammonia as raw materials. Membranes have been used.

  The SiN film formed by this method has a high RIE selectivity of the TEOS film to the SiN film when RIE of the TEOS film is about 7 and the dielectric constant of the SiN film is about 7.5.

  However, the dielectric constant of 7.5 is relatively large. In recent years, in particular, the capacitance of the RIE stopper film has come to influence the inter-wiring capacitance or RC delay time of the entire device as the element size is reduced. In DRAMs of the 0.18 micron generation and later, the capacitance of the RIE stopper film is increased. Has appeared as a delay in the operating speed of the device.

  Further, the use of such a SiN film as an RIE stopper film leads to an increase in bit line capacitance, and it is necessary to make a capacitor with a large capacity to compensate for this, which is disadvantageous in terms of device characteristics.

  Furthermore, from the viewpoint of the manufacturing process, when an SiN film is used as the RIE stopper film, the RIE gas condition is switched to a condition that allows the SiN film to be etched after an opening is formed in an oxide film such as a BPSG film or a TEOS film. Need to be done.

  However, in this case, since the aspect ratio of the opening is large and the opening diameter is small, in-plane uniformity at the time of RIE with respect to the SiN film on the bottom of the opening cannot be sufficiently obtained, and the residue of the SiN film tends to remain on the bottom. In addition, since the silicon substrate is directly exposed to RIE, there is a concern that the substrate may be damaged, there is a concern that sufficient over-etching cannot be performed, the SiN film remains, and a contact failure may occur.

  Further, in the next step, dilute hydrofluoric acid treatment for removing the natural oxide film at the contact portion is performed. However, the DCS-SiN film formed using dichlorosilane (DCS) as a raw material at 780 ° C. is diluted with hydrofluoric acid (1/200). ) Is about 0.2 (nm / min), slower than the etching rate of about 1 (nm / min) of the natural oxide film, and the above-mentioned natural oxide film cannot be removed by the dilute hydrofluoric acid process. there were.

  On the other hand, since a high processing speed is required in a logic device, it is necessary to reduce so-called RC delay time, that is, to reduce capacitance between wirings and wiring resistance. In order to reduce the resistance of the wiring, the use of a copper (Cu) wiring as a metal wiring has been studied. In order to use the Cu wiring, a barrier layer that prevents oxidation of the Cu wiring and diffusion of Cu in the Cu wiring is necessary. Currently, an SiN film is being studied as one of the barrier layers.

  FIG. 40 shows an example of a structure in which a SiN film is formed as a barrier layer on a Cu wiring. In the figure, 701 is a TEOS oxide film, 702 is a TaN film, 703 is a Cu wiring, and 704 is a SiN film. Here, even in the case of using the Cu wiring technology, Al wiring is partially used in a portion where the pitch between the wirings is narrow in order to reduce the RC component between the wirings. Therefore, the SiN film 704 to be formed in a later step needs to be formed at a temperature not exceeding 450 ° C. which is the Al reflow temperature. In addition, a low dielectric film (usually referred to as a low-k film) such as (f) SG (fluorine-added silicate glass) is used for the interlayer insulating film already formed at the time of wiring formation in order to reduce the dielectric constant. Since these films are formed at a low temperature of 400 ° C. or lower, cracks may occur at 450 ° C. or higher. For these reasons, the SiN film 704 needs to be formed at a low temperature of 450 ° C. or lower, and is usually performed by plasma CVD, which can be easily formed at a low temperature.

  In semiconductor devices, with the miniaturization of elements, the aspect ratio of element isolation trenches and recesses between gate electrodes in the STI structure is increasing. With such an increase in aspect ratio, it has become increasingly difficult to embed an insulating film such as a silicon oxide film in a recess without creating a so-called “soot”.

Therefore, use of HDP (High-Density Plasma) -CVD method, TEOS-O ₃ -based CVD method or the like has been attempted. However, the former method has a problem of plasma damage to the base, a problem of non-uniform film quality, and a problem of low throughput. Further, the latter method has a problem that high-temperature treatment is required to improve film quality after film formation.

  As described above, an LPCVD method using dichlorosilane as a Si raw material has been proposed as a method for forming a silicon nitride film for embedding a wiring trench.

However, since the polishing rate by CMP of the interlayer insulating film (SiO ₂ film) with respect to the silicon nitride film (DCS-SiN film) formed by this method is about 30, the excess DCS-SiN film outside the wiring trench is removed by CMP. In the step of removing by this, there is a problem that the DCS-SiN film is excessively polished, resulting in an increase in leakage current between the buried wiring and the lower capacitor electrode.

  A first object of the present invention has been made in consideration of the above circumstances, and a semiconductor device having a silicon nitride film in which a covering ratio is not different from that of a conventional one and a selection ratio can be obtained with respect to a silicon oxide film, and It is in providing the manufacturing method.

  Further, as described above, the DCS-SiN film as the RIE stopper film was good in terms of the coverage ratio and the etching selection ratio. There is a problem that the etching rate is not large and the dielectric constant is relatively large from the viewpoint of reducing the capacitance between the wirings.

  The second object of the present invention has been made in consideration of the above circumstances, and has a low dielectric constant and a high etching rate with respect to dilute hydrofluoric acid, without changing the coverage and etching selectivity. An object of the present invention is to provide a semiconductor device having a silicon nitride film used as an etching stopper film used for etching an oxide film and a method for manufacturing the same.

In addition, a SiN film (plasma SiN film) formed using silane (SiH ₄ ) and ammonia (NH ₃ ) as raw materials by plasma CVD as a barrier film for Cu wiring has a relatively large dielectric constant of about 7. In addition, when a high temperature bias test was performed at 100 ° C. and 1 (MV / cm) using a plasma SiN film and Cu electrode formed at 370 ° C., an SiN diffusion / oxidation barrier against Cu required for maintaining a dielectric strength It was found that the thickness of the layer was about 100 nm. However, when such a SiN film having a large dielectric constant is used in the wiring portion with a thickness of 100 nm, the capacitance between the wirings is remarkably increased and the device characteristics are impaired.

  The third object of the present invention is to provide a semiconductor device having a low dielectric constant and a silicon nitride film used as a Cu barrier film, and a method for manufacturing the same, in view of the above circumstances. is there.

  Further, as described above, with the miniaturization of elements, it has become difficult to form a silicon oxide film excellent in embedding characteristics and film characteristics in a recess having a high aspect ratio.

  A fourth object of the present invention is to provide a semiconductor device capable of forming a silicon oxide film excellent in embedding characteristics and film characteristics in a recess having a high aspect ratio, and a method for manufacturing the same.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a main surface of a semiconductor substrate, a step of forming a contact hole reaching the main surface of the semiconductor substrate in the interlayer insulating film, and the contact Forming a silicon nitride film on the sidewall of the hole ; forming a barrier metal layer having a Ti layer and a TiN layer in the contact hole having the silicon nitride film formed on the sidewall; and forming the barrier metal layer. Forming a conductive layer in the contact hole, and using a mixed gas of Si _n Cl _{2n + 2} and NH ₃ (n is a natural number of 2 or more) , at a film forming temperature of 700 ° C. or less, the inside of the contact hole Forming a silicon nitride film containing chlorine on the conductive layer in the contact hole by an LPCVD method, and CMP Characterized by comprising a step of removing the silicon nitride film Kutohoru outside parts.
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a sidewall insulating film on a sidewall of a gate electrode formed on a semiconductor substrate via a gate insulating film, the semiconductor substrate, the sidewall insulating film, and the Forming a silicon nitride film by LPCVD at a film forming temperature of 700 ° C. or lower using a mixed gas of Si _n Cl _{2n + 2} and NH ₃ (n is a natural number of 2 or more) over the gate electrode; Forming an interlayer insulating film on the silicon nitride film; forming a contact hole reaching the silicon nitride film in the interlayer insulating film beside the gate electrode; and exposing the silicon nitride film exposed by the contact hole formation. And a removing step.

The method of manufacturing a semiconductor device according to the present invention is formed on a semiconductor substrate at a film forming temperature of 700 ° C. or lower using a mixed gas of Si _n Cl _{2n + 2} and NH ₃ (n is a natural number of 2 or more) . Forming a dummy gate having a first silicon nitride film, forming a first diffusion layer on the surface of the semiconductor substrate using the dummy gate as a mask, and using dichlorosilane on a side wall of the dummy gate. Forming a second silicon nitride film, forming a second diffusion layer on the surface of the semiconductor substrate using the dummy gate and the second silicon nitride film as a mask, and the second diffusion layer. Forming an interlayer insulating film on the semiconductor substrate on which the semiconductor layer is formed and the dummy gate; planarizing the interlayer insulating film using the first silicon nitride film as a stopper; and exposing by the planarizing process A step of removing the dummy gate, a step of forming a gate oxide film on the semiconductor substrate exposed by the removal of the dummy gate, and a step of forming a metal film on the gate oxide film. And

  A more specific configuration of the present invention is as follows.

(1) The silicon nitride film is excessive in silicon.

(2) Excess silicon with a nitrogen / silicon ratio of less than 1.33.

(3) The silicon nitride film is formed inside the trench. The aspect ratio of the groove is a high aspect ratio of 1 or more.

(4) A silicon nitride film having a chlorine concentration of 4 × 10 ²⁰ cm ⁻³ or more is formed by LPCVD using a compound containing Si—Si bonds and Si—Cl bonds as a Si raw material.

Specifically, a compound of Si _n Cl _{2n + 2} (n is a natural number of 2 or more) is used as the Si raw material. More specifically, Si ₂ Cl ₆ is used. Further, NH ₃ is used as a nitrogen source.

(5) A laminated film of a Ti film and a TiN film is used as the barrier metal film, and the deposition temperature of the silicon nitride film is set to 700 ° C. or lower. Further, the aspect ratio of the wiring groove is a high aspect ratio of 1 or more.

According to the study by the present inventors, in a method of forming a silicon nitride film using the LPCVD method, a compound containing Si—Si bonds and Si—Cl bonds such as Si ₂ Cl ₆ is used as a Si raw material. It was found that a silicon nitride film having a selective ratio with respect to polishing and etching with the silicon oxide film can be realized. Further, the coverage is not different from the conventional one because the LPCVD method which is a film forming method with good coverage is used.

Further, it has been found that when this type of Si raw material is used, the deposition rate of the silicon nitride film can be secured even at a low deposition temperature of 700 ° C. or lower. Therefore, a Ti / TiN film can be used as the barrier metal film. Further, the chlorine concentration of the silicon nitride film formed with such a Si raw material and the film forming temperature was 4 × 10 ²⁰ cm ⁻³ or more.

  Further, if the film formation temperature is 600 ° C. or less, a silicon-excess silicon nitride film can be formed. This type of silicon nitride film has a low density and a higher polishing rate than the silicon oxide film.

In order to achieve the second and third objects, the semiconductor device according to the present invention uses a silicon nitride film having a chlorine concentration of 1 × 10 ²¹ cm ⁻³ or more as an etching stopper film or a barrier film. It is characterized by.

In the method of forming a silicon nitride film using the LPCVD method, if a compound containing Si—Si bond and Si—Cl bond, such as Si ₂ Cl ₆ , is used as the Si raw material, etching with the silicon oxide film is performed. It was found that a silicon nitride film having a high selectivity can be realized.

The chlorine concentration of the silicon nitride film formed using such Si raw material was 1 × 10 ²¹ cm ⁻³ or more. Further, the coverage is not different from the conventional one because the LPCVD method which is a film forming method with good coverage is used. Further, it has been found that when this type of Si raw material is used, the dielectric constant of the silicon nitride film can be reduced, the etching rate of the silicon nitride film against dilute hydrofluoric acid can be increased, and the barrier property against Cu can be increased. This point will be further described in the section of the embodiment.

As described above in detail, according to the present invention, a compound containing Si—Si bond and Si—Cl bond as a Si raw material, and a LPCVD method as a film formation method can be used to obtain a selectivity with respect to a silicon oxide film. A silicon nitride film having a chlorine concentration of 4 × 10 ²⁰ cm ⁻³ or more can be realized.

Further, when the chlorine concentration is 1 × 10 ²¹ cm ⁻³ or more, the silicon oxide film etching with a low dielectric constant and a high etching rate with respect to dilute hydrofluoric acid is not changed as the coverage and etching selectivity. It becomes possible to realize a silicon nitride film that is used as an etching stopper film that is sometimes used and also used as a Cu barrier film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 and 2 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention. These drawings show a cross section of a MOS transistor of a DRAM cell cut in a direction perpendicular to the channel length direction.

First, as shown in FIG. 1A, an n-type drain diffusion layer 102 and the like are formed on a silicon substrate 101 by a known method to complete a MOS transistor, and then an interlayer insulating film (SiO ₂ film) 103 is formed. Form on the entire surface.

  Next, as shown in FIG. 1B, the interlayer insulating film 103 has a contact hole 104 for the n-type drain diffusion layer 102 and a wiring groove 5 connected to the n-type drain diffusion layer 102 through the contact hole 104. Then, a silicon nitride film 106 is formed on the entire surface.

  Next, as shown in FIG. 1C, the silicon nitride film 106 other than the sidewalls of the contact hole 104 and the wiring layer 105 is removed by RIE, and subsequently, a Ti layer 107 is formed on the substrate surface at the bottom of the contact hole 104 by ion implantation. Then, a TiN film 108 is formed on the entire surface by CVD.

  Next, as shown in FIG. 2D, a W buried wiring 109 that fills a portion from the bottom surface of the contact hole 104 to a depth in the middle of the wiring groove 105 is formed by selective growth of tungsten (W). A portion of the wiring trench 105 that is not buried with the W-embedded wiring 109 (hereinafter simply referred to as a trench) has a depth of 150 nm and a width of 150 nm. Therefore, the aspect ratio of the trench is 1.

In such a structure, a tungsten film as the W buried wiring 109 is formed on the entire surface, and then the excess tungsten film outside the contact hole 104 and the wiring trench 105 is removed by CMP, and then an interlayer insulating film (SiO _2). The film can also be obtained by forming a wiring groove on the wiring groove 105.

  The Ti layer 107 and the TiN film 108 formed on the bottom surface of the contact hole 104 function as a barrier metal film for preventing a reaction between the drain diffusion layer 102 and the W buried wiring 109 in a subsequent thermal process.

  The Ti layer 107 and the TiN film 108 cannot maintain their functions when subjected to heat treatment at a high temperature of 700 ° C. or higher for a long time due to heat resistance. Therefore, it is necessary to set the silicon nitride film 106 to have a film forming temperature of less than 700 ° C.

  The silicon nitride film 106 is formed using the LPCVD method. The reason is that the CVD method using plasma has a low coverage, so when the aspect ratio of the wiring groove 105 is 1 or more, a gap remains in the center of the wiring groove 105 as shown in FIG. This is because it cannot be secured. Another reason is that the silicon nitride film formed by the CVD method using plasma has no etching resistance under the silicon RIE condition and does not function as a mask.

  Even in the case of the LPCVD method, when a mixed gas of silane and ammonia is used as the source gas, there is a problem that the coverage is poor and the uniformity within the wafer surface is also poor. On the other hand, when a Si raw material in which hydrogen is replaced with chlorine, such as dichlorosilane or tetrachlorosilane, is used, the coverage is good, and the coverage can be 100% even when the aspect ratio is about 20. However, the LPCVD method using this type of source gas has the problems described in the prior art.

Next, as shown in FIG. 2E, after the TiN film 108 above the W buried wiring 109 is removed by wet etching, a mixed gas of Si ₂ Cl ₆ (hexachlorodisilane: HCD) and NH ₃ is used. A silicon nitride film (HCD-SiN film) 110 as a cap insulating film is formed on the entire surface so as to fill the inside of the trench by LPCVD using the above.

Here, the film forming temperature is 650 ° C., the reactor internal pressure is 0.5 Torr, and the flow rate ratio is NH ₃ / Si ₂ Cl ₆ = 2000 sccm / 20 sccm. The film forming speed under these film forming conditions is 2.7 nm / min.

  Finally, as shown in FIG. 2F, after removing excess HCD-SiN film 110 outside the trench by CMP and planarizing the surface, a lower capacitor electrode and a capacitor insulating film (not shown) are formed according to a well-known method. The upper capacitor electrode is formed to complete the DRAM memory cell.

The capacitor insulating film is an insulating film made of a metal oxide having a high dielectric constant such as Ba _x Sr _1-x TiO ₃ , and the lower and upper capacitor electrodes are metal oxides such as SrRuO ₃ that exhibit metal conductivity even when oxidized. A conductive film made of may be used. The capacitor insulating film and the upper and lower capacitor electrodes preferably have the same crystal structure, for example, a perovskite structure.

  In the CMP in this step, the slurry is made of silica having a small particle diameter, 2.5 wt% phosphoric acid and water, and the polishing pad load is 200 g weight.

  From the film thickness measurement result of the average of 9 points in the wafer surface after CMP, the polishing rate is about 60 nm / min for the DCS-SiN film, which is a conventional silicon nitride film, but about 90 nm for the HCD-SiN film 10. / Min. That is, according to the present embodiment, the selection ratio (silicon nitride film polishing rate / silicon oxide film polishing rate) can be increased from the conventional 30 to 45.

  Since the selection ratio can be increased in this way, polishing of the HCD-SiN film 110 by CMP stops at the interlayer insulating film 103, and the W buried wiring 109 is exposed even though the interlayer insulating film 3 is somewhat removed. This does not cause excessive polishing. Therefore, it becomes possible to realize a buried shape and high flatness processing as designed.

Further, according to the present embodiment, a high coverage equivalent to that of the conventional DCS-SiN film can be obtained. The reason is that the LPCVD method is used as the film forming method, so that the inside of the wiring trench 106 can be filled uniformly, and the Si ₂ Cl ₆ (chlorine of disilane) used as the Si raw material in this embodiment. Two of the reaction intermediates of chlorinated compounds such as) are considered to have a smaller adsorption probability than a complete hydride.

FIG. 3 shows the film formation temperature dependence of the chlorine concentration in a silicon nitride film (HCD-SiN film) formed by LPCVD using Si ₂ Cl ₆ as a Si raw material. Although not shown in the figure, the chlorine concentration in the silicon nitride film (DCS-SiN film) formed by LPCVD using a dichlorosilane as a Si raw material at a film forming temperature of 700 ° C. was 8 × 10 ¹⁹ . . The chlorine concentration is a value determined by secondary ion mass spectrometry (SIMS).

In this embodiment, the case where the film forming temperature is 650 ° C. has been described. However, when Si ₂ Cl ₆ is used as the Si raw material, the chlorine concentration is linearly about 1000 / T = 1.1 or more from FIG. Therefore, if the film formation temperature is set to 800 ° C. or lower, it is considered that the silicon nitride film 110 having a higher chlorine concentration can be formed than when dichlorosilane, which is a conventional Si raw material, is used. .

  However, when the silicon nitride film 110 is formed in the buried wiring portion as in the present embodiment, the heat resistance of the Ti film 107 and the TiN film 108 is not high at a temperature higher than 700 ° C. It is desirable to form a film.

  There are two main reasons why the HCD-SiN film has a higher Cl concentration than the DCS-SiN film. The first reason is that the HCD-SiN film has a higher film formation speed than the DCS-SiN film, and therefore, a shorter film formation time is required under the same temperature and the same film thickness conditions. This is because less Cl is lost from the film. The reason why the film formation speed differs between the HCD-SiN film and the DCS-SiN film is considered to be because the dissociation of the Si-Si bond works favorably in the film formation.

When roughly discussing the bond energy, the Si—Cl bond is the highest energy among the bond types conceivable when the 4.16 eV and HCD + NH ₃ system is used. Therefore, it is assumed that the DCS-SiN film and the HCD- If the same number of Cl atoms are adsorbed on the surface of the SiN film, more Si-Cl bonds that are difficult to break are included in the HCD-SiN film having a high film formation rate.

The second reason is that the HCD-SiN film can be formed at a lower temperature. As shown in FIG. 3, the Cl concentration increases as the film formation temperature decreases, and the Cl concentration increases under a condition (NH ₃ / HCD = 1000/50) where the film formation rate is higher than 450 ° C. I understand that.

FIG. 4 shows the relationship between the dielectric constant of the HCD-SiN film obtained by CV measurement and the film formation temperature. In the figure, white squares indicate data in which ammonia and HCD are used as raw materials, and black squares indicate data in which nitrogen (N ₂ ) is further flowed during film formation.

From the figure, it can be seen that the dielectric constant of the HCD-SiN film is lower than the dielectric constant (= 7.8) of the normal silicon nitride (Si ₃ N ₄ ) film at the deposition temperature of 700 ° C. or less. For example, an HCD-SiN film formed at 450 ° C. indicated by a black square has a dielectric constant 20-30% lower than that of P-CVD-SiN indicated by a dotted line in the drawing. The HCD-SiN film formed at 450 ° C. indicated by a black square is an HCD-SiN film (ammonia flow rate (R [SCCM]) = 100, 0.5 Torr, dielectric constant = shown by white circles formed at 550 ° C. to 700 ° C. Compared with 7.3), the dielectric constant is as small as 5.4. A white square is an HCD film of 1.4 Torr and R = 100. Further, at a film forming temperature of 450 ° C. or lower, the dielectric constant is as very small as 6 or lower. This value is smaller than the dielectric constant (about 7) of the plasma-silicon nitride film (p-SiN film). Since the dielectric constant is small, the wiring capacity can be remarkably reduced, which is a great advantage when the above HCD-SiN film is used as an insulating film in a so-called multilayer wiring portion. Further, different samples were used at 600 ° C. or higher and 450 ° C. or lower, but similar results were obtained even when the same sample was used. Note that FIG. 4 shows the result of the HCD-SiN film in which nitrogen is not supplied during film formation, but there is no large difference in dielectric constant even when nitrogen is supplied.

  FIG. 5 shows the relationship between the chlorine concentration in the silicon nitride film and the polishing rate. It can be seen from the figure that the polishing speed increases in proportion to the chlorine concentration. The reason is considered that the higher the chlorine concentration is, the more disturbed the network is due to the presence of a large number of chlorine ions having a large ion radius in the Si-N network. That is, it is considered that the higher the chlorine concentration, the lower the density of the silicon nitride film, and the faster the polishing rate by CMP.

  Although the case where the silicon nitride film is removed by CMP has been described here, the following results were obtained in the case of RIE.

  That is, as shown in FIG. 6, it was found that the etching rate of the HCD-SiN film was slower at any film formation temperature than the DCS-SiN film formed at a film formation temperature of 700 ° C.

Therefore, in the HCD-SiN film 10 of this embodiment, a connection hole for connecting the lower capacitor electrode to the n ⁺ -type source diffusion layer 2 is formed in the interlayer insulating film 3 by RIE, as compared with the conventional DCS-SiN film. It can be said that it is more suitable as a mask to be used.

  6A shows the results under the contact hole opening etching conditions, and FIG. 6B shows the results under the taper etching conditions.

  FIG. 7 shows the dependency of the RIE selection ratio (TEOS oxide film etching rate / HCD-SiN film etching rate) of the TEOS oxide film on the HCD-SiN film on the deposition temperature and ammonia flow rate (R [SCCM]). The drawing also shows the RIE selectivity of the TEOS oxide film to the DCS-SiN film formed at a film formation temperature of 700 ° C. Here, black circles are etching selectivity ratios when films are formed at 600 ° C., 650 ° C., and 700 ° C. with DCS as the material, 0.5 Torr, and the ammonia / DCS flow rate ratio (hereinafter abbreviated as R) as 100. About 7 is obtained. In contrast, black squares and black triangles are selective ratios when HCD is used as the material, 1.4 Torr, and the ammonia / HCD flow rate ratio (hereinafter abbreviated as R) is 50 and 20, both of which are low temperatures of 450 ° C. However, it has been found that a selection ratio of about 6 can be obtained. From the figure, it can be seen that, in the case of RIE, almost the same selection ratio as that of the DCS-SiN film can be obtained regardless of the ammonia flow rate (R) and the film formation temperature.

  FIG. 8 shows the deposition temperature dependence of the deposition rate of the HCD-SiN film. From the figure, it can be seen that in the case of the HCD-SiN film, a sufficient film formation rate can be secured even at a film formation temperature of 250 ° C.

  Therefore, if the silicon nitride film 110 is formed at a film formation temperature of 650 ° C. as in this embodiment, the film formation speed of the silicon nitride film 110 can be secured without losing the function of the TiN film 108 as a barrier metal film. .

  Further, in the present embodiment, the case where the silicon nitride film is formed so as to fill the inside of the wiring groove 105 in which the embedded wiring is formed to an intermediate depth has been described. For example, it is also effective for a groove in which various laminated film structures are embedded to a halfway depth.

  Specifically, a groove formed in a silicon oxide film, which is buried partway with a laminated film (polymetal gate) of oxynitride film / polysilicon film / tungsten film, is mentioned.

In the present embodiment, the case where Si ₂ Cl ₆ is used as the Si raw material has been described. However, when a silicon nitride film having a high chlorine concentration is formed, Si—Si such as Si ₃ Cl ₈ and Si ₄ Cl _{10 is used.} The same effect can be obtained by using Si raw materials such as chloride having one or more bonds, Si _n Cl _{2n + 2} (where n = 2 or more).

(Second Embodiment)
In the first embodiment, a case where a silicon nitride film having a high chlorine concentration is formed has been described. In this embodiment, a method for forming a silicon nitride film having a high chlorine concentration and excessive silicon will be described. The process cross-sectional view is the same as that of the first embodiment, and will be described with reference to FIGS.

First, similarly to the first embodiment, the process up to the step of FIG. 2D is performed, and then, as shown in FIG. 2E, by the LPCVD method using a mixed gas of Si ₂ Cl ₆ and NH _3. Then, a silicon nitride film (HCD-SiN film) 8 is formed on the entire surface so as to fill the inside of the wiring trench 106.

Here, the film forming temperature is 600 ° C., the reactor internal pressure is 0.5 Torr, and the flow rate ratio is NH ₃ / Si ₂ Cl ₆ = 2000 sccm / 20 sccm. The deposition rate under these deposition conditions is 1.4 nm / min.

  Next, as shown in FIG. 2F, under the same conditions as in the first embodiment, the excess HCD-SiN film 110 outside the wiring trench is removed by CMP to planarize the surface.

  From the film thickness measurement results after CMP, the polishing rate of the HCD-SiN film 110 formed by the method of this embodiment is faster than the DCS-SiN film formed by the method using dichlorosilane as a conventional Si raw material. I understood that.

  Thus, according to the present embodiment, since the polishing rate can be increased, the selectivity to the silicon oxide film can be increased, and polishing by CMP can be stopped at the silicon oxide film. For this reason, excessive polishing is suppressed, an embedding shape as designed can be realized, and processing with high flatness can be performed.

  FIG. 9 shows the result of examining the bonding state of silicon in each silicon nitride film formed by changing the deposition temperature in the method of this embodiment by surface analysis by photoelectron spectroscopy (XPS). From the figure, it can be seen that according to the method of the present embodiment, a silicon nitride film having a Si—N bond is formed even when the film forming temperature changes.

  FIG. 10 shows the results of examining the N / Si ratio of each silicon nitride film formed by changing the deposition temperature in the method of this embodiment by chemical analysis.

From the figure, when the film forming temperature is 700 ° C. or less, the silicon nitride film (HCD−) having silicon excess (N / Si ≦ 1.33) than the silicon nitride film (Si ₃ N ₄ film) having the chemical quantum ratio. It can be seen that a SiN film) can be formed. Further, it can be seen from the figure that the HCD-SiN film is silicon richer than the DCS-silicon nitride film.

  Since the Si—Si bond distance is 0.225 nm and longer than the Si—N bond distance 0.157 nm, it is considered that when a silicon-excess silicon nitride film is formed, the Si—N network is greatly disturbed. That is, the silicon-rich silicon nitride film has a lower density and a higher polishing rate by CMP. Further, as shown in FIG. 3, the chlorine concentration in the film also increases.

  FIG. 11 shows the results of examining the density of an HCD-SiN film formed at different film formation temperatures and the density of a DCS-SiN film formed at a film formation temperature of 700 ° C. in the method of this embodiment.

  The density was examined as follows. First, the surface of the silicon nitride film other than the region to be dissolved with the DHF solution was covered with an HF-resistant tape. Next, the surface of the silicon nitride film in a square region having a side of 6 cm was dissolved with a DHF solution. Thereafter, the weight of silicon and nitrogen in the DHF solution was determined to determine the density.

  In the figure, the black square at a film forming temperature of 700 ° C. is DCS-SiN, and the other three points are HCD-SiN. Here, DCS-SiN has an ammonia flow rate (R [SCCM]) = 10, and HCD-SiN has R = 100.

  From the figure, it can be seen that the lower the film formation temperature, the lower the density of the HCD-SiN film. Unlike the DCS-SiN film, the HCD-SiN film does not significantly decrease the film formation rate even at a film formation temperature lower than 700 ° C., and can be formed in a practical film formation time. Therefore, an HCD-SiN film having a density lower than that of the DCS-SiN film can be easily obtained by lowering the film formation temperature.

Further, by reducing the flow ratio (NH ₃ / Si ₂ Cl ₆ ) between NH ₃ and Si ₂ Cl ₆ to 10 or less, a silicon-excess film can be formed even at a film forming temperature of 700 ° C. and a furnace pressure of 0.5 Torr. Is possible.

  However, since the conductivity increases when the silicon is excessive, the insulation cannot be maintained if the flow rate ratio is too small. Therefore, it is necessary to set the flow rate ratio so as to satisfy the desired performance.

Although only Si ₂ Cl ₆ has been described as a raw material, in order to form a silicon nitride film having a high chlorine concentration and excessive silicon, Si—Si bonds such as Si ₃ Cl ₈ and Si ₄ Cl ₁₀ are formed. Similar effects can be obtained by using Si raw materials such as chlorides having one or more and Si _n nCl _{2n + 2} (where n = 2 or more).

(Third embodiment)
It is necessary to reduce the resistance of the gate electrode along with the miniaturization of elements. Therefore, it is necessary to change the current polymetal gate structure to a metal gate electrode in the next generation. On the other hand, since it is difficult to finely process a metal film by etching, a damascene gate process (A. Yagishita, et.al., IEDM Tech Digest, 1998: p.785.) Is used to form a metal gate electrode. In addition, a dummy gate is required when forming the trench in which the metal gate electrode is embedded. A method for manufacturing a MOS transistor using a metal gate electrode according to the third embodiment of the present invention will be described below with reference to FIGS.

  First, as shown in FIG. 12A, a shallow trench is formed on the surface of the silicon substrate 121. Subsequently, a thermal oxide film 122 is formed on the entire surface, and then an element isolation insulating film 123 is embedded in the trench. Thus, element isolation is performed by STI (Shallow Trench Isoiation). The element isolation insulating film 123 is an oxide film formed using TEOS as a raw material.

  Next, as shown in FIG. 12B, a polycrystalline silicon film 124 having a thickness of 150 nm is formed under normal conditions using the LPCVD method.

Next, as shown in FIG. 5B, the flow rate ratio (NH ₃ / Si ₂ Cl ₆ ) = 1000/10, the film forming temperature is 550 ° C., using the Si ₂ Cl ₆ + NH ₃ gas as the raw material of the present invention. Then, an HCD-SiN film 125 having a thickness of 150 nm is formed on the polycrystalline silicon film 124 by LPCVD at a deposition pressure of 1.4 Torr.

  Here, the HCD-SiN film 125, which is the silicon nitride film of the present embodiment, is formed at a film forming temperature as low as 500 ° C., but the DCS-SiN film, which is a conventional silicon nitride film, is usually 700-780 ° C. The film is formed at a high film formation temperature.

Under the above film forming conditions (flow rate ratio, film forming temperature, film forming pressure), the film forming speed is 1.5 nm / min, so the film forming time is 100 min. By increasing the partial pressure ratio of Si ₂ Cl ₆ , for example, it is possible to further increase the film formation rate by increasing the total pressure or decreasing the NH ₃ flow rate.

  Next, as shown in FIG. 12C, a resist pattern 126 is formed using photolithography or EB drawing, and the HCD-SiN film 125 and the polycrystalline silicon film 124 are formed by RIE using the resist pattern 126 as a mask. Etching is performed to form a dummy gate 127 made of a laminated film of the HCD-SiN film 125 and the polycrystalline silicon film 124. Thereafter, the resist pattern 126 is peeled off.

Next, as shown in FIG. 13D, after a post-oxide film 128 having a thickness of about 6 nm is formed by thermal oxidation, ion implantation is performed using the HCD-SiN film 125 as a mask, and shallow diffusion is performed at a low impurity concentration. A layer (LDD) 129 is formed. When the conductivity type of the diffusion layer 129 is n-type, for example, As ions are implanted under the conditions of an acceleration voltage of 1 KeV and a dose of 3 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 13E, after forming a 70 nm thick DCS-SiN film to be the gate sidewall DCS-SiN film 130 on the entire surface by LPCVD using the conventional raw material dichlorosilane system, The DCS-SiN film is etched on the entire surface by the RIE method to form the gate sidewall DCS-SiN film 130. Here, the film formation conditions are, for example, a film formation temperature of 700 ° C., a film formation pressure of 0.5 Torr, and a flow rate ratio (NH ₃ / SiH ₂ Cl ₂ ) of 500/50.

Next, as shown in FIG. 4E, ion implantation is performed using the gate sidewall DCS-SiN film 130 and the HCD-SiN film 125 as a mask to form a source / drain diffusion layer 131 having a high impurity concentration. When the conductivity type of the source / drain diffusion layer is n-type, for example, As ions are implanted under the conditions of an acceleration voltage of 45 KeV and a dose of 3 × 10 ¹⁵ cm ⁻² .

  It should be noted that the activation annealing of the impurities in the shallow diffusion layer 129 and the source / drain diffusion layer 131 may be performed every time immediately after the implantation, or may be performed collectively after all the ion implantations are completed.

  Next, as shown in FIG. 13 (f), an interlayer insulating film 132 having a thickness of about 350 nm is formed on the entire surface by LPCVD using TEOS as a raw material, and then the interlayer insulating film 132 is polished by CMP to polish the surface. To flatten. At this time, the HCD-SiN film 125 functions as a CMP stopper.

  Next, as shown in FIG. 14G, after selectively removing the HCD-SiN film 125 using a hot phosphoric acid solution at 160 ° C., and subsequently removing the polycrystalline silicon film 124 using the CDE method, The underlying thermal oxide film 122 is removed using a diluted hydrofluoric acid solution.

  In this embodiment, the HCD-SiN film 125 is used as the silicon nitride film constituting the dummy gate 127 and the gate side wall DCS-SiN film 130 is used as the gate side wall insulating film. By controlling the film temperature, the wet etching selectivity of the gate sidewall DCS-SiN film 130 with respect to the HCD-SiN film 125 can be increased.

  Thus, it is important that the wet etching selectivity of the gate sidewall insulating film with respect to the silicon nitride film constituting the dummy gate 127 is high. This is because if both of them are etched at the same time, the silicon substrate 121 is damaged in the step of removing the polycrystalline silicon film 124 by the CDE method, or the silicon substrate 121 is ground in the worst case. It is.

  FIG. 15 is a cross-sectional view corresponding to the cross-sectional view of FIG. 14G when the dummy gate 127 and the gate sidewall insulating film are formed using only the conventional technique. As shown in the figure, the conventional technique alone causes a problem that the silicon substrate 121 is ground. In order to prevent such a problem from occurring, it is necessary to make it possible to obtain a selective ratio between the dummy gate and the gate sidewall insulating film with respect to the chemical solution used for processing as in this embodiment. Become.

  Here, FIG. 16 shows the film formation temperature dependency of the etching rate of dilute hydrofluoric acid (water: HF = 200: 1) of the silicon nitride film (HCD-SiN film) formed using hexachlorodisilane according to the present invention. . The reason why the film formation pressure is set to 1.4 Torr at a film formation temperature of 550 ° C. or less is to shorten the time required to form the HCD-SiN film as the sample.

  As is apparent from the figure, the etching rate increases as the film is formed at a lower temperature. The etching rate of dilute hydrofluoric acid (water: HF = 200: 1) of the DCS-SiN film formed at a film formation temperature of 700 ° C. is 0.19 nm / min. Therefore, the selection ratios of the HCD-SiN film formed at the film formation temperature of 600 ° C. and 450 ° C. with respect to the DCS-SiN film formed at the film formation temperature of 700 ° C. are 1.6 and 119, respectively. In the case of 550 ° C., a selection ratio of 24 can be realized.

  In addition, when hot phosphoric acid is used as the chemical solution, it is known that the selectivity of the HCD-SiN film formed at the film formation temperature of 650 ° C. with respect to the DCS-SiN film formed at the film formation temperature of 700 ° C. is 3.7. . That is, it is considered that the tendency found in dilute hydrofluoric acid with respect to hot phosphoric acid (the etching rate by the chemical increases with the film formation temperature) similarly occurs.

As shown in FIG. 17, when Si ₂ Cl ₆ is used as the Si raw material, if nitrogen (N ₂ ) is flowed during the formation of the silicon nitride film, the etching rate is doubled compared to the case where no flow is performed. Become weaker and bigger.

  This value can be about 240 as a selective ratio with respect to the DCS-SiN film formed at a film forming temperature of 700 ° C. The DCS-SiN film formed at other film formation temperatures is considered to have the same effect. Therefore, by controlling the film formation temperature, the wet etching rate of the HCD-SiN film and the DCS-SiN film can be controlled and selected. It is thought that a large ratio can be obtained.

  As is apparent from the above, the HCD-SiN film according to the present invention is used for the silicon nitride film of the dummy gate, and the DCS-SiN film according to the prior art is used for the gate side wall insulating film, so that selection during wet etching is performed. A large ratio can be taken.

  In this way, the reduction of the gate sidewall DCS-SiN film 130 in the removal process of the polycrystalline silicon film 124 can be effectively suppressed by the CDE process, and problems such as substrate damage can be avoided during the CDE process. Further, since the polycrystalline silicon film 124 and the HCD-SiN film 125 can be removed by appropriate etching, the dummy gate 127 can be easily removed.

  In the present embodiment, a laminated film of the polycrystalline silicon film 124 and the HCD-SiN film 125 is used as the dummy gate 127 as in the prior art. The polycrystalline silicon film 124 is formed to surely prevent the gate sidewall DCS-SiN film 130 from being etched at the same time when the HCD-SiN film 125 is removed by etching.

  However, it is not necessary when the selection ratio between the dummy gate 27 and the gate sidewall DCS-SiN film 130 can be sufficiently ensured. That is, in the case of this embodiment, since the selection ratio can be originally obtained between the HCD-silicon nitride film 125 and the gate sidewall DCS-SiN film 130, a structure in which the dummy gate 127 is only the HCD-silicon nitride film 125 is possible. is there. In this case, the step of forming the polycrystalline silicon film 124, the step of removing by CDE, and the step of forming the post oxide film 128 (FIG. 13D) are unnecessary.

Next, as shown in FIG. 14H, a gate insulating film 133 is formed in the groove formed by removing the dummy gate 27. As the gate insulating film 133, for example, an insulating film made of a ferroelectric such as Ta ₂ O ₅ or (Ba, Sr) TiO ₃ can be considered.

Here, the case where a Ta ₂ O ₅ film is used will be specifically described. First, the surface of the substrate is irradiated with oxygen radicals to form a SiO ₂ film (not shown) with a thickness of about 0.2 to 0.3 nm, and then silicon nitride with a thickness of 0.6 nm using ammonia, silane or the like. A film (not shown) is formed. Thereafter, a Ta ₂ O ₅ film having a thickness of about 1 nm is formed as a gate insulating film 133 on the silicon nitride film.

  Finally, as shown in FIG. 14I, after depositing a TiN film 134 having a thickness of about 10 nm and an Al film 135 having a thickness of about 250 nm as a gate electrode over the entire surface so as to fill the inside of the groove, The excess gate insulating film 133, the TiN film 134, and the Al film 135 outside are removed by CMP to flatten the surface, thereby completing the MOS transistor.

  In the first to third embodiments, the case of the silicon nitride film for preventing a short-circuit between the lower capacitor electrode and the plug electrode of the so-called M0 portion (portion where contact is made from the silicon substrate) has been described. The present invention can also be applied to silicon nitride films for other purposes.

(Fourth embodiment)
FIG. 18 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention. These drawings show a cross section in which a MOS transistor and a contact opening of a DRAM cell are cut in a direction perpendicular to the channel width direction.

In FIG. 18A, a polysilicon film 208, a WN (tungsten nitride) film 209, a W (tungsten) film 210, and a SiN film 212 are laminated on a silicon substrate 201 via a gate insulating film (not shown). By using the gate electrode 200 that selectively leaves only the region by RIE as a mask, As ions are implanted by ion implantation under the conditions of 15 keV and 5 ¹³ cm ⁻² for forming an n ⁻ layer. A region 206 and a drain region 207 are formed.

  Next, a SiN film is formed on the entire surface of the silicon substrate 201 by low pressure chemical vapor deposition (LPCVD) using DCS as a raw material, and etched back to form a gate sidewall insulating film 211 made of SiN only on the sidewall of the gate electrode 200. Form.

  In this way, a base comprising the silicon substrate 201, the gate electrode 200, and the gate sidewall insulating film 211, having a step structure with an aspect ratio of about 2 and a narrowest space of about 0.15 microns in the cell portion is completed.

On this underlayer, a film forming temperature of 450 ° C. using LP ₂ CVD method using Si ₂ Cl ₆ (hexachlorodisilane, hereinafter abbreviated as HCD) and ammonia (NH ₃ ) as a source gas and nitrogen (N ₂ ) as a carrier gas, The SiN film 213 is formed to a thickness of 15 nm under the conditions of the reactor internal pressure of 1.4 Torr and the flow rate ratio of ammonia: HCD: nitrogen = 1000 sccm: 50 sccm: 50 sccm (this SiN film is referred to as an HCD-SiN film). This HCD-SiN film becomes an RIE stopper film when a contact is opened to the interlayer insulating film later (FIG. 18B).

  The deposition rate of the HCD-SiN film under the above deposition conditions was 2.6 (nm / min). Incidentally, it was possible to form a film without flowing nitrogen during film formation.

  Further, from FIG. 7 shown above, since the RIE selection ratio is almost the same as that of the conventional SiN film using DCS even when HCD is used, the SiN film using HCD is also used as a stopper. The film thickness is 15 nm, which is the same as the conventional film, and there is no problem.

Next, a BPSG film is formed as the interlayer insulating film 220, and then heat treatment (2H ₂ + O ₂ → 2H ₂ O (water vapor)) at 800 ° C. in an atmosphere containing H ₂ and O ₂ is performed. 220 was densified, and then the surface of the interlayer insulating film 220 was removed by about 370 nm by CMP using the SiN film 213 as a CMP stopper to flatten the surface of the interlayer insulating film 220.

  Next, when planarization is completed, resist coating, exposure, and development are performed. Using the resist (not shown) as a mask, the interlayer insulating film 220 (BPSG) is etched by RIE to open a contact hole 214 (FIG. 18 ( c)).

  At this time, since the SiN film (HCD-SiN film) 213 has a slower etching rate than BPSG, it acts as an RIE stopper, and RIE stops. The HCD-SiN film serving as the RIE stopper can be used as an RIE stopper when a contact is opened in the peripheral portion in addition to the contact opening in the cell portion.

  Next, the gas conditions are switched, and the SiN film 213 on the bottom surface of the contact hole 214 is subjected to RIE. However, at this time, since it is necessary to suppress the underlying silicon substrate 201 to such a weak etching condition as not to etch, a portion of the SiN film is generated and a contact cannot be obtained. This film residue is removed by dilute hydrofluoric acid treatment for removing the equivalent of 1 nm of the natural oxide film as a pretreatment for buried polysilicon film to be a contact plug in the next process (FIG. 18D).

  As shown in FIG. 16, the etching rate of HCD-SiN formed at 550 ° C. or higher (deposition pressure: 0.5 Torr) is as low as about 20 (angstrom / min), that is, about 2 (nm / min). However, HCN-SiN deposited at 450 ° C. has an etching rate of 20 (nm / min) or more, which is 20 times or more that of a natural oxide film.

  For this reason, even if there is non-uniformity in the etching surface of the RIE during the SiN etching in the step of FIG. 18D, it is possible to remove all of the SiN film remaining in the pretreatment with dilute hydrofluoric acid at the same time. , Contact failure due to the SiN film residue can be avoided.

Incidentally, FIG. 16 shows the result of the HCD-SiN film in which nitrogen (N ₂ ) is not flowed during film formation. When nitrogen is flowed, for example, at 450 ° C., the etching rate with 1/200 dilute hydrofluoric acid increases to 45 nm / min, so that the etching is further facilitated.

  As confirmed by the present inventors, the HCD-SiN film has a deposition rate of 2 (nm / min) at 450 ° C., which is slightly higher than 3 (nm / min) of the DCS-SiN film at 780 ° C. It was found to be small but practical enough. In addition, the plasma SiN film | membrane confirmed simultaneously was 100 (nm / min) at 370 degreeC, and the film-forming speed | rate was the fastest.

  By forming SiN at a low temperature of about 450 ° C. using HCD as described above, it has become possible to obtain SiN having a low density and a low dielectric constant.

  Here, the low dielectric constant is closely related to the low density. That is, the dielectric constant and density are considered to follow the following Clausius-Mossotti equation.

  Note that the following Clausius-Mossotti equation is calculated according to Ashcroft. According to P542 of Solid State Physics (Saunders College (1976)) by Mermin.

(Ε-1) / (ε + 2) = {(N ₀ × α) / (3 × ε ₀ )} × (ρ / M)
... Clauus-Mossotti equation where ρ is density, ε is dielectric constant, M is molecular weight, and α is polarizability. Further, ε _o is a vacuum dielectric constant, N ₀ is Avogadro's number, and both are constants. From this equation, it can be seen that density and dielectric constant are generally proportional. That is, the reason why the low dielectric constant HCD-SiN film was practically used as described above is considered to be due to the realization of the low density HCD-SiN film.

  On the other hand, as described above, the film thickness required for the HCD-SiN film to function as an RIE stopper is the same as that of the DCS-SiN film and the dielectric constant is smaller than that, so that the HCD-SiN film is smaller than the conventional DCS-SiN film. In addition, it is possible to remarkably reduce the inter-wiring capacitance while ensuring the same RIE barrier property.

  Further, when considering transistor characteristics, it is generally known that the interface state at the gate insulating film interface is reduced by hydrogen sintering, and the retention time of the transistor is increased. This is said to be due to the fact that silicon dangling bonds are terminated with hydrogen, thereby reducing defects that cause leakage current (termination effect).

The HCD-SiN film has more hydrogen in the film as 1 × 10 ²² cm ^-3 than the conventional LP-SiN film, and degass the hydrogen at a temperature higher than the film formation temperature. is there.

  FIG. 19 is a diagram showing the element profile in the depth direction by SIMS of the HCD-SiN film before and after heat treatment at 1000 ° C. for 30 minutes. In this figure, sputter etching is performed from the surface, and the atomic count number (CPS) of each atom of hydrogen and chlorine is examined by SIMS of the portion. The horizontal axis indicates time (minutes), and the vertical axis indicates the count number (CPS). : Count number per second). The solid line before the heat treatment and the dotted line after the heat treatment are shown. The range of about 0 to 9 minutes on the horizontal axis in this figure corresponds to the HCD-SiN film.

As shown here, it was confirmed that the hydrogen decreased by about two orders of magnitude from about 1.5 × 10 ⁵ CPS to about 4 × 10 ² CPS by heat treatment. Chlorine (Cl) did not change significantly before and after the heat treatment.

Here, the H concentration before annealing corresponds to 1 × 10 ²² cm ^−3, and the H concentration after annealing corresponds to 1 × 10 ²⁰ cm ⁻³ or less (below the detection limit). The chlorine concentration corresponds to 1 × 10 ²¹ cm ⁻³ . As described above, since the HCD-SiN film degass a large amount of hydrogen by annealing, it was found that silicon dangling bonds could be effectively terminated.

  The SiN film formed by the chemical vapor deposition (P-CVD) method using plasma or the low pressure chemical vapor deposition (LPCVD) method using silane and ammonia as raw materials has a poor step coverage as described above, and the aspect ratio. If the film is formed on about two grooves, the uppermost portion of the stepped portion may be thick, the lower portion and the side wall may be thinned, or an overhanging portion may be formed at the uppermost edge portion.

  In such a state, it becomes difficult to wrap the source gas into the lower portion of the overhang portion when forming the interlayer insulating film, and the interlayer insulating film (BPSG or the like) cannot be embedded. Further, the above-described SiN film has a non-homogeneous film quality and cannot function as a stopper at the edge portion.

  On the other hand, when using a silicon raw material in which hydrogen of silane is replaced with chlorine, such as dichlorosilane (DCS) or tetrachlorosilane, the step coverage is good, and the coverage is 100% even when the aspect ratio is about 20. . However, this effect is not limited to silane-based elements, and the present inventors have confirmed that a step structure can be formed uniformly and with good coverage by LPCVD using HCD, which is a chlorinated disilane. I understood that I could do it.

  In the present embodiment, only the example in which the HCD-SiN film is used as the SiN film as the RIE stopper has been described. However, the effect of reducing the dielectric constant of the HCD-SiN film is also effective for the SiN film 212 on the gate electrode or the SiN film 211 on the gate sidewall. That is, by forming an HCD-SiN film as these SiN films, a SiN film having a low dielectric constant can be obtained, so that the capacitance between wirings can be reduced.

  In the present embodiment, the gate electrode has a polysilicon / WN / W laminated structure as an example. However, the present invention is not limited to this, and the gate electrode is made of only metal and polysilicon. It goes without saying that an electrode may be used.

(Fifth embodiment)
FIG. 20 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention. These figures are cross-sectional views in which the vicinity of a Cu wiring used in a semiconductor device is cut in a direction perpendicular to the longitudinal direction of the wiring.

  In the wiring groove of the TEOS interlayer oxide film 203, a TaN (tantalum nitride) film 204 as a barrier metal film and Cu as a metal wiring 201 ′ are embedded, and a base (wiring layer) whose surface is flattened by CMP is formed. (FIG. 20 (a)).

On this base, by LPCVD, Si ₂ Cl ₆ (HCD, hexachlorodisilane) and ammonia (NH ₃ ) are used as source gases, the film forming temperature is 450 ° C., the reactor pressure is 1.4 Torr, and the flow rate ratio is ammonia. : HCD: nitrogen = 1000 sccm: 50 sccm: 50 sccm The SiN film 205 was formed to a thickness of 10 nm (FIG. 20B).

  In order to confirm the breakdown voltage of the SiN film 205, the following test was performed. In the test sample, a SiN film having a predetermined thickness was formed on a silicon substrate, and a Cu film was formed thereon. A predetermined voltage is applied to the silicon substrate and the Cu film, and the change in leakage current with time is measured. The result is shown in FIG.

  FIG. 21 shows a case where a P-SiN film having a thickness of 50 nm, an HCD-SiN film having a thickness of 10 nm, or an HCD-SiN film having a thickness of 50 nm is used as an SiN film on a silicon substrate at 100 ° C. and 1 (MV The change in leakage current (Leakage current) over time is shown with the horizontal axis representing the application time (Stress timc (min)) and the vertical axis representing the leakage current. It is a measurement result of a test (BT test).

In general, Cu diffusion is said to be caused by Cu ¹⁺ ions, and the bias is applied under the condition that the Cu electrode is at a high potential so that Cu ¹⁺ diffuses into the silicon substrate. In the figure, the vertical axis indicates the leakage current, and the horizontal axis indicates the time during which stress is applied. It can be said that a film that has not been broken for a longer time (leakage current is stable) has high barrier properties. As is apparent from the figure, the HCD-SiN film has a barrier property against Cu diffusion as compared with the plasma SiN film, regardless of whether the film thickness is 50 nm or 10 nm.

  Here, the breakdown means a point where the leakage current changes abruptly. The P-SiN film having a thickness of 21 to 50 nm is about 13 minutes, the HCD-SiN film having a thickness of 10 nm is about 1000 minutes, and the thickness is 50 nm. It takes 5000 minutes or more for the HCD-SiN film.

  The reason why the barrier property is high even if the HCD-SiN film is thinner than the plasma-SiN film is considered to be because the Cl concentration in the film is high.

FIG. 22 shows a plot in which the time required for breakage (Break Time) is plotted on the vertical axis and the Cl concentration in the film (Cl concentration) is plotted on the horizontal axis. As can be seen from FIG. 22, the higher the Cl concentration, the longer the time until destruction. That is, in the P-SiN film, since no chlorine (Cl) -containing raw material is used, no Cl is contained and the time until breakdown is very short, whereas in the HCD-SiN film, the Cl concentration is 3.4. × 10 ²¹ cm ^-3 was reached, and the time to failure exceeded 1000 minutes.

Here, since Cl has a large electronegativity and is negatively charged, it is considered that Cu ¹⁺ diffusion species were not destroyed for a longer time by being trapped at the Cl site. Further, as shown in FIG. 4, it is known that the HCD-SiN film formed at a low temperature has a dielectric constant as small as 5.4. That is, when an HCD-SiN film is used, a high withstand voltage can be obtained even if a film having a small dielectric constant is used as a thin film. This reduces the inter-wiring capacitance by about 20% compared to the conventional DCS-SiN film.

  The implementation of the inventions according to the fourth and fifth embodiments is not limited to the semiconductor device or the manufacturing method thereof described above, and it is widely applied to an insulating film that requires a low dielectric constant and an insulating film that requires a high breakdown voltage. Applicable. For example, it can be applied to a power element such as an IGBT.

In the fourth and fifth embodiments, the example in which hexachlorodisilane is used as the raw material for forming the silicon nitride film has been described. However, the present invention is not limited to this, and generally Si _n Cl _{2n is used. +2} (n is an integer of 2 or more) are feasible if possible silicon chloride gas described. A silicon nitride film having a high chlorine concentration can be formed by using a gas containing a large amount of Cl groups.

(Sixth embodiment)
FIG. 23 is a process cross-sectional view showing a sixth embodiment of the present invention and showing a process of embedding a silicon oxide film in a recess between adjacent gate electrodes (or gate wirings).

  FIG. 23A shows a gate electrode formed on the silicon substrate 310 by a normal method and a configuration around the gate electrode. The gate electrode is formed by a polysilicon film 311, a WN film 312 and a W film 313, and a gate insulating film 314 is formed under the gate electrode. A cap silicon nitride film 315 is formed on the upper surface of the gate electrode, and a sidewall silicon nitride film 316 is formed on the side surface of the gate electrode. A liner silicon nitride film 317 is formed around the gate structure constituted by these, and a BPSG film 318 is formed on the side of the liner silicon nitride film 317. Further, a diffusion layer 319 serving as a source / drain is formed between adjacent gate electrodes.

  Next, as shown in FIG. 23B, a silicon oxide film 321 is formed on the substrate in which the recesses 320 are formed between the gate electrodes as follows.

First, after forming the structure shown in FIG. 23A, a silicon nitride film is formed by LPCVD. As the source gas, hexachlorodisilane (HCD, Si ₂ Cl ₆ ) and ammonia (NH ₃ ) are used. Note that N ₂ gas or rare gas may be used as the dilution gas. The film formation conditions are a film formation temperature of 250 ° C., a gas flow rate ratio NH ₃ / HCD = 1000/10, and a reactor pressure of 1.4 Torr. As a result, a silicon nitride film (SiN: HCl composition) containing chlorine is formed on the entire surface. The film formation rate under the above-described conditions was 0.26 nm / min.

FIG. 24 is a diagram showing SIMS profiles of each element contained in the formed silicon nitride film. Concentrations for oxygen (O), hydrogen (H), and chlorine (Cl), and nitrogen (N) Indicates the ion count. Here, in order not to oxidize the silicon nitride film formed at 250 ° C. using HCD, the silicon nitride film formed at 450 ° C. is formed on the upper surface thereof. It can be seen that the silicon nitride film formed at 250 ° C. contains about 1 × 10 ²² cm ⁻³ of chlorine.

Next, the formed silicon nitride film is oxidized under mild conditions, and converted into a silicon oxide film 321 containing chlorine. The conditions at this time are, for example, an O ₂ atmosphere, an oxidation temperature of 600 ° C., and an oxidation time of 10 minutes. By this film conversion treatment, the film thickness increases by about 20% (for example, the film thickness increases from 22.9 nm to 27.8 nm). Further, the refractive index decreases from 1.56 to 1.43, and shows a value almost equivalent to that of a normal silicon oxide film. That is, by performing oxidation under a mild condition, the silicon nitride film is converted into the silicon oxide film 321 with volume expansion. Incidentally, a silicon nitride film formed under the above-described conditions can be changed into a silicon oxide film even when left in the atmosphere at room temperature for a long time.

FIG. 25 is a diagram showing SIMS profiles of each element contained in the silicon oxide film after film conversion. Concentrations are shown for oxygen (O), hydrogen (H) and chlorine (Cl), and nitrogen (N). Indicates the ion count. The silicon oxide film contains about 6 × 10 ¹⁹ cm ^{−3 of} chlorine and about 1 × 10 ²¹ cm ^{−3 of} hydrogen. The measurement conditions are primary ion species: Cs ⁺ , primary acceleration voltage: 5 kV, and sputtering rate: 0.4 nm / second. Moreover, the ion count of NSi43 (segment ion composed of N of atomic weight 14 and Si of atomic weight 29) was about 6 × 10 ² (CPS). In the silicon nitride film containing 4 × 10 ²² cm ^{−3 of} nitrogen formed at 650 ° C. using HCD, the ion count of NSi43 was 5 × 10 ⁵ (CPS) under the above measurement conditions.

  According to this embodiment, a silicon nitride film containing chlorine is formed at a low temperature by LPCVD using HCD as a source gas, and the silicon nitride film is oxidized to be converted into a silicon oxide film. The silicon oxide film can be embedded uniformly and uniformly in the part. Even if “soot” is present in the silicon nitride film, volume expansion occurs when the silicon nitride film is converted into a silicon oxide film, so that a silicon oxide film without “soot” can be obtained.

In the above example, the silicon nitride film is formed at a temperature of 250 ° C. However, if it is lower than 450 ° C., the same effect can be expected by appropriately selecting the oxidation conditions. In the above-described example, the oxidizing atmosphere is the O ₂ atmosphere. However, an ozone (O ₃ ) atmosphere may be used, and by using the ozone atmosphere, the silicon nitride film can be converted into the silicon oxide film at a lower temperature. Also, the silicon nitride film can be converted into a silicon oxide film by oxidation treatment in water vapor, oxidation treatment using a chemical solution functioning as an oxidant (for example, ozone water, hydrogen peroxide solution, or the like).

(Seventh embodiment)
FIG. 26 is a view showing a seventh embodiment of the present invention, and is a process sectional view showing a process of embedding a silicon oxide film in an element isolation trench in the STI structure.

  FIG. 26A shows a configuration when the element isolation trench 331 is formed on the silicon substrate 330 by a normal method. Reference numeral 332 denotes a silicon oxide film, and reference numeral 333 denotes a silicon nitride film. In this example, a thinner silicon oxide film 334 is formed on the entire surface.

  FIG. 26B shows a state in which a silicon oxide film 335 containing chlorine is formed on the substrate on which the element isolation trench 331 is formed. As in the sixth embodiment, the silicon oxide film 335 is formed by forming a silicon nitride film containing chlorine by LPCVD using HCD as a source gas, and oxidizing the silicon nitride film to convert it into a silicon oxide film. Can be obtained.

  Finally, as shown in FIG. 26C, the silicon oxide film 335 outside the element isolation trench 331 is removed by CMP, and the element isolation process by STI is completed.

  Also according to this embodiment, similarly to the sixth embodiment, a silicon oxide film without “soot” can be uniformly and uniformly embedded in the element isolation trench.

(Eighth embodiment)
FIG. 27 is a process sectional view showing a process of embedding a silicon oxide film on a base region having a recess, showing the eighth embodiment of the present invention. Examples of the base region include the structure of FIG. 23A in the sixth embodiment, the structure of FIG. 26A in the seventh embodiment, and the like.

  In the sixth and seventh embodiments, a silicon nitride film containing chlorine is formed in the entire recess by LPCVD using HCD as a source gas, and this is converted into a silicon oxide film. In the embodiment, the silicon oxide film is finally embedded in the entire recess by repeating the silicon nitride film forming step and the silicon oxide film converting step a plurality of times.

  First, as shown in FIG. 27A, a silicon nitride film 352 containing chlorine is formed on the base region 351 in which the recess 51 is formed. The conditions for forming the silicon nitride film 352 are the same as those in the sixth embodiment.

  Subsequently, as shown in FIG. 27B, the silicon nitride film 352 is oxidized and converted into a silicon oxide film 353 containing chlorine. The conditions for this conversion processing are the same as in the sixth embodiment.

  Further, as shown in FIGS. 27 (c) and 27 (d), a silicon nitride film 354 containing chlorine is formed in the same manner as in FIGS. 27 (a) and 27 (b). The nitride film 354 is oxidized and converted into a silicon oxide film 355.

  By repeating the above-described silicon nitride film forming step and silicon oxide film converting step a plurality of times, as shown in FIG. 27E, finally the silicon oxide film 356 containing chlorine in the entire recess portion. Is formed.

  According to the present embodiment, since the silicon nitride film forming process and the silicon oxide film converting process are repeated a plurality of times, the thickness of each silicon nitride film can be reduced. Therefore, even when it is difficult to convert the entire silicon nitride film into a silicon oxide film by a single oxidation process, such as when the recess is deep, the silicon oxide film can be easily formed in the entire recess. .

In the sixth to eighth embodiments described above, the silicon nitride film containing chlorine is formed by LPCVD. However, the silicon nitride film further contains at least one of phosphorus (P) and boron (B). You may make it make it. In order to contain phosphorus, PH ₃ is further used in addition to HCD and ammonia as a source gas, and in order to contain boron, B ₂ H ₆ is further used as a source gas in addition to HCD and ammonia. .

  A silicon nitride film containing at least one of phosphorus and boron is oxidized in the same manner as in the sixth embodiment, so that a silicon oxide film containing at least one of phosphorus and boron in addition to chlorine (for example, chlorine is added). BPSG film) can be formed in the recess. Note that the contents of phosphorus and boron in the silicon oxide film are each preferably about 3 to 10 wt%.

  As described above, by incorporating phosphorus or boron into the silicon oxide film, the effects described in the sixth to eighth aspects can be obtained, as well as impurities such as Na and Fe that cause deterioration in electrical characteristics. A gettering effect can be obtained. Further, when the structure shown in FIG. 23 is used, when a contact hole is formed in the silicon oxide film 321 (in this case, a silicon oxide film containing phosphorus or boron in addition to chlorine) by RIE, a lower layer is formed. Etching can be performed at a high selectivity with respect to the silicon nitride film formed on the side, and a contact hole can be easily formed.

(Ninth embodiment)
First, the background that has motivated the present invention will be described. There are various technical problems in order to further advance high integration and miniaturization and realize a next-generation semiconductor.

  For example, problems with silicon nitride films with various application points will be shown. Here, applications of silicon nitride films widely used in semiconductor integrated circuits include electrical insulating films, capacitors or gate insulating films, etching stoppers, hard masks, barrier films, and passivation films.

  The problems in applying a silicon nitride film to a semiconductor device can be broadly divided into the following three.

  1. In next-generation semiconductor devices with advanced integration and miniaturization, it is necessary to form a film with good coverage on a substrate having fine irregularities. Usually, the LPCVD method is used as a film forming method with a good coverage. The normal film formation temperature of the silicon nitride film when the LPCVD method is used is about 80 ° C. However, in a next-generation semiconductor device, a film temperature of about 80 ° C. is too high because many non-heat-resistant devices such as metal wiring, barrier metal film, silicide layer, and shallow diffusion layer are used.

  2. Since the silicon nitride film used as an etching stopper film or hard mask has low etching resistance, it is necessary to increase the film thickness of the silicon nitride film in order to ensure the necessary etching resistance. As the film thickness increases, the time for forming the silicon nitride film increases and the thermal budget increases. Under such a thermal budget, various problems occur in areas with no heat resistance, such as elongation (re-diffusion) and inactivation of diffusion layers, aggregation and corrosion of metal films, and aggregation of silicide layers. make worse. In addition, there are problems such as poor productivity and increased costs.

  3. The dielectric constant of the silicon nitride film is as high as 7.5. When an insulating film having a high dielectric constant is used at a plurality of locations, the parasitic capacitance between wirings or between wiring layers is remarkably increased. In the future, if the insulating film having the same dielectric constant as before is used due to the reduction of the distance between the gate electrodes and the narrowing of the distance between the wirings as the miniaturization progresses, the parasitic capacitance will further increase. In addition, since the parasitic capacitance is large, for example, the effective capacitance of the capacitor holding the memory is reduced by the amount of the parasitic capacitance. In order to earn the reduced capacity, it is necessary to increase the capacity and area of the capacitor. This leads to an increase in chip size and an increase in production cost.

  28 and 29 are process sectional views showing a method for manufacturing a semiconductor device according to the ninth embodiment of the present invention. These drawings show a cross section of a MOS transistor of a DRAM cell cut in a direction perpendicular to the channel length direction.

  First, the structure shown in FIG. 28A is formed according to a known method. FIG. 28A is a cross-sectional view after the fabrication of a plurality of MOS transistors constituting the memory cell is completed and a metal wiring as a bit line or a word line is embedded in a layer one layer above the gate electrode. Show.

  In the figure, 401 is a silicon substrate, 402 is a polycrystalline silicon film (gate), 403 is a tungsten nitride film (gate), 404 is a tungsten film (gate), 405 is a silicon nitride film, 406 is a silicon oxide film (interlayer insulating film) , 407 is a trench, 408 is a silicon nitride film, 409 is a barrier metal film (for example, Ti film / TiN film), and 410 is a metal wiring (for example, W wiring).

  The maximum aspect ratio of the portion of the trench 407 where the metal wiring 410 is not buried is about 1 (depth is about 150 nm, width is about 150 nm). The barrier metal film 409 and the metal wiring 410 are formed by sequentially depositing a metal film (for example, a TiN film) and a metal film (for example, a W film) and then etching back these metal films.

  Next, as shown in FIG. 28B, a silicon nitride film 411 as a cap insulating film having a thickness of 200 nm is formed by the LPCVD method which is a film forming method excellent in controllability and covering property.

  The silicon nitride film 411 needs to be uniform and uniform, and the silicon nitride film 411 needs to be formed without generating a gap in the trench 407. Therefore, a film forming method with good coverage such as the LPCVD method is used for forming the silicon nitride film 411.

  Further, since the barrier metal film 409 has no heat resistance, a silicon nitride film forming method using dichlorosilane (DCS) as a raw material, that is, a silicon nitride film is formed at a high temperature and for a long time (for example, 7OO ° C., 330 In the conventional film forming method that requires a minute), the titanium silicide layer in the contact portion aggregates or the impurities in the diffusion layer are deactivated.

  Therefore, in the present embodiment, a silicon source capable of forming a film at a low temperature of 7 OO ° C. or lower, for example, hexachlorodisilane (HCD) and ammonia, a film forming temperature of 600 ° C., a reactor internal pressure of 0.5 Torr, and a gas flow ratio ammonia / HCD is used. A silicon nitride film 411 is formed by LPCVD under the film formation conditions of / methylamine = 2000 / 2O / 2O (each unit is sccm).

The deposition rate of the silicon nitride film 411 under this condition is 1.3 nm / min. It is. By this method, the silicon nitride film 411 contains hydrogen, chlorine and carbon as impurities. The hydrogen concentration is 5 × 10 ²¹ cm ⁻³ , the chlorine concentration is 9 × 10 ²⁰ cm ^−3, and the carbon concentration is 5 × 10 ²¹ cm ⁻³ . In order to sufficiently obtain the effects of the present invention, the chlorine concentration and the carbon concentration are preferably 4 × 10 ²⁰ cm ⁻³ or more. For this purpose, the film formation temperature of the silicon nitride film 411 is preferably set to 700 ° C. or lower.

  In the present embodiment, methylamine is described as the carbon supply source, but any of hydrocarbon compounds and amine-based carbides such as methane, ethane, ethylene, acetylene, dimethylamine and the like can be used.

  Next, as shown in FIG. 29C, the silicon nitride film 411 outside the trench 407 is removed by CMP to flatten the surface. At this time, planarization is performed using the silicon oxide film 406 as a CMP stopper. The CMP is performed under general conditions for polishing a silicon nitride film, for example, small particle size silica and phosphoric acid 2.5 wt. % And water, and the polishing pad load is 2 OOg.

  The polishing rate of CMP is not affected by lowering the film forming temperature and changing the silicon source. In the case of the above polishing conditions, any silicon nitride film formed by the conventional method and the method of this embodiment is used. The polishing rate is 2 Onm / min. Met. That is, it was confirmed that even if a silicon nitride film as a cap insulating film is formed by the method of the present invention, polishing characteristics that are the same as those of the prior art can be obtained with respect to planarization.

  As described above, according to the method of the present embodiment, the silicon nitride film can be formed at a low temperature. Therefore, there is a problem that the device characteristics are deteriorated in the cap insulating film forming process (silicon nitride film 411 forming process). Absent.

  Further, according to the method of the present embodiment, it was found that the density of the silicon nitride film can be reduced and the dielectric constant of the silicon nitride film can be reduced.

  FIG. 30 shows the result of the film formation temperature dependence of the dielectric constant of a silicon nitride film to which methylamine is not added, that is, a silicon nitride film into which carbon is not introduced. Incidentally, the dielectric constant of the silicon nitride film introduced with carbon was 6.4 at a film forming temperature of 60 ° C. In the figure, white circles indicate DCS-SiN films, and black circles indicate HCD-SiN films.

  Next, as shown in FIG. 29D, a resist pattern (not shown) is formed, and the silicon oxide film 406 is etched by RIE (Reactive Ion Etcher) using the silicon nitride film 411 and the resist pattern as a mask. The contact hole 412 is opened in a self-aligning manner.

  The RIE (Reactive Ion Etching) etching rate of the silicon nitride film 411 hardly depends on the film forming temperature.

  FIG. 31 shows the deposition temperature dependence of the RIE rate of a silicon nitride film that does not contain carbon. From the figure, it is the same as a DCS-SiN film (conventional silicon nitride film) having a film forming temperature of 70 ° C. up to a film forming temperature of 550 ° C. When the film forming temperature is lowered to 450 ° C., the RIE rate increases slightly.

  FIG. 32 shows the relationship between the RIE rate and the carbon concentration in the silicon nitride film. From the figure, it can be seen that by introducing carbon into the silicon nitride film, the RIE rate can be reduced by about 20% compared to the silicon nitride film without introducing carbon.

  In the step (RIE step) of FIG. 29C, the exposed portion of the silicon nitride film 411 that is not covered with the resist pattern (the portion that functions as a mask) drops due to the RIE etching species (ions, radicals). , The whole curls up.

  FIG. 33 shows a state in which the entire silicon nitride film 411 is rounded in the RIE process. In the drawing, the dotted line shows the silicon nitride film 411 after the CMP process and before the RIE process.

  The silicon nitride film as the cap insulating film needs to have a function of electrically insulating the electrode formed right next to the cap insulating film and the lower electrode of the capacitor formed thereon. For this reason, the silicon nitride film as the cap insulating film must remain to some extent even after the RIE process is finished.

  The conventional silicon nitride film into which carbon has not been introduced is 18 nm at the top and 70 nm at the corners, but the silicon nitride film 411 into which the carbon of the present invention has been introduced is 14 nn at the top. The corner was 54 nm.

  That is, when a conventional silicon nitride film is used, in order to secure a film thickness that can be used as a cap insulating film after the RIE process, the film thickness of the silicon nitride film before the RIE process needs to be 200 nm. However, if the silicon nitride film of the present invention is used, the film thickness before the RIE process can be reduced to 160 nm.

  As described above, according to this embodiment, it is possible to form a silicon nitride film having a lower dielectric constant and etching resistance than the conventional one. Therefore, it becomes possible to use a silicon nitride film having a lower dielectric constant and thinner than the conventional one, and the parasitic capacitance due to the interlayer insulating film of the semiconductor device can be reduced.

  Hereinafter, the reduction of the parasitic capacitance of the 1G-DRAM which is the next generation DRAM will be specifically described.

  34A is a cross-sectional view of a DRAM using the silicon nitride film of the present invention, and FIG. 34B is a cross-sectional view of a DRAM using a conventional silicon nitride film.

  In an actual semiconductor device, since the wirings and the electrodes and the wirings intersect in a complicated manner, the generated electric field distribution is also complicated. Therefore, only one example of the electrode arrangement that contributes to the parasitic capacitance is shown in the drawing. 28 and 29 are denoted by the same reference numerals as in FIGS. 28 and 29. In the figure, reference numeral 413 denotes a source / drain diffusion layer having an LDD structure, and reference numerals 414 and 415 denote gate side wall insulating films.

  For example, the parasitic capacitance is generated between the gate electrodes 402 to 404 and the metal wiring 410. According to the present invention, since the silicon nitride film 411 having a lower dielectric constant and a smaller film thickness is formed between the gate electrode and the metal wiring, the parasitic capacitance can be sufficiently reduced. Become.

  FIG. 34A shows an example in which the distance between the gate electrode and the metal wiring is large. In this case, when the pitch of the gate electrodes is narrower, the effect of lowering the dielectric constant and reducing the thickness of the silicon nitride film of the present invention becomes more remarkable.

  If the parasitic capacitance can be reduced, the capacitor area can be reduced, the distance between wirings and the distance between gates can be reduced, and finally the chip size can be reduced. In addition, since so-called RC delay resistance is reduced, device characteristics are also improved.

  On the other hand, in the conventional technique, the silicon nitride film 411 is formed to 200 nm. The conventional silicon nitride film 411 is typically formed under the conditions of a film forming temperature of 780 ° C., a reactor internal pressure of 66.5 Pa, and a dichlorosilane / ammonia flow rate ratio of 150 sccm / 1500 sccm. In this case, the deposition rate of the silicon nitride film 411 is 3.0 nm / min. Degree. However, when the silicon nitride film 411 is formed at 780 ° C., the barrier metal film 409 does not have the thermal pressure resistance, and reacts with the metal wiring 410 and the silicon substrate 401.

  In the first place, when the silicon nitride film 411 is formed at 780 ° C., the already formed MOS transistor is damaged, and the MOS transistor becomes useless.

  Even with the conventional technique, the film forming temperature can be lowered to 700 ° C. However, the deposition rate at a deposition temperature of 700 ° C. is 0.7 nm / min. Therefore, it takes less than 5 hours to form a cap silicon nitride film having a thickness of 200 nm.

  In an actual process, the time required for the temperature to become uniform and the time required for purging are required, and the entire process requires a film formation time of about 9 hours. That is, even if the cap silicon nitride film is formed at a relatively high film formation temperature of 700 ° C., the productivity is very poor.

  Under such a relatively high temperature / long-time thermal budget, a TixSiy (titanium silicide) layer (not shown) formed on the bottom surface of the contact hole is agglomerated in part, resulting in an increase in contact resistance. . Furthermore, under the thermal budget, the diffusion layer once activated is deactivated again, or the diffusion layer is re-diffused to increase the resistance of the diffusion layer.

  As described above, in the method of forming a silicon nitride film using dichlorosilane, there is a problem that if the film forming temperature is lowered, the productivity becomes very poor. However, according to the present invention, it is possible to establish a method for forming a silicon nitride film at a low temperature and a high speed, that is, a method for forming a silicon nitride film used in the next-generation semiconductor device.

  In the present embodiment, the case where the present invention is applied to the cap silicon nitride film has been described. However, the present invention can also be applied to the gate upper insulating film 414 and the gate sidewall insulating films 414 and 415.

  In this embodiment, the example in which the RIE rate of the silicon nitride film can be slowed has been described, but other etching rates can also be slowed. For example, the etching rate of the silicon nitride film with dilute hydrofluoric acid can be slowed.

  FIG. 35 shows the relationship between the carbon concentration of the silicon nitride film and the etching rate of the silicon nitride film with dilute hydrofluoric acid. The dilute hydrofluoric acid solution used in this experiment is obtained by diluting 46% hydrofluoric acid with water having a volume 2OO times larger than that.

  From the figure, it can be seen that by introducing carbon into the silicon nitride film, the etching rate of the silicon nitride film with dilute hydrofluoric acid can be reduced. This means that the etching selectivity can be obtained between silicon nitride films depending on the presence or absence of carbon.

  For example, a damascene metal gate process can be cited as a process that actively uses this. That is, as shown in FIG. 36A, a silicon nitride film 501 not containing carbon is formed as a dummy gate, and a silicon nitride film 502 containing carbon is formed as a gate side wall insulating film. As shown, the silicon nitride film 502 can be easily and selectively removed by wet etching using a diluted hydrofluoric acid solution. In the figure, 500 is a silicon substrate, 503 is a gate insulating film, 504 is a source / drain diffusion layer having an LDD structure, and 505 is an interlayer insulating film.

Process sectional drawing which shows the first half of the manufacturing method of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention Process sectional drawing which shows the second half of the manufacturing method of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention The figure which shows the film-forming temperature dependence of the chlorine concentration of the silicon nitride film (HCD-SiN film) of this invention The figure which shows the film-forming temperature dependence of the dielectric constant of HCD-SiN Characteristic diagram showing CMP rate dependence of chlorine concentration in silicon nitride film The figure which shows the film formation temperature dependence of the RIE rate of a HCD-SiN film | membrane, and the RIE rate in the film formation temperature of 700 degreeC of a DCS-SiN film | membrane. The figure which shows the dependence of the film forming temperature and the ammonia flow rate of the RIE selection ratio of the TEOS oxide film with respect to the HCD-SiN film The figure which shows the film-forming temperature dependence of the film-forming speed of a HCD-SiN film The figure which shows the result of having investigated the bonding state of the silicon | silicone of a HCD-SiN film | membrane by photoelectron spectroscopy measurement The figure which shows the result of having investigated the N / Si ratio of each silicon nitride film formed by changing the film-forming temperature in the method of 2nd Embodiment by chemical analysis The figure which shows the result of having investigated the density of the HCD-SiN film formed by changing the film-forming temperature in the method of 2nd Embodiment, and the density of the DCS-SiN film formed at the film-forming temperature of 700 degreeC. Process sectional drawing which shows the first half of the manufacturing method of the MOS transistor which concerns on the 3rd Embodiment of this invention Process sectional drawing which shows the middle half of the manufacturing method of the MOS transistor which concerns on the 3rd Embodiment of this invention Process sectional drawing which shows the second half of the manufacturing method of the MOS transistor which concerns on the 3rd Embodiment of this invention Sectional drawing equivalent to sectional drawing of FIG.14 (g) at the time of forming a dummy gate and a gate side wall insulating film only using a prior art Diagram showing the dependence of the etching rate of dilute hydrofluoric acid on the silicon nitride film formed using hexachlorodisilane. Figure Si raw material showing the relationship between the wet etching rate of the nitrogen flow rate and the silicon nitride film flowing during deposition of the silicon nitride film of Si ₂ Cl ₆ system Process sectional drawing which shows the manufacturing process of the semiconductor device based on 4th Example of this invention The figure which shows the SIMS profile of Cl and H before and behind heat processing of a HCD-SiN film | membrane. Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 5th Example of this invention The figure which shows the time-dependent change of the leakage current of various SiN films The figure which shows the relationship between the time until a SiN film | membrane breaks, and the Ci density | concentration in a SiN film | membrane. Process sectional drawing which shows the manufacturing process which concerns on 6th Example of this invention The figure which shows the SIMS profile of each element contained in the silicon nitride film which concerns on this invention The figure which shows the SIMS profile of each element contained in the silicon oxide film which concerns on this invention Process sectional drawing which shows the manufacturing process which concerns on 7th Example of this invention Process sectional drawing which shows the manufacturing process which concerns on the 8th Example of this invention. Process sectional drawing which shows the first half of the manufacturing method of the semiconductor device based on 9th Example of this invention Process sectional drawing which shows the second half of the manufacturing method of the semiconductor device based on 9th Example of this invention The figure which shows the result of the deposition temperature dependence of the dielectric constant of the silicon nitride film which has not introduce | transduced carbon The figure which shows the film formation temperature dependence of the RIE rate of the silicon nitride film which does not contain carbon The figure which shows the relationship between the RIE rate and the carbon concentration in the silicon nitride film The figure which shows a mode that the whole silicon nitride film was rounded by the RIE process. Sectional view of DRAM using the present invention and a conventional silicon nitride film The figure which shows the relationship between the carbon concentration of a silicon nitride film, and the etching rate by the diluted hydrofluoric acid of a silicon nitride film The figure for demonstrating the modification of 9th Example Sectional drawing which shows the cross section which cut | disconnected the conventional DRAM cell in the direction perpendicular | vertical to the channel length direction of MOS transistor Sectional drawing for demonstrating the problem in forming a silicon nitride film by LPCVD method using dichlorosilane etc. Sectional drawing for demonstrating the other problem in the case of forming a silicon nitride film by LPCVD method using dichlorosilane etc. Sectional view of the Cu wiring portion near the conventional Cu wiring The figure for explaining the reason why the silicon nitride film is formed by the LPCVD method

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101,121 ... Silicon substrate, 102 ... N-type drain diffusion layer, 103 ... Interlayer insulating film (SiO2 film), 104 ... Contact hole, 105 ... Wiring groove, 106 ... Silicon nitride film, 107 ... Ti layer, 108, 134 ... TiN film, 109 ... W buried wiring, 110 ... silicon nitride film (HCD-SiN film), 122 ... thermal oxide film, 123 ... element isolation insulating film, 124 ... polycrystalline silicon film, 125 ... HCD-SiN film, 126 ... Resist pattern, 127 ... dummy gate, 128 ... post oxide film, 129 ... diffusion layer (LDD), 130 ... gate sidewall DCS-SiN film, 131 ... source / drain diffusion layer, 132 ... interlayer insulation film, 133 ... gate insulation film 135 ... Al film, 200 ... gate electrode, 201 ... silicon substrate, 201 '... metal wiring, 203 ... TEOS interlayer oxide film, 04 ... TaN film, 205 ... SiN film, 206 ... source region, 207 ... drain region, 208 ... polysilicon film, 209 ... WN film, 210 ... W film, 211 ... gate sidewall insulating film, 212, 213 ... SiN film, 214 ... contact hole, 220 ... interlayer insulating film, 311 ... polysilicon film, 312 ... WN film, 313 ... W film, 314 ... gate insulating film, 315, 316, 317, 350 ... silicon nitride film, 318 ... BPSG film, 319 ... Source / drain diffusion layer, 320 ... recess, 330 ... silicon substrate, 331 ... element isolation trench, 332, 334 ... silicon oxide film, 350 ... base region, 351 ... recess, 352, 354 ... silicon nitride containing chlorine Films, 321, 335, 353, 355, 356... Silicon oxide films containing chlorine.

Claims (4)

Forming an interlayer insulating film on the main surface of the semiconductor substrate;
Forming a contact hole reaching the main surface of the semiconductor substrate in the interlayer insulating film;
Forming a silicon nitride film on the side wall of the contact hole;
Forming a barrier metal layer having a Ti layer and a TiN layer in a contact hole having a silicon nitride film formed on the side wall;
Forming a conductive layer in the contact hole in which the barrier metal layer is formed;
Using a mixed gas of Si _n Cl _{2n + 2} and NH ₃ (n is a natural number of 2 or more) and on the conductive layer in the contact hole so as to bury the inside of the contact hole at a film forming temperature of 700 ° C. or less. Forming a silicon nitride film containing chlorine in the LPCVD method;
And a step of removing the silicon nitride film outside the contact hole by CMP. Forming a sidewall insulating film on the sidewall of the gate electrode formed on the semiconductor substrate via the gate insulating film;
LPCVD at a film forming temperature of 700 ° C. or lower using a mixed gas of Si _n Cl _{2n + 2} and NH ₃ (n is a natural number of 2 or more) over the semiconductor substrate, the sidewall insulating film, and the gate electrode. Forming a silicon nitride film by a method;
Forming an interlayer insulating film on the silicon nitride film;
Forming a contact hole reaching the silicon nitride film in the interlayer insulating film beside the gate electrode;
And a step of removing the silicon nitride film exposed by the formation of the contact hole. _{3. The} method of manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film is formed by a mixed gas of Si ₂ Cl ₆ and NH ₃ . A dummy gate having a first silicon nitride film formed on a semiconductor substrate at a film forming temperature of 700 ° C. or lower using a mixed gas of Si _n Cl _{2n + 2} and NH ₃ (n is a natural number of 2 or more) . Forming a step;
Forming a first diffusion layer on the surface of the semiconductor substrate using the dummy gate as a mask;
Forming a second silicon nitride film on the sidewall of the dummy gate using dichlorosilane;
Forming a second diffusion layer on the surface of the semiconductor substrate using the dummy gate and the second silicon nitride film as a mask;
Forming an interlayer insulating film on the semiconductor substrate on which the second diffusion layer is formed and on the dummy gate;
Planarizing the interlayer insulating film using the first silicon nitride film as a stopper;
Removing the dummy gate exposed by the planarization step;
Forming a gate oxide film on the semiconductor substrate exposed by removing the dummy gate;
And a step of forming a metal film on the gate oxide film.

Images