KR20010051285A - Hdp capping layer or polish layre over hsq/peteos ild stack to enhance planarity and gap-fill - Google Patents

Abstract

PURPOSE: A HDP Capping layer or polish layer over HSQ/PETEOS ILD(inter level dielectrics) stack to enhance planarity and gap-fill is provided to form a dielectric stack with chemical and mechanical polishing process, without forming gaps, joints and divots. CONSTITUTION: The method forms an ILD, using high density plasma cap layers(HDP). A liner layer and an HSQ layer are deposited in a metal wire on a semiconductor body, followed by deposition of PETEOS layers on the HSQ layer. Gaps, joints or divots may be formed in the HSQ layer. Then HDP cap layers are deposited by means of high deposition ration to etching. The HDP processing forces to open any gaps to have them filed by the HDP materials. A structure formed through the method is subjected to chemical and mechanical polishing process after/before the HDP processing.

Description

HDP CAPPING LAYER OR POLISH LAYRE OVER HSQ / PETEOS ILD STACK TO ENHANCE PLANARITY AND GAP-FILL} over HSD / PEETOSOS ILD Stacks

The present invention relates generally to the field of interlayer dielectric layers for semiconductor devices, and more particularly to forming an interlayer dielectric (ILD) layer comprising a high density plasma (HDP) capping layer.

In modern integrated circuit (IC) technology, the rate limiting factor is no longer a transistor gate delay, but RC delays associated with interconnects. For this reason, considerable research has been undertaken to develop new low-k dielectric materials to reduce wiring capacitance. These dielectrics include hydrogen silsesquioxane (HSQ), fluorinated silicon dioxide (FSG), polymers and zerogels.

The development of new low dielectric constant materials also necessitated significant work in integrating these materials into the semiconductor manufacturing process flow.

Conventional fabrication methods for integrating HSQ into an interlayer dielectric (ILD) are described in FIGS. 1A-1C. As shown in FIG. 1A, after the metallization 12 is formed over the surface of the semiconductor substrate 10, plasma enhanced tetraethyoxysilane (PETOS) lines 14 are deposited over the metallization 12. An HSQ coat layer 16 is then deposited over the PETEOS line 14. Finally, a PETEOS polish layer 18 is deposited over the HSQ coat layer 16. Then, as shown in FIG. 1B, the stack is then chemically-mechanically polished (CMP). Typically the HSQ is cured after the coout step, PRTEOS polish layer deposition, or via etch.

In general, HSQ has good gap filling and local planarization capabilities (e.g., to completely fill a 0.21 m space between metal lines 0.21 m wide). However, gap filling and local planarization by HSQ is sensitive to the metal geometry. One of the problems sensitive to geometry is known as wicking. Where HSQ leaves the divote 20 there are metal structures with some unique geometry. When the PETEOS polish layer 18 is deposited over the HSQ 16, voids, seams, or large diverts 20 may be generated in the PETEOS. As shown in FIG. 1B, this void / seam / devote 20 may expand, ie, open during oxide or tungsten plug CMP. Expanded, flared voids / seams / devots may trap slurry or polish residues and may be partially or wholly filled with conductive material. The conductive material may be from via lines / barriers or fills (eg Ti, TiN, W or Al). Thus, the void / seam / devote 20 thus opened may cause defects that may result in shorts or leakage. 1C shows that the divote 20 filled with a conductive material can cause a short between the two metal wires 22 and 24.

The present invention is directed to a dielectric layer having an HDP capping layer or polish layer over at least one other dielectric layer. Other dielectric layers may include, for example, PETEOS polish layers overlying HSQ layers as interlayer dielectrics (ILDs) or doped silicate glass layers as poly-metal dielectrics (PMDs).

It is an advantage of the present invention to provide a method of forming a dielectric stack that is compatible with CMP without forming voids, seams or devots.

These and other advantages will be apparent to those of ordinary skill in the art from the detailed description of the invention with reference to the accompanying drawings.

1A-1C are cross-sectional views of conventional interlevel dielectrics using HSQ.

2A-2C are cross-sectional views showing a first attempt to form an ILD layer using HDP.

3A-3C are cross-sectional views showing a second attempt to form an ILD layer using HDP.

4A-4C illustrate cross-sectional views of an ILD with an HDP capping layer in accordance with a first embodiment of the present invention.

5A-5C illustrate cross-sectional views of an ILD with an HDP capping layer in accordance with a second embodiment of the present invention.

6A-6B illustrate cross-sectional views of PMDs with HDP capping layers in accordance with the present invention.

7 is a cross-sectional view of an alternative PMD with an HDP capping layer in accordance with the present invention.

<Explanation of symbols for main parts of drawing>

10, 100: semiconductor substrate

12, 102: metal wiring

14, 104: linear layer

16, 106: HSQ coat layer

18: PETEOS polish layer

20: void, seam, devoted

107: line

108: HDP layer

110, 310: polish layer

208, 308: HDP capping layer

210: filling layer

112, 212, 312: ILD

410: oxide

The present invention will now be described in connection with forming an interlayer dielectric layer using HSQ. It will be apparent to one of ordinary skill in the art that the HDP capping layer of the present invention may be applied to form thick dielectric layers or other dielectric stack layers dependent on CMP, such as a poly-metal dieletric (PMD) layer. .

One method of forming an interlayer dielectric using high density plasma (HDP) on the HSQ layer is described with reference to FIGS. 2A-2C. The HDP process involves simultaneously depositing and sputtering materials such as silicon dioxide. HDP oxide deposition takes place simultaneously with a mixture containing silicon (eg SiH ₄ ), a mixture containing oxygen (eg O ₂ ), non-reactive gases (eg non-corrosive gases such as Ar). It is defined as chemical vapor deposition with dc-bias sputtering. This method usually forms high quality oxides with good thermal stability, low water absorption and good mechanical properties. Process variables such as gas flow rates, wafer temperatures, source RF power and bias RF power can be attributed to the SiO ₂ film on the surface due to the reaction between SiH ₄ and O _2. It is optimized so that there is deposition of. The bias RF power is tailored such that the selected value of the supply RF power controls the sputtering temperature. Typically higher bias RF power results in more sputtering of the deposited film. Simultaneous deposition and dc-bias sputtering enhance the gap filling capabilities. In general, higher etch to deposition ratios (E / D ratios) lead to better gap fills. As an example, the E / D ratio may be in the range 0.25-0.35. Preferably the E / D ratio is in the range of 0.28-0.32 according to chuck life. HDP is expected to fill voids / seams / devots in HSQ since it has good gap filling capability. HDP oxide deposition was issued on February 27, 96, which is further described in US Pat. No. 5,494,854, which is incorporated herein by reference.

Referring to FIG. 2A, a linear layer 104 is deposited over the semiconductor substrate 100 and the metal lines 102. For example, the semiconductor substrate 100 may include transistors formed in a silicon substrate and in a PMD layer that insulates these transistors from the first layer of the metallization except the portion where the contacts are formed. The metal wires 102 may be part of the first or any subsequent metal wiring layer except for most wiring layers of the upper layer. The method of forming the semiconductor substrate 100 and the metal wires 102 is a well known technique.

Linear layer 104 is a thin conformal dielectric layer. The thickness of the linear layer 104 may be in the range of 200 ns-1000 ns. For example, linear layer 104 may comprise a PETEOS material. Next, the HSQ coat layer 106 is deposited. The HSQ coat layer 106 is deposited to a thickness such that a space is filled between the narrow metal wires.

Referring to FIG. 2B, an HDP layer 108 is next formed. Because the HDP process has both deposition and etch components, some of the HSQ coout layer 106 is removed. For example, the HDP layer 108 may include silicon dioxide (undoped), F (fluorine) HDP oxide (HDP-FSG), phosphorus doped HDP oxide (HDP-PSG), or the like. HDP-PSG is particularly useful for PMD applications.

The polish layer 110 is then deposited. For example, PETEOS may be used. The structure is CMP'd as shown in FIG. 2C. Prior art voids / seams / devots are removed.

Since some of the HSQ material is removed during the deposition of the HDP layer 108, a portion of the HDP layer 108 is deposited between the metal lines. HDP silicon dioxide has a dielectric constant (approximately 4.0-4.3) that is significantly greater than that of HSQ (approximately 2.7-3.0). The resulting capacitance of ILD 112 is greater than the prior art attempts. Sputtered HSQ materials can also be deposited in HDP deposition chambers and cause potential contamination.

A second attempt to form an interlayer dielectric using a high density plasma (HDP) layer over the HSQ layer is described with reference to FIGS. 3A-3C. Referring to FIG. 3A, a linear layer 104 is deposited over the semiconductor substrate 100 and the metal lines 102 as in the first trial. Linear layer 104 is a thin conformal dielectric layer. The thickness of the linear layer 104 may be in the range of 200 ns-1000 ns. For example, linear layer 104 may comprise a PETEOS material. Next, the HSQ coat layer 106 is deposited. The HSQ coat layer 106 is deposited to a thickness such that a space is filled between the narrow metal wires.

Referring to FIG. 3B, a thin oxide line 107 is deposited over the HSQ coout layer 106. The HDP layer 108 is then formed using a lower etch to deposition (E / D) ratio to ensure that all of the lines 107 are not removed. For example, HDP layer 108 may include silicon dioxide (undoped), HDP-FSG, HDP-PSG, or the like. The polish layer 110 is then deposited. For example, PETEOS may be used. The structure is CMP'd as shown in Figure 3c. The voids / seams / devots of the prior art are removed.

Temporary oxide line 107 increases the cost. In addition, low E / D ratios may result in poor gap filling and may actually show voids / seams / devots. The high E / D ratio will corrode the line and also erode some of the HSQ resulting in a higher overall dielectric constant for the ILD 112 as described above in connection with the first attempt. .

According to a first embodiment of the invention, the ILD 212 will now be described with reference to FIGS. 4A-4C. Referring to FIG. 4A, a linear layer 104 is deposited over the semiconductor substrate 100 and the metal lines 102. For example, the semiconductor substrate 100 may include transistors formed in a silicon substrate and in a PMD layer that insulates these transistors from the first layer of the metallization except the portion where the contacts are formed. The metal wires 102 may be part of the first or any subsequent metal wiring layer except for most wiring layers of the upper layer. The method of forming the semiconductor substrate 100 and the metal wires 102 is a well known technique.

Linear layer 104 is a thin conformal dielectric layer. The thickness of the linear layer 104 may be in the range of 200 ns-1000 ns. For example, linear layer 104 may comprise a PETEOS material. Alternative materials may include thin (˜50 μs-200 μs) silicon nitride, inorganic low k lines such as FSG lines, and organic low k lines such as polymer lines. The use of low k lines can further lower capacitance. In addition, the linear layer 104 may be omitted as it is possible to deposit the HSQ directly on the metal.

Next, the HSQ coat layer 106 is deposited. The HSQ coat layer 106 is deposited to a thickness such that space is filled between the narrow metal wires.

Next, a filler layer 210 may be deposited. For example, the filling layer may comprise PETEOS. The filling layer may be similar to the polish layer 110 in the previous example, except that the filling layer may be thinner. For example, the filling layer 210 may have a thickness within the range of 2000 kV-10000 kPa. The material of the packed layer 210 should have a dielectric constant less than or equal to that of PETEOS (ie, <= 4.2). Moreover, the more conformal the deposition of the packed layer 210, the better. Alternative examples include FSG and PSG.

As shown in FIG. 4A, after deposition of the fill layer 210, the void / seam / devote 20 may appear as in the prior art. As shown in FIG. 4B, HDP capping layer 208 is then deposited with a high enough E / D ratio for good gap filling. The high E / D ratio results in some of the filling layer 210 being removed. As such, voids / seams / devots 20 appear during this process and are again filled with the material of the HDP capping layer 208. In a preferred embodiment, the HDP capping layer 208 includes silicon dioxide (Si0 ₂ ). However, HDP deposition of alternative materials such as silicon nitride, silicon oxynitride, FSG or PSG may be used. The thickness of the HDP capping layer 208 is in the range of 5000 kV-15000 kPa.

As shown in FIG. 4C, after deposition of the HDP capping layer 208, the ILD 212 is CMP'd for planarization. The process may then continue with the formation and packaging of additional wiring layers as desired. The additional wiring layer may include ILDs such as ILD 212.

According to a second embodiment of the invention, the ILD 312 will now be described with reference to FIGS. 5A-5C. Referring to FIG. 5A, a linear layer 104 is deposited over the semiconductor substrate 100 and the metal lines 102. For example, the semiconductor substrate 100 may include transistors formed in a silicon substrate and in a PMD layer that insulates these transistors from the first layer of the metallization except the portion where the contacts are formed. The metal wires 102 may be part of the first or any subsequent metal wiring layer except for most wiring layers of the upper layer. The method of forming the semiconductor substrate 100 and the metal wires 102 is a well known technique.

Linear layer 104 is a thin conformal dielectric layer. The thickness of the linear layer 104 may be in the range of 200 ns-1000 ns. For example, linear layer 104 may comprise a PETEOS material. Next, the HSQ coat layer 106 is deposited. The HSQ coat layer 106 is deposited to a thickness such that space is filled between the narrow metal wires.

The polish layer 310 may then be deposited. For example, the polish layer 310 may include a PETEOS material. The polish layer 310 may have a thickness in the range of 10000 kPa-20000 kPa. As shown in FIG. 5A, after deposition of the polish layer 310, void / seam / devotes 20 may appear as in the prior art.

Referring to FIG. 5B, the polish layer 310 is then CMP'd for planarization. The CMP process can be tailored to somewhat thinner objects such that the last ILD 312 thickness is the same as in the prior art. Alternatively, the thickness of the last ILD 312 may be somewhat larger than the prior art. During CMP, void / seam / devote 20 may appear.

As shown in FIG. 5C, a thin HDP capping layer 308 is then deposited with a high E / D ratio for good gap filling. The high E / D ratio results in the slight removal of the polish layer 310. The revealed void / seam / devote 20 is filled with the material of the HDP capping layer 308. In a preferred embodiment, the HDP capping layer 308 includes silicon dioxide (Si0 ₂ ). However, HDP deposition of alternative materials such as silicon nitride, silicon oxynitride, or HDP-FSG may be used. The thickness of the HDP capping layer 308 is in the range of 1000 ns-5000 ns.

The process may then continue with the formation and packaging of additional wiring layers as desired. The additional wiring layer may include ILDs such as ILD 312.

While the present invention has been described in connection with specific embodiments, it is not intended that the description be understood in a limiting sense. Various modifications and combinations of specific embodiments as well as other specific embodiments of the invention will be apparent to those of ordinary skill in the art with reference to the description. For example, the HDP capping layer of the invention can also be applied to PMD layers as well. For PMDs, the gap filling is filled with phosphorus doped (PSG), or boron (B) and phosphorus doped (BPSG) silicate free oxide, or undoped oxide in tight polysilicon spaces. It is being tried. As shown in FIG. 6A, voids / seams / devots 20 may be revealed within post-CMP oxide 410. HDP capping layers 208 or 308 may further be applied to the PMD. FIG. 6B shows the application of the first embodiment of the invention to a PMD layer, and FIG. 7 shows the application of the second embodiment of the invention to a PMD layer. The appended claims are therefore to be construed as including any such modifications or embodiments.

According to the present invention it is possible to form a dielectric stack that is compatible with CMP without forming voids, seams or devots.

Claims (12)

In the method of manufacturing an integrated circuit (IC), Forming a dielectric layer over the semiconductor substrate, the dielectric layer comprising at least one divert; And Forming the capping layer over the dielectric layer using a high density plasma (HDP) process to fill the at least one divote with a capping layer Method comprising a. The method of claim 1, Forming a linear layer on the semiconductor substrate; And Forming a hydrogen silsesquioxane (HSQ) layer on the linear layer before forming the dielectric layer Method further comprising a. The method of claim 2, wherein the linear layer comprises plasma enhanced tetraethyoxysilane (PETOS). The method of claim 1 wherein the dielectric layer comprises PETEOS. 2. The method of claim 1, further comprising chemically mechanically polyspun (CMP) the dielectric layer prior to the capping layer deposition step. The method of claim 1, further comprising chemically mechanically polyspun (CMP) the capping layer. The method of claim 1 wherein the capping layer comprises HDP silicon dioxide. The method of claim 1, wherein the capping layer comprises HDP silicon nitride. The method of claim 1 wherein the capping layer comprises HDP silicon oxynitride. The method of claim 1 wherein the capping layer comprises fluorinated HDP oxide. The method of claim 1, wherein the capping layer comprises HDP oxide doped with phosphorus. The method of claim 1, wherein the HDP process has an etch to deposition ratio (E / D) in the range of 0.25-0.35.