JP4679277B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device to be obtained, and more particularly to a method for manufacturing a semiconductor device including a chemical mechanical polishing (CMP) process for polishing and planarizing a film to be polished and a semiconductor device to be obtained. .

  In a method for manufacturing a semiconductor device, chemical mechanical polishing (CMP) is used. Chemical mechanical polishing forms recesses such as grooves in the base, forms films that fill the recesses, removes unnecessary films on the surface, forms damascene wiring, shallow trench isolation (STI), etc. An insulating film is deposited on a base having irregularities on the surface on which wiring and the like are formed, and is used for surface flattening of the insulating film for flattening the surface. By flattening the surface, it is possible to improve the accuracy of the photolithography process having only a shallow depth of focus and the uniformity of the etching process.

  For example, in STI formation, the silicon substrate surface is thermally oxidized to form a buffer silicon oxide film, a silicon nitride film is deposited thereon, an opening corresponding to the STI is formed in silicon nitride by photolithography and etching, Etch the trench in the silicon substrate. The silicon nitride film functions as an etching mask and also functions as a stopper in later CMP.

  The silicon surface exposed in the trench is thermally oxidized to form a silicon oxide film liner, a silicon nitride film is deposited to form a silicon nitride film liner, and then an insulating film such as undoped silicate glass (USG) is formed in the trench. Embed with film. High density plasma (HDP) chemical vapor deposition (CVD) has been used to fill the miniaturized trenches with USG films. The USG film deposited outside the trench is removed by CMP. After the CMP, the exposed silicon nitride film is etched with hot phosphoric acid or the like, and the buffer silicon oxide film is etched with dilute hydrofluoric acid or the like.

  In forming the gate electrode of the MOS transistor, a silicon oxide film is formed on the surface of the active region of the silicon substrate by thermal oxidation, and nitrogen is introduced as necessary to form a gate insulating film. A polycrystalline silicon film is deposited on the gate insulating film and patterned into a gate electrode shape. After ion implantation for forming source / drain extension regions, sidewall spacers are formed, and ion implantation for forming high-concentration source / drain regions is performed. After performing a silicidation step as necessary, a phosphosilicate glass (PSG) film, which is a silicon oxide film containing phosphorus, is deposited to form an interlayer insulating film covering the gate electrode.

  The interlayer insulating film covering the gate electrode has irregularities on the surface. In order to remove the unevenness, the surface of the interlayer insulating film is planarized by CMP. The interlayer insulating film to be deposited is made thick enough for CMP polishing. After planarization, the contact hole for the source / drain or the like is etched, and a conductive plug such as polycrystalline silicon or tungsten is buried in the contact hole. An unnecessary conductive layer on the interlayer insulating film is removed by CMP.

In CMP, for example, an abrasive containing abrasive grains made of silica and an additive made of KOH was used. As an abrasive that achieves higher planarization, an abrasive containing cerium oxide (ceria, cerium dioxide CeO ₂ ) as abrasive grains and an ammonium polyacrylate, polyvinyl pyrrolidone, or the like as an additive has been proposed. An abrasive in which cerium oxide is mixed with water has a very high polishing rate and a low step relief function. For example, when an appropriate amount of poly (ammonium acrylate) salt is added, the polishing rate can be controlled to an appropriate value, polishing at the recesses is suppressed and the leveling function is enhanced, and when the polishing surface is flattened, automatic stop (auto stop) Create function.

JP 2001-009702 A JP 2001-085373 A JP, 2000-248263, A As a technique of detecting the polish end point in which the unevenness of the polish surface disappeared, the technique of detecting the temperature and the rotation torque of the polish surface is also proposed. JP, 11-104955, A In order to achieve high planarization, a method of dividing CMP into two stages and performing two stages of CMP under different conditions has been proposed. For example, the main polishing is performed with the first polishing pad while supplying the abrasive, and then the polishing is stopped and the final polishing is performed using the second polishing pad harder than the first polishing pad while supplying water. To prevent dishing. A polishing apparatus that performs CMP includes a rotatable polishing table having a polishing surface, a rotatable polishing head that holds a substrate, and a plurality of nozzles that supply abrasive and pure water. While applying a pressing force to press the polishing head against the polishing table, the polishing head and the polishing table are rotated, and polishing is performed while supplying an abrasive. The semiconductor integrated circuit device is increasingly miniaturized and highly integrated. The gate length of the MOS transistor is as short as 90 nm and 65 nm. The lowest layer wiring that can be placed in the integrated circuit device is a gate wiring. Along with miniaturization, the interval between the gate wirings becomes narrower and the wirings become denser. After the gate wiring is formed, a PSG film is deposited to form an interlayer insulating film that embeds the gate wiring. Conventionally, a PSG film has been deposited by plasma (PE) CVD that applies high-frequency power between the counter electrodes. However, as the gate interval decreases, the embedding performance becomes insufficient, and an attempt is made to embed a narrow gap. There are times when it enters. In order to fill a narrow gap with a PSG film, high density plasma (HDP) CVD that applies high frequency power to the inductive coupling coil has been used instead of PE-CVD.

  An object of the present invention is to provide a method of manufacturing a semiconductor device having excellent uniformity of thickness of an interlayer insulating film at a wafer level.

  Another object of the present invention is to provide a semiconductor device manufacturing method including an efficient CMP process.

According to one aspect of the present invention,
(A) forming a wiring above the semiconductor substrate;
(B) After the step (a), a step of burying the wiring and depositing a first insulating film by high density plasma (HDP) chemical vapor deposition (CVD);
(C) After step (b), depositing a second insulating film above the first insulating film by a deposition method other than HDP-CVD;
After the step (d) (c), a step of flattening the previous SL second insulating film,
Only including,
Step (d) is a first step performed using a first slurry containing cerium dioxide abrasive grains and an additive, and a second step carried out using a second slurry containing silica abrasive grains after the first step. Then, after the second step, there is provided a method for manufacturing a semiconductor device including a third step performed using the first slurry and pure water .

  When an interlayer insulating film is deposited by HDP-CVD, the thickness varies at the wafer level. By combining HDP-CVD and another deposition method, an interlayer insulating film having a uniform thickness can be formed.

  After forming a trench in a silicon substrate, a USG film is deposited by HDP-CVD, an unnecessary portion is removed by CMP using a polishing agent containing cerium dioxide oxide grains, an STI is formed, and a PSG film is formed after forming a gate electrode It has been found that new problems arise when deposited by HDP-CVD and planarized with an abrasive containing cerium dioxide abrasive grains.

  Hereinafter, an experiment conducted by the present inventor in order to investigate this problem will be described.

  As shown in FIG. 1A, a wafer WAF having a silicon oxide film OX formed on a silicon substrate SUB was created. Three types of samples as silicon oxide film OX, a sample in which USG film HDP-USG is deposited by HDP-CVD, a sample in which PSG film HDP-PSG is deposited by HDP-CVD, and tetraethoxysilane used for an interlayer insulating film, etc. A sample in which a TEOS oxide film PE-TEOS was deposited by PE-CVD using (TEOS) as a silicon source was prepared.

  FIG. 1B is a graph showing the results of measuring the in-wafer thickness distribution of the silicon oxide film for three types of samples. The film thickness distribution of the sample PE-TEOS in which the TEOS oxide film is formed by PE-CVD shows a value of about 580 nm over almost the entire surface of the wafer, and the uniformity is extremely high. The film thickness distributions of the two samples HDP-USG and HDP-PSG in which the silicon oxide film was formed by HDP-CVD showed almost the same fluctuation at the wafer level. A substantially M-shaped distribution is shown which is as thin as about 570 nm at the wafer central portion, gradually increases toward the periphery, and becomes thinner to 585 nm or less toward the rear peripheral portion showing the maximum value of about 592 nm.

  This M-shaped distribution is a large gradual change at the wafer level and does not fluctuate locally. Although local thickness variations can be planarized by CMP, it is expected that such a gradual thickness distribution over a large area cannot be planarized by CMP.

  In a chip formed from the wafer central portion, the interlayer insulating film is thin, and in a chip formed from the wafer peripheral portion, the interlayer insulating film is thick. When etching a contact hole penetrating the interlayer insulating film, a large amount of over-etching is performed in the central portion so that the contact hole also penetrates in the peripheral portion. When the conductive plug is embedded in the contact hole, the conductive plug of the chip formed from the central portion is short, the connection resistance is low, the conductive plug of the chip formed from the peripheral portion is long, and the connection resistance is high. In order to increase the reliability of processes and products, it is desirable to suppress the wafer level thickness variation as much as possible. Next, the three types of samples were polished using a slurry containing ceria abrasive grains and a surfactant.

  FIG. 2A schematically shows the configuration of the polishing apparatus. A polishing pad 104 is provided on the polishing table 102. The wafer WAF was supported by the polishing head 112 with the silicon oxide film facing down. Slurry was dropped from the nozzle 124a onto the polishing table, pressure was applied to the polishing head, and polishing was performed by rotating the polishing table 102 and the polishing head 112 counterclockwise.

FIG. 2B shows the polishing rate when three types of samples are CMPed for 1 minute using the same slurry. The vertical axis represents the polishing rate in units of nm / min. The film thickness before and after polishing was measured, and the polishing rate was calculated by dividing the decrease in film thickness by the polishing time. The polishing conditions are as follows.
Polishing head pressure: 200 g weight / cm ²
Polishing head rotation speed: 100 rotations / minute,
Polishing table rotation speed: 100 rotations / minute,
Ceria slurry supply rate: 0.2 l / min.

  The polishing pad used was an IC1400K groove type manufactured by Nitta Haas, and the ceria slurry used was a microplanar STI2100 RA9 manufactured by DuPont Air Products Nanomaterials. The film thickness measurement was performed using a film thickness measuring apparatus ASET F5x manufactured by KLA-TENCOR.

  The polishing rate of the HDP-USG film is 12 nm / min and the polishing rate of the PE-TEOS film is 14 nm / min, both of which are extremely low, and the polishing hardly progresses. It can be seen that the auto-stop property, which is a feature of the ceria slurry containing the ammonium polyacrylate, is worked when a flat film to be polished is polished. The average polishing rate of the HDP-PSG film was 210 nm / min. Compared to 12 nm / min and 14 nm / min, it is extremely high, and it can be seen that the auto-stop function does not work.

  FIG. 2C shows the polishing rate of the HDP-PSG film when the amount of polyacrylic acid ammonium salt in the ceria slurry is changed. The low concentration on the left is the same as in FIG. 2B, and the high concentration on the right is when the amount of ammonium polyacrylate is increased about 10 times. When the amount of ammonium polyacrylate is increased to about 10 times, the auto-stopping property also works for the HDP-PSG film.

  From the results shown in FIGS. 2B and 2C, when the HDP-USG film and the HDP-PSG film are to be CMPed with ceria slurry containing ammonium polyacrylate, the amount of ammonium polyacrylate must be significantly changed. I understand. When the buried oxide film of STI is formed of an HDP-USG film and the interlayer insulating film on the gate electrode is formed of an HDP-PSG film, the CMP for each must be different. If CMP performed by one polishing apparatus is fixed to one type, two polishing apparatuses are required to perform two types of CMP.

  By the way, the polishing rate of the PE-TEOS film is almost the same as the polishing rate of the HDP-USG film. If the HDP-USG film and the PE-TEOS film are to be CMPed, the same kind of ceria slurry can be used under the same conditions. However, the PE-TEOS film has inferior embedding characteristics, and an interlayer insulating film for embedding the gate electrode cannot be formed of the PE-TEOS film.

  In view of this, an interlayer insulating film for embedding the gate electrode was considered to be formed by stacking an HDP-PSG film and a PE-TEOS film. A gate electrode is embedded with an HDP-PSG film, a PE-TEOS film is laminated thereon, and a polishing target is a PE-TEOS film.

  3A to 3G are partial cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 3A, the surface of the semiconductor substrate 10 which is a silicon wafer is thermally oxidized to form a silicon oxide film 12 having a thickness of about 10 nm. A silicon nitride film 13 is deposited on the silicon oxide film 12 to a thickness of about 100 nm by chemical vapor deposition (CVD). An opening 14 exposing the surface of the semiconductor substrate 10 is formed in the silicon nitride film 13 and the silicon oxide film 12 by photolithography and etching. Here, the resist pattern formed by photolithography may be removed. The semiconductor substrate 10 is anisotropically etched by reactive ion etching (RIE) using at least the silicon nitride film 13 in which the openings 14 are formed as a mask. For example, a trench 15 having a depth of about 300 nm from the surface of the silicon nitride film 13 is formed. Form. It is preferable to etch the side surface of the trench under an inclined condition.

  As shown in FIG. 3B, the silicon surface exposed on the trench surface is thermally oxidized to form a silicon oxide film (liner) 17 having a thickness of about 1 to 5 nm, for example. For example, a silicon nitride film (liner) 18 having a thickness of about 2 to 8 nm is deposited by low pressure (LP) CVD so as to cover the surfaces of the silicon oxide film 17 and the silicon nitride film 13. The silicon oxide film having a thickness of about 1 to 5 nm has a thickness that makes it difficult for dilute hydrofluoric acid to enter, and the silicon nitride film having a thickness of about 2 to 8 nm has a thickness that makes it difficult for hot phosphoric acid to enter. On the semiconductor substrate on which the silicon nitride film 18 is formed, a silicon oxide film 20 having a thickness of, for example, about 450 nm is deposited by high density plasma (HDP) CVD. The trench 15 is filled with a silicon oxide film 20. The silicon oxide film 20 above the surface of the silicon nitride film 13 (and the silicon nitride film 18) becomes a film to be polished.

  As the size of the wafer increases, it becomes not always easy to remove the silicon oxide film for STI by CMP on the entire surface of the wafer. A CMP residue may remain in the center of the wafer, resulting in a defective chip.

  Using the polishing apparatus shown in FIG. 2A, the semiconductor substrate 10 is supported by the polishing head 112 so that the film to be polished 20 faces down. The polishing head 112 is lowered while rotating, and the semiconductor substrate 10 is pressed onto the polishing pad 104 of the rotating polishing table 102 while supplying a polishing agent containing ceria abrasive grains and additives from the nozzle 124a.

As shown in FIG. 3C, main polishing is performed until the surface unevenness disappears, and the surface of the polishing target film 20 is flattened. For example, the main polishing may be performed under the following conditions.
The pressure presses the polishing head to the polishing pad: 100 to 500 g weight / cm ^2, for example, 210g weight / ^cm 2,
The number of revolutions of the polishing head: 70 to 150 revolutions / minute, for example 142 revolutions / minute,
The number of rotations of the polishing table: 70 to 150 rotations / minute, for example, 140 rotations / minute,
Abrasive: Abrasive containing pure ceria abrasive as polishing abrasive and ammonium polyacrylate as additive (for example, DuPont Air Product Nanomaterials, model number Micro Planer STI2100),
Abrasive supply amount: 0.1 to 0.3 liter / minute, for example, 0.15 liter / minute,
Abrasive supply position: center of polishing table (polishing pad).

  When the main polishing is completed and the surface of the silicon oxide film 20 is flattened, pure water is supplied from the nozzle 124b and the polishing agent is poured away. There is a possibility that the additive adhering to the surface of the semiconductor substrate cannot be removed only by this pure water washing step.

Next, preliminary polishing for final polishing is performed. The preliminary polishing for the final polishing is performed, for example, by supplying a silica-based polishing agent from the nozzle 124c to the center of the polishing pad. As the silica-based abrasive, for example, an abrasive of model number SEMI SPRES 25 manufactured by Cabot Corporation can be used. While rotating the polishing head 112, the polishing head 112 is pressed onto the polishing pad 104 of the rotating polishing table 102. The preliminary polishing for the final polishing may be performed, for example, under the following conditions.
Polishing pressure: 100~500g heavy / cm ^2, for example, 210g weight / ^cm 2,
The number of revolutions of the polishing head: 70 to 150 revolutions / minute, for example, 122 revolutions / minute,
The number of rotations of the polishing table: 70 to 150 rotations / minute, for example, 120 rotations / minute,
Abrasive supply amount: 0.05 to 0.3 liter / minute, for example, 0.1 liter / minute,
Polishing amount (time): film thickness of 10 nm or less, for example, preliminary polishing for final polishing for about 5 seconds is to remove an additive that may be adhered by removing the surface of the film to be polished shallowly, The silicon nitride films 18 and 13 are preferably not exposed.

  After preliminary polishing, pure water is supplied from the nozzle 124b for about 10 seconds, for example, and the silica-based abrasive is poured away. If the silica-based abrasive remains, the selectivity of finish polishing can be degraded.

  Thereafter, as shown in FIG. 3D, final polishing for final polishing is performed by supplying a ceria-based abrasive from the nozzle 124a and pure water from the nozzle 124b. For example, the ceria-based abrasive is supplied in the center of the polishing pad, and the pure water is supplied outside. However, the supply position is not limited to this. Both the polishing head and the polishing pad are rotated.

For example, the final polishing is performed under the following conditions.
Polishing pressure: 100 to 500 g weight / cm ^2, for example, 210g weight / ^cm 2,
The number of revolutions of the polishing head: 70 to 150 revolutions / minute, for example, 122 revolutions / minute,
The number of rotations of the polishing table: 70 to 150 rotations / minute, for example, 120 rotations / minute,
Abrasive supply amount: 0.05 to 0.3 liter / minute, for example 0.05 liter / minute,
Pure water supply amount: 0.05 to 0.3 liter / minute, for example, 0.15 liter / minute,
Polishing amount (time): For example, about 60 seconds until the silicon nitride film is exposed.

  Note that the conditions of the final polishing of the final polishing are not limited to the above. It suffices if the silicon oxide film on the silicon nitride film 13 (silicon nitride film 18) is removed and the silicon nitride film is exposed. The thin silicon nitride film 18 may be removed or left.

  As shown in FIG. 3E, the silicon nitride film 13 (18) is etched with, for example, hot phosphoric acid, and the silicon oxide film 12 is etched with dilute hydrofluoric acid. The embedded silicon oxide film 20, the silicon oxide film 17 and the silicon nitride film 18 sandwiched between the semiconductor substrates 10 may not be etched. If the above-described film thickness is preferable, etching can be suppressed because the etchant hardly enters.

  Thus, by performing the preliminary polishing of the final polishing by physical polishing before the final polishing of the final polishing, even if the additive is attached to the wafer surface, the additive can be surely removed. Even with a large-diameter wafer, the entire silicon oxide film can be removed.

  As shown in FIG. 3F, using a resist mask, ions are implanted into the semiconductor substrate to form a p-channel transistor n-type well NW and an n-channel transistor p-type well PW. The surface of the active region defined by STI is thermally oxidized to form a silicon oxide film, and further nitrogen treatment is performed to introduce nitrogen to form a silicon nitride oxide film. A polycrystalline silicon film having a thickness of 100 to 200 nm, for example, 180 nm is deposited on the silicon nitride oxide film by thermal CVD and patterned using a resist pattern. In this way, an insulated gate electrode is formed. A p-type impurity is implanted into the p-channel transistor region and an n-type impurity is ion-implanted into the n-channel transistor region with a low acceleration energy and a low concentration to form a shallow extension. After the sidewall SW is formed of silicon oxide or the like, p-type impurities are implanted into the p-channel transistor region and n-type impurities are ion-implanted at a high concentration into the n-channel transistor region, so that the low resistance source / drain regions S / Dp, S / Dn Form. In this way, a CMOS structure is formed.

  A PSG film 41 having a thickness equal to or greater than the thickness of the gate electrode, for example, a thickness of 200 nm is deposited by HDP-CVD so as to embed the gate electrode, and a space between the gate electrodes is buried. Since HDP-CVD is used instead of PE-CVD, the embedding characteristics are good, and the space between the gate electrodes is completely buried. The surface of the PSG film 41 shows irregularities reflecting the gate electrode.

  As shown in FIG. 3G, a TEOS oxide film 42 is deposited to a thickness of, for example, 250 nm on the PSG film 41 by PE-CVD. Since the surface of the HDP-PSG film 41 relaxes the curvature and aspect ratio of the underlying surface, there is no problem with the embedding characteristics even in PE-CVD having inferior embedding characteristics. An interlayer insulating film 40 is formed by stacking the HDP-PSG film 41 and the PE-TEOS film 42. As a comparative example, a sample in which the interlayer insulating film 40 was formed with a single HDP-PSG film was also prepared. In this state, the film thickness distribution of the interlayer insulating film on the wafer was investigated.

  FIG. 3H shows the measurement result of the film thickness distribution. The film thickness distribution of the sample in which the interlayer insulating film 40 is formed of a single HDP-PSG film film shows an M-shaped distribution similar to the film thickness distribution shown in FIG. 1B, and increases toward the periphery by about 440 nm at the wafer center. After showing the maximum value of about 462 nm, it decreased toward the periphery and became about 453 nm.

  The film thickness distribution of the sample in which the interlayer insulating film 40 was formed by stacking the HDP-PSG film 41 and the PE-TEOS film 42 showed a substantially flat and stable value of about 450 nm over almost the entire surface of the wafer. Although the cause is unknown, a flat surface could be obtained by laminating an HDP-CVD film and a PE-CVD film. Therefore, the thickness distribution of the interlayer insulating film 40 was examined by changing the thickness of the lower interlayer insulating film 41.

  FIG. 4 is a graph showing the measurement results of the film thickness distribution. Based on the thickness of the wiring (gate electrode), a PSG film 41 having a height higher than the wiring height was deposited by HDP-PSG, and a TEOS oxide film was deposited thereon by PE-CVD. The horizontal axis indicates the ratio of the HDP-PSG film thickness to the wiring height. The vertical axis shows the film thickness variation in arbitrary units. In the region where the multiple of the wiring height is 2.5 or more, the variation seems to increase almost in proportion to the multiple. In the region where the multiple is 2 or less, the variation that decreases as the multiple decreases is small. In order to suppress variations in the film thickness, it is preferable to form an HDP-PSG film having a thickness of 2 times or less, preferably 1.5 times or less the wiring height.

As shown in FIG. 5A, the interlayer insulating film 40 formed by stacking the HDP-PSG film 41 and the PE-TEOS film 42 is polished in two steps. First, polishing in the first step until the unevenness on the surface of the interlayer insulating film 40 disappears is performed. Polishing is performed up to P1 in the figure. This polishing is performed by CMP with an auto-stop function. The specific polishing conditions were as follows.
Polishing head pressure: 200 g weight;
Polishing head rotation speed: 100 rotations / minute;
Polishing table rotation speed: 100 rotations / minute;
Ceria slurry supply rate: 0.2 l / min.
The polishing pad used for polishing was an IC1400 K groove type manufactured by Nitta Haas, and the ceria slurry used was a microplanar STI2100RA9 manufactured by DuPont Air Products Nanomaterials. The polishing time was 100 seconds.

  Polishing consumes a film to be polished and also gives scratches to the polished surface. When the auto stop function is activated, the consumption of the surface to be polished decreases rapidly. However, the scratch applied to the polished surface hardly changes. If the surface to be polished is consumed, the scratch once formed is also consumed, but if the surface to be polished is not consumed, scratches are accumulated more and more.

The second polishing step is polishing that reduces the scratches under conditions where a certain polishing rate is obtained by reducing the auto-stop property. In order to alleviate the auto-stop property, the amount of ceria slurry supplied was reduced, and polishing was performed to the surface P2 while supplying water. Specific polishing conditions were as follows.
Polishing head pressure: 200 g weight;
Polishing head rotation speed: 100 rotations / minute;
Polishing table rotation speed: 100 rotations / minute;
Ceria slurry supply rate: 0.1 liter / min;
Water supply: 0.35 liter / min.
The polishing pad used for polishing was an IC1400 K groove type manufactured by Nitta Haas, and the ceria slurry used was a microplanar STI2100RA9 manufactured by DuPont Air Products Nanomaterials. This is the same type of slurry as the ceria slurry used in the first step. The ceria slurry was diluted on the polishing table. Cost is lower than using pre-diluted slurry. The polishing rate in the second step was 100 nm / min.

  As shown in FIG. 5B, the nozzle 124b for supplying pure water was disposed more outward from the center of the polishing table than the nozzle 124a for supplying ceria slurry, and the ceria slurry was diluted on the polishing table.

  FIG. 5C shows the number of scratches after the first step and after the second step. The left side shows the number of scratches after polishing in the first step. As many as 300 scratches are formed. The right side shows the number of scratches after the end of the second step. While the number of scratches after the first step was about 300, the number of scratches after the second step was greatly reduced to about 10.

  FIG. 5D shows the film thickness distribution after polishing. The film thickness distribution of the comparative sample (PSG single-layer interlayer insulating film formed by HDP-CVD) is also shown. In the comparative sample, the film thickness at the wafer center is about 316 nm, increases toward the periphery to about 332 nm, and then decreases to about 323 nm. M-shaped distribution continues. The interlayer insulating film according to the example shows a stable film thickness of about 320 nm on almost the entire surface of the wafer. It can be seen that the thickness variation of the entire wafer is prevented by the laminated interlayer insulating film of the embodiment. Further, using the same type of ceria slurry as that used for STI CMP, CMP of the interlayer insulating film on the gate electrode can be suitably performed.

Note that pure water cleaning may be inserted between the first step CMP and the second step CMP. Furthermore, it is also possible to insert a physical polishing as needed. When physical polishing is inserted, it may be preferable to perform pure water cleaning thereafter. The example in which the lower interlayer insulating film is deposited higher than the wiring (gate electrode) height has been described. However, the thickness of the lower interlayer insulating film relaxes the underlying three-dimensional structure (step, curvature, etc.) that is not easily embedded. I just need it. The surface of the lower interlayer insulating film does not necessarily have to come above the wiring surface.

  FIG. 6A shows a modification of the above embodiment. The thickness of the PSG lower interlayer insulating film 41 deposited by HDP-CVD is made smaller than the height of the gate electrode G. The deposited lower interlayer insulating film has irregularities on the surface, and the concave portions are lower than the surface (top surface) of the gate electrode. Although the HDP-PSG film has good embedding characteristics, the film thickness uniformity is not guaranteed. By limiting the thickness of the lower interlayer insulating film 41 of HDP-PSG, the flatness of the film thickness distribution of the entire laminated interlayer insulating film 40 can be more stably ensured while relaxing the underlying three-dimensional structure. Be expected.

  FIG. 6B shows another modification. When the wiring W such as the local interconnect is formed in the same layer as the gate wiring G, there is a possibility that the height of the lower interlayer insulating film 41 on the wiring W is somewhat higher than the other regions. In such a place, a part of the lower interlayer insulating film 41 may be exposed by the first step CMP. Even if the lower interlayer insulating film is exposed by CMP in the first step, it does not matter as long as no particular problem occurs.

  In the above embodiment, the lower interlayer insulating film is formed of an HDP-PSG film, but may be formed of an HDP-USG film. An insulating film with good embedding characteristics is formed using HDP-CVD, and a polishing oxide film such as a TEOS oxide film is formed thereon using PE-CVD. By limiting the film formation by HDP-CVD and performing the film formation by PE-CVD with good flatness thereon, a laminated insulating film with good flatness will be obtained. If only the film thickness uniformity over the entire wafer is targeted, the material of the upper interlayer insulating film is not limited to the TEOS oxide film. The film forming method is not limited to PE-CVD. Any film may be used as long as the film thickness is uniform. Further, the wiring is not limited to being formed from the same layer as the gate electrode.

  7A and 7B show an example including the case where the wiring is other than the gate wiring.

  7A and 7B show a method for manufacturing a dynamic random access memory (DRAM). As shown in FIG. 7A, an n-channel MOS transistor is formed in the memory cell region of the semiconductor substrate by a process similar to that shown in FIGS. The figure shows a configuration in which two n-channel MOS transistors share a central source / drain region and memory capacitors are connected to the source / drain regions on both sides. After forming the MOS transistor, an interlayer insulating film 40 is formed so as to embed the gate electrode.

  After planarizing the surface of the interlayer insulating film 40 by CMP, contact holes reaching the source / drain regions are formed by photolithography and etching, and polycrystalline silicon or the like is buried to form a conductive plug PLG1. After removing the conductive layer on the surface by CMP, a silicon oxide film is deposited to form an interlayer insulating film 50.

  A connection hole that penetrates the interlayer insulating film 50 and reaches the conductive plug PLG1 in the center of the figure is formed, a wiring layer such as an aluminum alloy is deposited by sputtering or the like, and the wiring layer is patterned by photolithography and etching. A line BL is formed.

  An HDP-PSG film 61 and a PE-TEOS film 62 are formed so as to cover the bit line BL. The interlayer insulating film 60 is formed by planarizing the surface by the same two-step CMP as described above.

  As shown in FIG. 7B, a connection hole reaching the conductive plug PLG1 on both sides through the interlayer insulating films 60 and 50 is formed, and the conductive plug PLG2 is embedded. A storage electrode SE such as polycrystalline silicon, a capacitor dielectric film CDF such as a thermal silicon oxide film, and a counter electrode OE such as a polycrystalline silicon film are formed on the conductive plug PLG2. Any known method may be used as a method of manufacturing the DRAM capacitor. The capacitor is embedded, and an HDP-PSG film 71 and a PE-TEOS film 72 are deposited to form an interlayer insulating film 70. Reflecting the underlying capacitor, the surface of the interlayer insulating film 70 has irregularities. The surface of the interlayer insulating film 70 is planarized by the same two-step CMP as described above.

  Thus, when the surface is uneven due to the wiring structure, the step, curvature, etc. are first relaxed with a silicon oxide film of HDP having excellent embedding characteristics, and then the film thickness is uniform and stable CMP is possible. A silicon oxide film by PE-CVD is deposited to form a good interlayer insulating film. By planarizing this interlayer insulating film by two-step CMP, an interlayer insulating film having a uniform thickness and a flat surface is obtained.

  Although the present invention has been described according to the embodiments, the present invention is not limited to these. For example, as the additive used for the ceria-based abrasive, polyvinyl pyrrolidone or the like may be used in addition to the ammonium polyacrylate. The film to be polished is not limited to a silicon oxide film, and may be a silicon oxynitride film or the like. A lower insulating film may be formed using HDP-CVD, which is a film formation method with good embedding characteristics, and an upper insulating film with good flatness (thickness uniformity) may be formed thereon. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.

FIG. 1A is a cross-sectional view showing the configuration of a sample formed in a preliminary experiment, and FIG. 1B is a graph showing the thickness distribution of three types of silicon oxide films measured after the silicon oxide film OX is deposited on the substrate SUB. 2A is a cross-sectional view schematically showing the structure of the polishing apparatus, FIG. 2B is a graph showing polishing rates when three types of silicon oxide films are polished with the same type of ceria slurry, and FIG. 2C is a polyacrylic acid having different concentrations. It is a graph which shows the polishing rate when a HDP-PSG film | membrane is grind | polished with the ceria slurry containing an ammonium salt. 3A to 3E are cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment. 3F and 3G are cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment, and FIG. 3H is a graph showing a thickness distribution of an interlayer insulating film after polishing. It is a graph which shows the change of the film thickness dispersion | variation with respect to ratio of the height of a lower interlayer insulation film with respect to wiring height. FIG. 5A is a cross-sectional view of a semiconductor wafer for explaining two-step polishing, and FIG. 5B is a plan view of a polishing apparatus showing a nozzle arrangement during polishing. FIG. 5C is a graph showing the number of scratches after the first step and after the second step, and FIG. 5D is a graph showing the film thickness distribution after polishing. 6A and 6B are cross-sectional views of a semiconductor wafer showing two modifications of the embodiment. 7A and 7B are cross-sectional views of a semiconductor wafer showing a method of manufacturing a DRAM according to another embodiment.

Explanation of symbols

OX silicon oxide film SUB semiconductor substrate WAF wafer STI shallow trench isolation G gate electrode SW sidewall S / D source / drain PW p-type well NW n-type well PLG conductive plug BL bit line CAP capacitor 10 silicon wafer 12 silicon oxide film 13 Silicon nitride film 17 Silicon oxide film (liner)
18 Silicon nitride film (liner)
20 Silicon oxide film (element isolation region)
40 interlayer insulating film 41 lower interlayer insulating film 42 upper interlayer insulating film 50 interlayer insulating film 60 interlayer insulating film 61 lower interlayer insulating film 62 upper interlayer insulating film 70 interlayer insulating film 71 lower interlayer insulating film 72 upper interlayer insulating film 102 polishing table 104 Polishing pad 112 Polishing head 124 Nozzle

Claims (6)

(A) forming a wiring above the semiconductor substrate;
(B) After the step (a), a step of burying the wiring and depositing a first insulating film by high density plasma (HDP) chemical vapor deposition (CVD);
(C) After step (b), depositing a second insulating film above the first insulating film by a deposition method other than HDP-CVD;
After the step (d) (c), a step of flattening the previous SL second insulating film,
Only including,
Step (d) is a first step performed using a first slurry containing cerium dioxide abrasive grains and an additive, and a second step carried out using a second slurry containing silica abrasive grains after the first step. A method of manufacturing a semiconductor device comprising: a third step performed using the first slurry and pure water after the second step . Wherein in the third step, the manufacturing method of the first scan slurry and the semiconductor device of 請 Motomeko 1 wherein the pure water you mixed on the polishing table. Wherein depositing a second insulating film, the method of deposition than HDP-CVD is plasma (PE-) The method according to claim 1 or 2, wherein the CVD. It said first insulating film, a method of manufacturing a semiconductor device according to any one of claims 1 to 3 phosphosilicate glass (PSG) film or a borophosphosilicate glass (BPSG) film. The semiconductor substrate is a silicon substrate, and before step (a),
(X) forming a trench separating the active region in the silicon substrate;
(Y) depositing an undoped silicate glass (USG) film on the silicon substrate by HDP-CVD and filling the trench with the USG film;
(Z) removing the USG film outside the trench by chemical mechanical polishing using a polishing agent containing cerium dioxide abrasive grains;
The manufacturing method of the semiconductor device of any one of Claims 1-4 containing this. In step (c), the second insulating film is formed by PE-CVD using tetraethoxysilane (TEOS) as a silicon source, and an abrasive used in the first step of step (z) and step (d) is used. 6. The method of manufacturing a semiconductor device according to claim 5 , wherein the semiconductor devices have the same composition.

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