KR20100013986A - Method for fabrication of semiconductor device - Google Patents

Method for fabrication of semiconductor device Download PDF

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Publication number
KR20100013986A
KR20100013986A KR1020080075750A KR20080075750A KR20100013986A KR 20100013986 A KR20100013986 A KR 20100013986A KR 1020080075750 A KR1020080075750 A KR 1020080075750A KR 20080075750 A KR20080075750 A KR 20080075750A KR 20100013986 A KR20100013986 A KR 20100013986A
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KR
South Korea
Prior art keywords
film
insulating film
layer
insulating
device isolation
Prior art date
Application number
KR1020080075750A
Other languages
Korean (ko)
Inventor
윤태언
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080075750A priority Critical patent/KR20100013986A/en
Publication of KR20100013986A publication Critical patent/KR20100013986A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a tunnel insulating film and a first conductive film on a semiconductor substrate, and etching the first conductive film, the tunnel insulating film, and the semiconductor substrate to form a trench for device isolation. Forming a liner film on the sidewalls and bottom of the device isolation trench, and filling the device isolation trench with a first insulating film and a second insulating film, and filling the second insulating film with the first conductive film. Forming a dielectric film along a surface, forming a second conductive film and a gate electrode film on the dielectric film, the gate electrode film, the second conductive film, the dielectric film, the first conductive film and the Performing a gate patterning process for etching the tunnel insulating film to expose the source and drain regions of the semiconductor substrate and simultaneously etching the second insulating film. It discloses a method of manufacturing a semiconductor device including the step of removing the step of exposing the first insulating film and the first insulating film to form a device isolation film made of the liner film and the second insulating film.

Description

Method for fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including an element isolation film of a semiconductor device.

In a semiconductor circuit, it is necessary to electrically separate a unit element formed on the semiconductor substrate, for example, a transistor, a diode, or a resistor. Therefore, this device isolation process is an initial step in all semiconductor manufacturing process steps, and depends on the size of the active region and the process margin of subsequent steps.

As a method for forming such device isolation, a LOCal Oxidation of Silicon (LOCOS) has been widely used. However, according to the LOCOS device isolation, as the oxygen penetrates into the side of the pad oxide film under the nitride film used as the mask for the selective oxidation of the semiconductor substrate, a bird's beak is generated at the end of the field oxide film. Since the field oxide film is extended to the active region by the length of the buzz beak by such a buzz beak, the channel length is shortened and the threshold voltage is increased, thereby causing problems such as deterioration of the electrical characteristics of the transistor. Done.

On the other hand, the trench trench isolation (STI) process is an instability factor of the process such as deterioration of the field oxide film due to the reduction of the design rule of the semiconductor device, and the reduction of the active region due to the buzz beak. It is emerging as a device separation process that can fundamentally solve the problem.

1 is a cross-sectional view of a device for explaining a method of forming a device isolation film of a semiconductor device according to the prior art.

Referring to FIG. 1, a tunnel insulating film 11 and a polysilicon film 12 for floating gate are formed on the semiconductor substrate 10, and selectively etched to expose the device isolation region of the semiconductor substrate 10. The trench 13 is formed by etching the exposed semiconductor substrate 10. The trench 13 is then filled with an insulating film to form the device isolation film 14.

Here, before forming the device isolation film 14, a series of sidewall sacrificial oxidation processes (for the purpose of removing the etching defects of the semiconductor surface by dry etching), the trench 13 sidewall reoxidation process, and the like are performed. Omitted for the sake of simplicity.

Recently, in order to increase the integration of semiconductor devices, which are highly integrated, the device size is reduced to 60 nm or less. Accordingly, the semiconductor memory using the SA-STI (Self Aligned Shallow Trench Isolation) process can no longer secure a gap fill margin using an HDP oxide film. Therefore, the gap fill margin is secured using a PSZ film.

However, when the device isolation film is formed using the PSZ film, the volume of the PSZ film shrinks due to heat generated by a subsequent process, and a tensile stress acts on the adjacent tunnel insulating film, so that the retention characteristics of the device are repeated. Degrades.

According to an aspect of the present invention, a device isolation layer is formed by filling a portion of a device isolation trench with a PSZ layer, and then exposed to the upper end of the device isolation layer during the gate pattern etching process to expose the PSZ layer, and then removing the device isolation layer. The present invention provides a method for manufacturing a semiconductor device that can form voids to prevent the tunnel insulating film from being stressed by the PSZ film, thereby improving the retention characteristics of the device.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a tunnel insulating film and a conductive film on a semiconductor substrate, and forming a trench for device isolation by etching the conductive film, the tunnel insulating film and the semiconductor substrate. And forming a liner film on the sidewalls and the bottom of the device isolation trench, stacking and filling the device isolation trench with a first insulating film and a second insulating film, and etching the conductive film and the tunnel insulating film. Simultaneously etching the second insulating film to expose the first insulating film, and removing the first insulating film to fill the device isolation trench with the liner film and the second insulating film. Forming an empty void.

After the conductive film is formed, the method may further include forming a hard mask film.

Before forming the liner layer, the method may further include forming a wall oxide layer on the sidewalls and the bottom of the trench for isolation.

The method of claim 1, wherein the filling of the device isolation trench by laminating the first insulating film and the second insulating film comprises filling the device isolation trench including the liner film with the first insulating film. Etching an upper portion of the first insulating film, and filling the trench including the liner film and the first insulating film with the second insulating film.

In the etching of the upper portion of the first insulating layer, the upper height of the first insulating layer is higher than the upper surface height of the tunnel insulating layer.

The method of claim 1, further comprising: forming a dielectric film and a gate film on the semiconductor substrate including the conductive film after filling the device isolation trench by laminating and filling the first insulating film and the second insulating film.

The removing of the first insulating layer may be performed by a wet process to remove the first insulating layer surrounded by the second insulating layer and the liner layer, thereby forming a device isolation layer having an empty internal space.

After forming the first insulating film, a heat treatment process is further performed. The first insulating film is formed of a PSZ film. The liner film and the second insulating film are formed of an HDP oxide film.

According to an embodiment of the present invention, after forming a device isolation film by filling a portion of the device isolation trench with a PSZ film, the PSZ film is exposed by etching to the upper end of the device isolation film during the gate pattern etching process, and then removing the PSZ film. A void may be formed in the device isolation layer to prevent the tunnel insulation layer from being stressed by the PSZ film, thereby improving retention characteristics of the device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A through 2F are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a tunnel insulating layer 101, a charge storage layer 102, and a hard mask layer 103 are formed on a semiconductor substrate 100 including a cell region and a peripheral circuit region. The tunnel insulating film 101 is preferably formed of an oxide film. The charge storage layer 102 is preferably formed of a polysilicon film or a nitride film capable of trapping charge. When the charge storage layer 102 is formed of a polysilicon film, it is preferable to form a double film including an amorphous polysilicon film containing no impurities and a polysilicon film containing impurities. The hard mask film 103 is preferably formed of a nitride film. A buffer oxide film (not shown) may be further formed on the hard mask film 103.

Referring to FIG. 2B, the hard mask layer 103 is patterned by performing an etching process. Thereafter, an etching process using the patterned hard mast layer 103 as an etching mask is performed to etch the charge storage layer 102 and the tunnel insulating layer 101 to expose the device isolation region of the semiconductor substrate 100. The exposed semiconductor substrate 100 is etched to form an isolation trench 104.

Referring to FIG. 2C, a wall oxide film 105 is formed on the entire structure including the trench 104 for device isolation. The wall oxide layer 105 alleviates the etching damage that occurs during the etching process of the device isolation trench 104. Thereafter, the liner film 106 is formed on the entire structure including the wall oxide film 105. The liner film 106 is preferably formed of an HDP oxide film.

Thereafter, the first insulating film 107 is formed over the entire structure including the liner film 106 to fill the trench 104 for device isolation. The first insulating film 107 is preferably formed of a spin on dielectric (SOD) oxide film, for example, a PSZ film.

Thereafter, a heat treatment step is performed to cure the first insulating film 107 and to discharge impurities in the first insulating film 107.

Referring to FIG. 2D, a chemical mechanical polishing (CMP) process is performed to expose the hard mask film.

Thereafter, after the hard mask film is removed, an etching process is performed to etch the upper ends of the wall oxide film 105, the liner film 106, and the first insulating film 107. In this case, the height of the upper end portion of the first insulating layer 107 may be higher than that of the tunnel insulating layer 101.

Referring to FIG. 2E, the second insulating film 108 is formed on the entire structure including the first insulating film 107 and the etching process is performed to form the second insulating film 108 in the space between the charge storage layers 102. It is formed so as to remain only on the device isolation region, that is, the upper portion of the wall oxide film 105, the liner film 106, and the first insulating film 107. The second insulating film 108 is preferably formed of an HDP oxide film.

Thereafter, the dielectric film 109 is formed over the entire structure including the second insulating film 108. The dielectric film 109 is preferably formed in an ONO structure in which the first oxide film 109a, the nitride film 109b, and the second oxide film 109c are stacked.

Thereafter, the control gate conductive film 110 and the metal gate film 111 are sequentially stacked on the entire structure including the dielectric film 109. The control gate conductive film 110 may be formed of a polysilicon film. The metal gate layer 111 may be formed of a tungsten silicide, cobalt silicide, or nickel silicide layer.

Referring to FIG. 1F, a metal gate layer 111, a control gate conductive layer 110, and a dielectric layer 109 are formed to perform an etching process for forming a gate pattern to expose source and drain regions of the semiconductor substrate 100. , The charge storage layer 102 and the tunnel insulating film 101 are etched. At this time, during the etching process, the second insulating layer 108 is etched to expose the first insulating layer. Thereafter, the exposed first insulating layer is removed by a wet etching process to form an empty space A. As a result, voids A are formed in the device isolation layers 105, 106, and 108.

This prevents the first insulating film from shrinking by the heat of the subsequent process to prevent the tensile force from being applied to the tunnel insulating film, thereby improving the retention characteristics of the device.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view of a device for explaining a method of forming a device isolation film of a semiconductor device according to the prior art.

2A through 2F are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 tunnel insulating film

102: charge storage layer 103: hard mask film

104: trench for element isolation 105: wall oxide film

106: liner film 107: first insulating film

108: second insulating film 109: dielectric film

110: conductive film for control gate 111: gate electrode film

Claims (12)

Forming a tunnel insulating film and a conductive film on the semiconductor substrate; Etching the conductive layer, the tunnel insulating layer, and the semiconductor substrate to form a trench for device isolation; Forming a liner film on sidewalls and bottoms of the device isolation trenches, and filling the device isolation trenches with a first insulating film and a second insulating film; Performing a gate patterning process of etching the conductive film and the tunnel insulating film, and simultaneously etching the second insulating film to expose the first insulating film; And And removing the first insulating layer to form voids in the device isolation trench, wherein the inside of the device isolation trench is filled with the liner layer and the second insulating layer, and wherein the first insulating layer is removed. The method of claim 1, And forming a hard mask film after the conductive film is formed. The method of claim 1, And forming a wall oxide film on the sidewalls and bottom of the trench for isolation of the device before forming the liner film. The method of claim 1, wherein the filling of the isolation layer trench with a first insulating film and a second insulating film is performed. Filling the device isolation trench including the liner layer with the first insulating layer; Etching an upper portion of the liner layer and the first insulating layer; And And filling the trench including the liner layer and the first insulating layer with the second insulating layer. The method of claim 4, wherein The etching of the upper portion of the first insulating layer may further comprise a semiconductor device having a higher height than an upper surface height of the tunnel insulating layer. The method of claim 1, wherein after filling the device isolation trench with a first insulating film and a second insulating film, And forming a dielectric film and a gate film on the semiconductor substrate including the conductive film. The method of claim 1, Removing the first insulating film And performing a wet process to remove the first insulating film surrounded by the second insulating film and the liner film to form a device isolation film having an empty internal space. The method of claim 1, After forming the first insulating film, The method of manufacturing a semiconductor device further comprising the step of performing a heat treatment process. The method of claim 1, And the first insulating film is formed of a PSZ film. The method of claim 1, The liner film and the second insulating film are formed of an HDP oxide film. Forming a tunnel insulating film and a first conductive film on the semiconductor substrate; Etching the first conductive layer, the tunnel insulating layer, and the semiconductor substrate to form a device isolation trench; Forming a liner film on sidewalls and bottoms of the device isolation trenches, and filling the device isolation trenches with a first insulating film and a second insulating film; Forming a dielectric film along surfaces of the second insulating film and the first conductive film; Forming a second conductive film and a gate electrode film on the dielectric film; Performing a gate patterning process to etch the gate electrode film, the second conductive film, the dielectric film, the first conductive film, and the tunnel insulating film to expose the source and drain regions of the semiconductor substrate, Etching to expose the first insulating film; And And removing the first insulating film to form an isolation layer formed of the liner film and the second insulating film. The method of claim 11, The device isolation layer is a semiconductor device manufacturing method comprising a void in the interior space.
KR1020080075750A 2008-08-01 2008-08-01 Method for fabrication of semiconductor device KR20100013986A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9607841B2 (en) 2013-10-17 2017-03-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9607841B2 (en) 2013-10-17 2017-03-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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