KR20100008165A

KR20100008165A - Method for fabrication of semiconductor device

Info

Publication number: KR20100008165A
Application number: KR1020080068598A
Authority: KR
Inventors: 유종현
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-07-15
Filing date: 2008-07-15
Publication date: 2010-01-25

Abstract

The present invention relates to a method of manufacturing a semiconductor device, comprising the steps of: forming a tunnel insulating film and a conductive film on a semiconductor substrate, etching the conductive film, the tunnel insulating film and the semiconductor substrate to form a device isolation trench; Filling the device isolation trench with a first insulating film, etching the upper end of the first insulating film at the same time, and etching the upper end of the conductive film roundly, and forming a second insulating film on the first insulating film Disclosed is a method of manufacturing a semiconductor device comprising forming a.

Description

Method for fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for forming an element isolation film of a semiconductor device.

In a semiconductor circuit, it is necessary to electrically separate a unit element formed on the semiconductor substrate, for example, a transistor, a diode, or a resistor. Therefore, this device isolation process is an initial step in all semiconductor manufacturing process steps, and depends on the size of the active region and the process margin of subsequent steps.

As a method for forming such device isolation, a LOCal Oxidation of Silicon (LOCOS) has been widely used. However, according to the LOCOS device isolation, as the oxygen penetrates into the side of the pad oxide film under the nitride film used as the mask for the selective oxidation of the semiconductor substrate, a bird's beak is generated at the end of the field oxide film. Since the field oxide film is extended to the active region by the length of the buzz beak by such a buzz beak, the channel length is shortened and the threshold voltage is increased, thereby causing problems such as deterioration of the electrical characteristics of the transistor. Done.

On the other hand, the trench trench isolation (STI) process is an instability factor of the process such as deterioration of the field oxide film due to the reduction of the design rule of the semiconductor device, and the reduction of the active region due to the buzz beak. It is emerging as a device separation process that can fundamentally solve the problem.

1 is a cross-sectional view of a device for explaining a method of forming a device isolation film of a semiconductor device according to the prior art.

Referring to FIG. 1, a tunnel insulating film 11 and a polysilicon film 12 for floating gate are formed on the semiconductor substrate 10, and selectively etched to expose the device isolation region of the semiconductor substrate 10. The trench 13 is formed by etching the exposed semiconductor substrate 10. The trench 13 is then filled with an insulating film to form the device isolation film 14.

Here, before forming the device isolation film 14, a series of sidewall sacrificial oxidation processes (for the purpose of removing the etching defects of the semiconductor surface by dry etching), the trench 13 sidewall reoxidation process, and the like are performed. Omitted for the sake of simplicity.

Recently, in order to increase the integration of semiconductor devices, which are highly integrated, the device size is reduced to 60 nm or less. Accordingly, the semiconductor memory using the SA-STI (Self Aligned Shallow Trench Isolation) process can no longer secure a gap fill margin using an HDP oxide film. Therefore, a gap fill margin is secured by using a spin on dielectric (SOD) oxide film (for example, a PSZ film).

The technical problem to be achieved by the present invention is to round-etch the upper portion of the conductive film for the floating gate during the device isolation film forming process and to etch the upper end of the device isolation film, thereby suppressing the occurrence of overhang during the subsequent insulation film deposition process, thereby preventing void generation in the device isolation film. It is providing the manufacturing method of the semiconductor element which can be suppressed.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a tunnel insulating film and a conductive film on a semiconductor substrate, and forming a trench for device isolation by etching the conductive film, the tunnel insulating film and the semiconductor substrate. And filling the device isolation trench with a first insulating film, etching the upper end of the first insulating film and roundly etching the upper end of the conductive film, and forming a second insulating film on the first insulating film. Forming an isolation layer.

The method may further include forming a hard mask film on the conductive film.

After the filling of the trench with the first insulating layer, the method may further include etching the upper end portion of the first insulating layer while removing the hard mask layer by performing an etching process.

The etching process is performed using a dry etching process. The etching process is carried out using gas chemicals of the CxFx or CHxFx series. The etching process is performed so that the flow rate of the gas chemical is 0.1sccm to 1000sccm.

After forming the device isolation trench, and further comprising forming a wall oxide film and a liner film on the entire structure including the device isolation trench.

After forming the first insulating film, a heat treatment process is further performed.

Etching the upper end of the conductive film is performed by using a sputtering etching method. Etching the upper end of the conductive film is performed by using a single or mixed gas of the CxFx or CHxFx series. The step of etching the upper end of the conductive film is carried out so that the flow rate of the gas chemical is 0.1sccm to 1000sccm. The etching of the upper end of the conductive film is performed so that the etching amount of the conductive film is 1 to 100 kPa. The etching of the upper end of the conductive layer is performed in an in situ manner with the etching process.

The hard mask film is formed of a nitride film and an oxide film. The conductive film is formed of a polysilicon film. The first insulating film is formed of an SOD film. The second insulating film is formed of an HDP film, a HARP film, or a PSZ film.

According to an embodiment of the present invention, by roundly etching the upper portion of the conductive film for the floating gate during the device isolation film forming process and etching the upper end of the device isolation film, the occurrence of voids in the device isolation film is suppressed by suppressing the occurrence of overhang in the subsequent insulating film deposition process. Can be suppressed.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A through 2F are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a tunnel insulating layer 101, a charge storage layer 102, and a hard mask layer 103 are formed on a semiconductor substrate 100 including a cell region and a peripheral circuit region. The tunnel insulating film 101 is preferably formed of an oxide film. The charge storage layer 102 is preferably formed of a polysilicon film or a nitride film capable of trapping charge. When the charge storage layer 102 is formed of a polysilicon film, it is preferable to form a double film made of an amorphous polysilicon film containing no impurities and a polysilicon film containing impurities. The hard mask film 103 is preferably formed of a nitride film. A buffer oxide film (not shown) may be further formed on the hard mask film 103.

Referring to FIG. 2B, the hard mask layer 103 is patterned by performing an etching process. Thereafter, an etching process using the patterned hard mast layer 103 as an etching mask is performed to etch the charge storage layer 102 and the tunnel insulating layer 101 to expose the device isolation region of the semiconductor substrate 100. The exposed semiconductor substrate 100 is etched to form an isolation trench 104.

Thereafter, a wall oxide film 105 is formed over the entire structure including the trench 104 for device isolation. The wall oxide layer 105 alleviates the etching damage that occurs during the etching process of the device isolation trench 104. Thereafter, the liner film 106 is formed on the entire structure including the wall oxide film 105. The liner film 106 is preferably formed of an oxide film.

Referring to FIG. 2C, the first insulating layer 107 is formed on the entire structure including the liner layer 106 to fill the trench 104 for device isolation. The first insulating film 107 is preferably formed of a spin on dielectric (SOD) oxide film, for example, a PSZ film.

Thereafter, a heat treatment step is performed to cure the first insulating film 107 and to discharge impurities in the first insulating film 107.

After that, a chemical mechanical polishing (CMP) process is performed to expose the hard mask film 103.

Referring to FIG. 2D, an etching process is performed to remove the hard mask layer and to etch the upper end portions of the wall oxide layer 105, the liner layer 106, and the first insulating layer 107.

The etching process is preferably performed using a dry etching process, and it is preferable to perform the etching process so that the etching ratio of the nitride film and the oxide film is 1: 1. The etching process is preferably performed using gas chemicals of the CxFx or CHxFx series. The etching process is preferably performed so that the flow rate of the gas chemical is 0.1sccm to 1000sccm.

Referring to FIG. 2E, the upper end portion of the exposed charge storage layer 102 is etched by etching the upper end portions of the wall oxide layer 105, the liner layer 106, and the first insulating layer 107 by performing an etching process. Form to be round. As a result, an overhang may be prevented in a subsequent insulating gap fill process to prevent voids from occurring in the device isolation layer.

The etching process is preferably carried out using a sputtering etching method. The etching process is preferably performed by using a single or mixed gas of the CxFx or CHxFx series. The etching process is preferably performed so that the flow rate of the gas chemical is 0.1sccm to 1000sccm. The etching process is preferably performed so that the etching amount of the charge storage layer 102 is 1 to 100 kPa. The etching process is preferably performed in-situ with the above-described hard mask film removing process.

Referring to FIG. 2F, device isolation layers 105, 106, 107, and 108 are formed by forming a second insulating layer 108 on upper portions of the wall oxide layer 105, the liner layer 106, and the first insulating layer 107. . The second insulating film 108 is preferably formed of an HDP oxide film, a HARP film, or a PSZ film. In the process of forming the second insulating layer 108, the device isolation layers 105, 106, 107, and 108 may be formed without the overhang of the second insulating layer 108 by the charge storage layer 102 having the upper end rounded.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

100 semiconductor substrate 101 tunnel insulating film

102: charge storage layer 103: hard mask film

104: trench for element isolation 105: wall oxide film

106: liner film 107: first insulating film

108: second insulating film

Claims

Forming a tunnel insulating film and a conductive film on the semiconductor substrate;

Etching the conductive layer, the tunnel insulating layer, and the semiconductor substrate to form a trench for device isolation;

Filling the device isolation trench with a first insulating film;

Etching the upper end of the first insulating layer and simultaneously etching the upper end of the conductive layer; And

And forming a device isolation layer by forming a second insulation film on the first insulation film.

The method of claim 1,

And forming a hard mask film on the conductive film.

The method of claim 2,

After filling the device isolation trench with the first insulating film,

Performing an etching process to remove the hard mask layer and simultaneously etching an upper end portion of the first insulating layer.

The method of claim 3, wherein

The etching process is a manufacturing method of a semiconductor device performed using a dry etching process.

The method of claim 3, wherein

The etching process is a method of manufacturing a semiconductor device using a gas chemical of the CxFx or CHxFx series.

The method of claim 3, wherein

The etching process is a method of manufacturing a semiconductor device to be carried out so that the flow rate of the gas chemical is 0.1sccm to 1000sccm.

The method of claim 1,

After forming the device isolation trench,

And forming a wall oxide film and a liner film on the entire structure including the device isolation trench.

The method of claim 1,

After forming the first insulating film,

The method of manufacturing a semiconductor device further comprising the step of performing a heat treatment process.

The method of claim 1,

The etching of the upper end of the conductive film is performed using a sputter etching method.

The method of claim 1,

Etching the upper end portion of the conductive film is a method of manufacturing a semiconductor device by using a single or a mixture of CxFx or CHxFx-based gas chemical.

The method of claim 1,

The etching of the upper end of the conductive film is carried out so that the flow rate of the gas chemical is 0.1sccm to 1000sccm.

The method of claim 1,

Etching the upper end of the conductive film is performed so that the etching amount of the conductive film is 1 to 100 kPa.

The method of claim 3, wherein

The etching of the upper end of the conductive film is performed in the in-situ method with the etching process.

The method of claim 2,

And the hard mask film is formed of a nitride film and an oxide film.

The method of claim 1,

The conductive film is a semiconductor device manufacturing method of forming a polysilicon film.

The method of claim 1,

The first insulating film is a semiconductor device manufacturing method of forming a SOD film.

The method of claim 1,

And the second insulating film is formed of an HDP film, a HARP film, or a PSZ film.