KR20080015589A - Method for fabricating flash memory devices - Google Patents

Abstract

A method of fabricating a flash memory device is provided to increase a coupling ratio of a floating gate and a control gate by forming the floating gate in a U-shape. A semiconductor substrate(10) is prepared, the substrate having an isolation region defining an active region, an isolation film(20) burying a trench(12) of the isolation region and protruding upwardly from the active region and a tunnel oxide layer(30) on the active region. A conductive layer is formed to cover the isolation film and the tunnel oxide layer, thereby removing a step height. The conductive layer is patterned to form a U-shaped floating gate(40). The trench is formed by forming and patterning a pad oxide layer and a pad nitride layer and then etching the substrate using the layers as a mask.

Description

Method for fabricating flash memory devices {Method for fabricating flash memory devices}

1 is a layout diagram of a flash memory device manufactured by a method of manufacturing a flash memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

3 is a flowchart illustrating a process of a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention in order.

4 through 9 are cross-sectional views of intermediate structures in which a method of manufacturing a flash memory device according to an embodiment of the present invention is arranged according to a process sequence.

<Explanation of symbols for the main parts of the drawings>

10: semiconductor substrate 20: device isolation film

30 tunnel oxide film 40 floating gate

50: interlayer dielectric film 60: control gate

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a flash memory device.

Flash memory devices generally have a multilayer gate structure having floating gates formed on a semiconductor substrate. The multilayer gate structure typically includes one or more tunnel oxide or interlayer dielectric layers and control gates formed on or around the floating gates.

Flash memory devices are attempting to scale down as the demand for large memory increases. When the flash memory device is scaled down, a coupling ratio, which is a ratio of the voltage coupled to the floating gate by the voltage applied to the control gate during the write operation, may be reduced, thereby reducing the write and erase efficiency.

Accordingly, there is a demand for development of a flash memory device that does not reduce the coupling ratio while scaling down.

An object of the present invention is to provide a method of manufacturing a flash memory device that does not reduce the coupling ratio while scaling down.

A method of manufacturing a flash memory device according to an embodiment of the present invention for achieving the above technical problem is a device isolation region defining an active region, a device isolation layer buried in the trench of the device isolation region and protruded upwards, and the active Providing a semiconductor substrate having a tunnel oxide film in a region, forming a conductive film covering the device isolation layer and the tunnel oxide film to remove a step, and patterning the conductive film to form a U-shaped floating gate; do.

The trench of the device isolation region may be formed by sequentially forming a pad oxide layer and a pad nitride layer on the semiconductor substrate, patterning the pad oxide layer and the pad nitride layer, and etching the semiconductor substrate with an etching mask. In this case, the pad nitride layer may be, for example, about 2000 to 3000 Pa.

The device isolation layer may be formed by stacking an insulating material on the device isolation region and the pad nitride layer, and planarizing the layer of the insulating material using the pad nitride layer as an etch stop layer. In this case, the planarization may use a chemical mechanical polishing method.

In addition, the protruding upper portion of the device isolation layer may have an inclined sidewall.

The conductive layer may be formed by stacking a conductive material on the device isolation layer and the tunnel oxide layer and by planarizing a layer made of the conductive material. In this case, the planarization may use a chemical mechanical polishing method.

The conductive layer may have a first thickness on the device isolation layer and a second thickness thicker than the first thickness on the tunnel oxide layer.

The floating gate may be formed by forming a photoresist layer on the conductive layer to expose at least a portion of the conductive layer overlapping the active region and the device isolation region, and etching the photoresist layer with an etch mask until the device isolation layer is exposed. .

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided for the purpose of clarity, and the invention is defined only by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures and well known techniques are not described in detail in order to avoid obscuring the present invention. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on", "top" or "on" another layer or substrate, it may be formed directly on the other layer or substrate, with another layer interposed therebetween.

Below. A flash memory device manufactured by a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a layout diagram of a flash memory device manufactured by a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

1 and 2, an isolation region defining an active region is positioned in the semiconductor substrate 10, and an isolation layer 20 is positioned in the trench 12 of the isolation region. In this case, the device isolation layer 20 protrudes above the semiconductor substrate 10 while filling the trench 12 in the device isolation region. In addition, the protruding upper portion of the device isolation layer 20 has an inclined sidewall. In this case, a stringer capable of short-circuiting the adjacent floating gate 40 to be described later is hardly formed. An oxide layer 14 may be further included between the trench 12 and the device isolation layer 20 in the device isolation region.

The control gate 60 crosses the upper portion of the device isolation layer 20. In addition, a floating gate 40 is interposed between the active region of the semiconductor substrate 10 and the control gate 60, and an interlayer dielectric layer 50 is interposed between the control gate 60 and the floating gate 40, and the control is performed. A tunnel insulating film 30 is interposed between the gate 60 and the semiconductor substrate 10. The tunnel insulating layer 30 may be present only under the control gate 60, or may be present on the entire active region of the semiconductor substrate 10.

The floating gate 40 has a conformal shape on the device isolation layer 20 and the semiconductor substrate 10. That is, it has a U-shaped shape along the step formed between the device isolation layer 20 and the semiconductor substrate 10. Therefore, since the area of the interlayer dielectric film 50 per cell transistor is increased, not only can a high coupling ratio be obtained, but also the parasitic capacitance between adjacent floating gates 40 is low, so that the threshold voltage variation of the cell transistor can be reduced. .

Subsequently, a method of manufacturing a flash memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 to 9. 3 is a process flowchart illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention, and FIGS. 4 to 9 are process steps of a method of manufacturing a flash memory device according to an embodiment of the present invention. Cross-sectional views of intermediate structures listed according to.

First, as shown in FIG. 3, a semiconductor substrate having an element isolation region, an element isolation film, and a tunnel oxide film is provided (S1).

In more detail, as illustrated in FIG. 4, the pad oxide film 71, the pad nitride film 73, and the photosensitive film 75 are sequentially formed on the semiconductor substrate 10 made of silicon or the like.

In this case, the pad oxide film 71 may be subjected to a dry or wet oxidation method, for example, at a temperature of about 750 to 900 ° C. for crystal defects or surface treatment of the upper surface of the semiconductor substrate 10. It may be formed in a thickness. In addition, the pad nitride film 73 is formed relatively thick, for example, by a thickness of, for example, about 2000 to 3000 Pa using a Low Pressuer Chemical Vapor Deposition Method (LPCVD). Although not shown, an anti-reflection film may be further formed between the pad nitride film 73 and the photosensitive film 75.

In addition, the semiconductor substrate 10 may be cleaned through a pretreatment cleaning process before forming the pad oxide layer 71. For example, in the cleaning process, the semiconductor substrate 10 is immersed in a container filled with diluted HF (DHF) or Buffer Oxide Etchant (BOE), washed with deionized water, and then removed from the semiconductor substrate 10. To this end, the semiconductor substrate 10 is immersed in a solution filled with NH ₄ OH / H ₂ O ₂ / H ₂ O solution, washed with deionized water, and then dried.

Next, as shown in FIG. 5, the photoresist film 75 (FIG. 4) is patterned to expose a predetermined region of the pad nitride film 73 (FIG. 4), and the pad nitride film (FIG. 4) is used as the etch mask. 73) and the pad oxide film (71 in FIG. 4) are patterned in order to form a hard mask HM including the patterned pad nitride film 74 and the pad oxide film 72. FIG. The trench 12 is formed in the semiconductor substrate 10 using the hard mask HM as an etching mask. The semiconductor substrate 10 is divided into an active region and an isolation region by the trench 12.

Next, as shown in FIG. 6, the photosensitive film 76 of FIG. 5 is removed and a thermal oxidation process is performed on the semiconductor substrate 10 on which the trench 12 is formed to form an oxide film 14 on the inner wall of the trench 12. . The oxide layer 14 is used to compensate for the silicon damage caused by the high energy ion bombardment during the trench 12 etching process, for example, on the inner surface of the trench 12, ie, on the bottom and sidewalls, for example, about 20 to 500 kV. It may be formed to a thickness of. At this time, the edge of the pad oxide film 72 is grown thick to form a buzz beak.

Next, an insulating material filling the gap region between the hard mask and the inside of the trench 12 is laminated. The insulating material filling the trench 12 in the device isolation region may be formed of a material having excellent embedding characteristics such as a high density plasma oxide film or a PEOX film. In this case, the insulating material may be stacked by, for example, a gap filling process so that voids do not occur in the trench 12, and the thickness thereof may be, for example, about 5000 to 10000 mm 3.

Subsequently, the device isolation film 20 is formed by planarizing a layer made of an insulating material by performing a planarization process using the pad nitride film 74 as an etch stop layer on the entire structure. In this case, a chemical mechanical polishing method (CMP) may be used as a method of planarizing the insulating film.

Next, as shown in FIG. 7, the pad nitride film 74 of FIG. 6 is removed. The pad nitride film 74 may be removed by, for example, a wet etching method using a phosphoric acid solution. After the pad nitride film 74 is removed, the step between the active region of the semiconductor substrate 10 and the device isolation film 20 is, for example, about 1500 to 2500 kPa.

Subsequently, a well ion implantation process is performed to form a well region (not shown) in the active region of the semiconductor substrate 10, and a threshold voltage ion implantation process is performed to form an impurity region (not shown).

Next, after the pad oxide film 72 of FIG. 6 is removed by a cleaning process, an inclined sidewall is formed on the edge of the device isolation film 20 protruding to the upper surface of the semiconductor substrate 10. In this case, the device isolation layer 20 may adjust the height of the protruding upper portion by repeatedly performing wet etching and dry etching. When the protruding upper portion of the device isolation layer 20 has an inclined sidewall, the stringer does not remain on the substrate adjacent to the protruding upper portion.

Next, the tunnel insulating film 30 is formed in the portion where the pad oxide film 72 is removed. The tunnel insulating film 30 may be formed of, for example, a silicon oxide film or a silicon oxynitride film, or may be formed of a stacked film. While the tunnel insulating layer 30 is formed, the density of oxygen atoms or nitrogen atoms in contact with the semiconductor substrate 10 adjacent to the element isolation film 20 protruding by the 3D effect is lowered. This is because the protruding device isolation layer 20 surrounds the edge of the semiconductor substrate 10, thereby blocking access paths of oxygen atoms and nitrogen atoms. As a result, the tunnel insulating layer 30 may have a thickness of an edge adjacent to the device isolation layer 20 to be thinner than the thickness of the center spaced apart from the device isolation layer 20.

Next, a conductive film is formed to planarize the level difference of the semiconductor substrate (S2 in FIG. 3). That is, a conductive film is formed to cover the device isolation film and the tunnel oxide film on the semiconductor substrate to remove the step.

First, as shown in FIG. 8, a conductive material for the floating gate 40 is laminated on the entire structure. The conductive material is deposited using, for example, low pressure chemical vapor deposition (LPCVD) at a temperature of about 580 to 620 ° C. and a low pressure of about 0.1 to 3 Torr in a SiH ₄ or Si ₂ H ₆ and PH ₃ gas atmosphere. Can be. The conductive material conformally covers the tunnel insulating film 30 and the protruding device isolation film 20. In addition, impurities may be implanted into the layer made of a conductive material at a doping level of about 1.5 × 10 ²⁰ to 3.0 × 10 ²⁰ atoms / cc, for example.

Next, the upper layer is flattened using, for example, chemical mechanical polishing (CMP), and the conductive layer 35 is formed to flatten the step on the semiconductor substrate 10. The conductive film 35 flattened by the chemical mechanical polishing method is, for example, about 1500 to 2500 kPa thicker than a portion overlapping the active region of the semiconductor substrate 10 with the device isolation layer 20.

Subsequently, the conductive film is patterned to form a U-shaped floating gate (S3 in FIG. 3).

In more detail, a photosensitive film is formed on the planarized conductive film (35 in FIG. 8) as shown in FIG. 9.

Next, the photosensitive film is patterned to expose at least a portion of the conductive film (35 in FIG. 8) overlapping the element isolation region and the conductive film (35 in FIG. 8) overlapping the active region. Using the patterned photosensitive film 78 as an etch mask, the conductive film (35 in FIG. 8) is etched to form the floating gate 40 until the device isolation film 20 positioned in the device isolation region is exposed. The floating gate 40 may be formed in a groove, for example, U-shaped, to increase the coupling ratio with the control gate 60 formed by a subsequent process by securing a maximum surface area.

Next, as shown in FIG. 2, an interlayer dielectric film 50 having an oxide / nitride / oxide (ONO) structure is formed on the entire structure. At this time, the oxide film forming the lower and upper portions of the interlayer dielectric film 50 may be, for example, a source of DCS (SiH ₂ Cl ₂ ) and N ₂ O gas having excellent partial pressure resistance and TDDB (Time Dependent Dielectric Break down) characteristics. For example, it may be formed to a thickness of about 35 to 60 mm 3 using HTO. At this time, the oxide film of the interlayer dielectric film 50 is loaded at a temperature of about 600 to 700 ° C., and then is subjected to low pressure chemical vapor deposition (LPCVD) to raise the temperature to about 810 to 850 ° C. under a low pressure of about 0.1 to 3 Torr. It can be formed as. In addition, the nitride film of the interlayer dielectric film 50 may be formed to, for example, about 50 to 65 kW thick using NH ₃ and DCS gas as the reaction gas. In this case, the nitride film of the interlayer dielectric film 50 may be formed, for example, by low pressure chemical vapor deposition (LPCVD) at a temperature of about 650 to 800 ° C. and a low pressure of about 1 to 3 Torr.

Subsequently, a heat treatment process may be performed to improve the quality of the interlayer dielectric film 50 and to strengthen the interface of the layers formed on the semiconductor substrate 10. At this time, the heat treatment process is performed by the wet oxidation method, for example, at a temperature of about 750 to 800 ℃. Here, the interlayer dielectric film 50 forming process and the heat treatment process are formed to a thickness corresponding to the device characteristics, and is performed with almost no delay time between processes to prevent natural oxide film or impurity contamination between the layers.

Next, a conductive film for the control gate 60 is formed on the entire structure. Subsequently, an antireflection film (not shown) is formed on the entire structure using, for example, SiOxNy or Si ₃ N ₄ , and then the antireflection film, the conductive film, and the interlayer dielectric film 50 are sequentially etched using a gate mask. The control gate 60 is formed.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the terms and expressions used herein are used for descriptive purposes only and do not have any limitation, and the use of such terms and expressions is illustrated. It is not intended to exclude equivalents of the described components or portions thereof, and various modifications are of course possible within the scope of the claimed invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, the method of manufacturing a flash memory device according to the embodiment of the present invention increases the coupling ratio between the floating gate and the control gate by making the floating gate U-shaped, while scaling down the flash memory device including the same. It is possible to provide a highly integrated flash memory device having excellent characteristics.

Claims (10)

Providing a semiconductor substrate having a device isolation region defining an active region, a device isolation layer filling a trench in the device isolation region and protruding upward, and a tunnel oxide film on the active region; Forming a conductive film covering the device isolation layer and the tunnel oxide film to remove a step; And Patterning the conductive layer to form a U-shaped floating gate. The method of claim 1, The trench of the device isolation region is formed by sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate, patterning the pad oxide film and the pad nitride film, and etching the semiconductor substrate with an etching mask. . The method of claim 2, The pad nitride film is a manufacturing method of a flash memory device of 2000 to 3000Å. The method according to claim 1 or 2, The device isolation layer is formed by stacking an insulating material on the device isolation region and the pad nitride layer, and planarizing the layer of the insulating material using the pad nitride layer as an etch stop layer. The method of claim 4, wherein The planarization method of manufacturing a flash memory device using a chemical mechanical polishing method. The method of claim 1, A protruding upper portion of the device isolation layer has a slanted sidewall. The method of claim 1, The conductive film is formed by stacking a conductive material on the device isolation film and the tunnel oxide film and by planarizing a layer made of the conductive material. The method of claim 7, wherein The planarization method of manufacturing a flash memory device using a chemical mechanical polishing method. The method of claim 7, wherein And the conductive layer has a first thickness on the device isolation layer and a second thickness thicker than the first thickness on the tunnel oxide layer. The method of claim 1, The floating gate is formed by forming a photoresist film on the conductive layer that exposes at least a portion of the conductive layer overlapping the active region and the device isolation region, and etching the photoresist layer with an etching mask until the device isolation layer is exposed. Memory device manufacturing method.

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