CN112750788B - Method for manufacturing flash memory device - Google Patents
Method for manufacturing flash memory device Download PDFInfo
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- CN112750788B CN112750788B CN202110090033.XA CN202110090033A CN112750788B CN 112750788 B CN112750788 B CN 112750788B CN 202110090033 A CN202110090033 A CN 202110090033A CN 112750788 B CN112750788 B CN 112750788B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims description 65
- 239000000463 material Substances 0.000 claims abstract description 123
- 150000004767 nitrides Chemical class 0.000 claims abstract description 119
- 238000002955 isolation Methods 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims description 22
- 239000000126 substance Substances 0.000 claims description 22
- 238000007517 polishing process Methods 0.000 claims description 18
- 238000005498 polishing Methods 0.000 claims description 17
- 238000000227 grinding Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 4
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 4
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- -1 silicon dioxide Chemical compound 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The invention provides a manufacturing method of a flash memory device, which comprises the steps of sequentially forming a floating gate material layer and a pad nitride layer on a semiconductor substrate, wherein the floating gate material layer has a first thickness, the pad nitride layer has a second thickness, and the total thickness of the pad nitride layer and the floating gate material layer is within a preset thickness, so that the floating gate material layer is ensured to have a certain thickness, the height and the sharpness of a floating gate tip formed later are improved, and the problems of excessively low height and excessively blunt sharpness of the floating gate tip caused by excessively thin floating gate material layer are avoided, thereby improving the erasure performance of the flash memory device. Furthermore, by making the total thickness of the pad nitride layer and the floating gate material layer within a preset thickness, the problem of overlarge depth-to-width ratio of the shallow trench isolation structure can be avoided when the shallow trench isolation structure is formed later.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a flash memory device.
Background
The flash memory is a nonvolatile memory, and the operation principle is that the threshold voltage of a transistor or a memory cell is changed to control the switch of a gate channel so as to achieve the aim of storing data, so that the data stored in the memory cannot disappear due to power interruption. In a flash memory device, the height and sharpness of the tip of the floating gate can affect the voltage coupled to the floating gate during programming and erasing, thereby affecting the performance of the flash memory during programming and erasing. And the sharpness of the floating gate tip has strong correlation with the erasing performance of the flash memory. Therefore, precisely controlling the tip of the floating gate has a strong practical meaning for controlling the performance of the flash memory.
In the existing method for manufacturing the flash memory device, the method generally includes: and forming a floating gate layer and a pad nitride layer on the substrate in sequence, forming a shallow trench isolation structure in the floating gate layer, the pad nitride layer and the substrate, performing a planarization process on the shallow trench isolation structure, removing the pad nitride layer to expose the floating gate layer, and etching the floating gate layer to form a floating gate tip. When the flash memory device is erased, the floating gate tip can be used for discharging, so that the erasing efficiency is improved, and the performance of the flash memory device is improved.
If the height of the floating gate tip is too low and the sharpness is too blunt, the erase performance of the flash memory device is reduced, further, the height and sharpness of the floating gate tip are related to the thickness of the floating gate layer, and the thicker the floating gate layer is, the higher the height and sharpness of the floating gate tip are, so if the floating gate layer is too thin (for example, the thickness of the floating gate layer is less than 600 a), the problems of too low height and too blunt sharpness of the floating gate tip are caused, and thus the erase performance of the flash memory device is affected. Therefore, if the thickness of the floating gate layer is increased, the thickness of the pad nitride layer needs to be correspondingly reduced to ensure the total thickness of the pad nitride layer and the floating gate layer, but after the thickness of the pad nitride layer is reduced, cracks are generated in the floating gate layer and the semiconductor substrate under the pad nitride layer when the shallow trench isolation structure is subjected to the planarization process, so that the thickness of the floating gate layer cannot be increased, and the thickness of the pad nitride layer cannot be reduced, and therefore, a new manufacturing method of the flash memory device is needed to improve the height and the sharpness of the floating gate tip, avoid the occurrence of cracks in the planarization process, and avoid the occurrence of void defects in the shallow trench isolation structure.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory device, which is used for improving the height and the sharpness of a floating gate tip, avoiding cracks in a planarization process and avoiding void defects in a shallow trench isolation structure.
In order to achieve the above object, the present invention provides a method for manufacturing a flash memory device, the method comprising:
providing a semiconductor substrate;
sequentially forming a floating gate material layer and a pad nitride layer on the semiconductor substrate, wherein the floating gate material layer has a first thickness, the pad nitride layer has a second thickness, and the total thickness of the pad nitride layer and the floating gate material layer is within a preset thickness;
etching the pad nitride layer, the floating gate material layer and a part of the thickness of the semiconductor substrate to form a shallow trench, wherein the shallow trench penetrates through the pad nitride layer and the floating gate material layer and extends into the semiconductor substrate;
forming an isolation layer, wherein the isolation layer fills the shallow trench and extends to cover the top surface of the pad nitride layer;
performing a chemical mechanical polishing process on the isolation layer and the pad nitride layer to remove the isolation layer on the top surface of the pad nitride layer and form a shallow trench isolation structure; wherein, the grinding liquid adopted by the chemical mechanical grinding process comprises cerium oxide;
removing the remaining pad nitride layer to expose the floating gate material layer;
the floating gate material layer is etched to form a floating gate having a floating gate tip.
Optionally, in the method for manufacturing a flash memory device, the top surface of the shallow trench isolation structure is flush with the top surface of the pad nitride layer, and the method for forming the shallow trench isolation structure includes:
and performing the chemical mechanical polishing process on the isolation layer and the pad nitride layer to enable the top surface of the isolation layer to be level with the top surface of the pad nitride layer so as to form a shallow trench isolation structure.
Optionally, in the method for manufacturing a flash memory device, the top surface of the shallow trench isolation structure is higher than the top surface of the floating gate material layer and lower than the top surface of the pad nitride layer, and the method for forming the shallow trench isolation structure includes:
performing the chemical mechanical polishing process on the isolation layer and the pad nitride layer to enable the top surface of the isolation layer to be level with the top surface of the pad nitride layer;
and removing the remaining part of the isolation layer to make the top surface of the isolation layer lower than the top surface of the pad nitride layer so as to form a shallow trench isolation structure.
Optionally, in the method for manufacturing a flash memory device, when the chemical mechanical polishing process is performed on the isolation layer and the pad nitride layer, a ratio of a polishing rate of the isolation layer to a polishing rate of the pad nitride layer by the chemical mechanical polishing process is 20: 1-40:1.
Optionally, in the method for manufacturing a flash memory device, the preset thickness is less than or equal to 1700 angstroms;
the first thickness is 700-900 angstroms; and
the second thickness is 800 angstroms to 1000 angstroms.
Optionally, in the method for manufacturing a flash memory device, the method for etching the floating gate material layer includes:
forming a mask layer, wherein the mask layer covers the floating gate material layer;
forming a first opening in the mask layer, wherein the first opening exposes part of the floating gate material layer;
etching the exposed floating gate material layer with partial thickness so that the top surface of the floating gate material layer is concave;
forming a first side wall, wherein the first side wall covers the side wall of the first opening;
etching the exposed floating gate material layer by taking the first side wall and the mask layer as masks to form a second opening, wherein the second opening is communicated with the first opening;
forming a second side wall, wherein the second side wall covers the side wall of the second opening;
forming a word line filling the second opening and the first opening;
removing the mask layer to expose part of the floating gate material layer;
and etching the exposed floating gate material layer to form a floating gate, wherein the floating gate tip of the floating gate is positioned on one side surface of the floating gate away from the word line.
Optionally, in the method for manufacturing a flash memory device, when the first side wall and the mask layer are used as masks, etching is performed for 40 s-120 s on the exposed floating gate material layer with partial thickness.
Optionally, in the method for manufacturing a flash memory device, after the semiconductor substrate is provided, before the floating gate material layer and the pad nitride layer are sequentially formed on the semiconductor substrate, the method for manufacturing a flash memory device further includes:
and forming a floating gate oxide material layer, wherein the floating gate oxide material layer covers the floating gate oxide material layer after the floating gate material layer and the pad nitride layer are sequentially formed on the semiconductor substrate.
Optionally, in the method for manufacturing a flash memory device, after etching the exposed floating gate material layer with the first side wall and the mask layer as masks, the floating gate oxide material layer is further etched, so that the second opening extends through the floating gate oxide material layer;
and after the floating gate is formed, etching the floating gate oxide material layer to form a floating gate oxide layer, wherein the floating gate covers the floating gate oxide layer.
Optionally, in the method for manufacturing a flash memory device, a top surface of the floating gate is concave, and a part of the top surface and a side surface of the floating gate form the floating gate tip.
In the method for manufacturing the flash memory device, a semiconductor substrate is provided, and then, a floating gate material layer and a pad nitride layer are sequentially formed on the semiconductor substrate, wherein the floating gate material layer has a first thickness, the pad nitride layer has a second thickness, and the total thickness of the pad nitride layer and the floating gate material layer is within a preset thickness. Furthermore, by making the total thickness of the pad nitride layer and the floating gate material layer within a preset thickness, the problem of overlarge depth-to-width ratio of the shallow trench isolation structure can be avoided when the shallow trench isolation structure is formed later. Furthermore, when the chemical mechanical polishing process is performed on the isolation layer and the pad nitride layer, the polishing liquid comprises cerium dioxide, so that the pad nitride layer and the isolation layer have a higher polishing rate ratio, more pad nitride layers can be reserved when the chemical mechanical polishing process is performed, and cracks of the floating gate material layer and the semiconductor substrate below the pad nitride layer can be avoided.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory device according to an embodiment of the present invention;
fig. 2 to 16 are schematic structural views formed in a method for manufacturing a flash memory device according to an embodiment of the present invention;
wherein reference numerals are as follows:
100-a semiconductor substrate; 110-a floating gate oxide material layer; 120-a layer of floating gate material; 130-pad nitride layer; 140-shallow trenches; 150-isolating layer; 160-shallow trench isolation structures; 170-mask layer; 180-a first opening; 190-a first side wall; 191-a second opening; 192-second side walls; 193-word line; 194-floating gate; 194 a-floating gate tips; 195-floating gate oxide layer.
Detailed Description
The method for manufacturing the flash memory device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flow chart illustrating a method for manufacturing a flash memory device according to an embodiment of the invention. As shown in fig. 1, the method for manufacturing the flash memory device includes:
step S1: providing a semiconductor substrate;
step S2: sequentially forming a floating gate material layer and a pad nitride layer on the semiconductor substrate, wherein the floating gate material layer has a first thickness, the pad nitride layer has a second thickness, and the total thickness of the pad nitride layer and the floating gate material layer is within a preset thickness;
step S3: etching the pad nitride layer, the floating gate material layer and a part of the thickness of the semiconductor substrate to form a shallow trench, wherein the shallow trench penetrates through the pad nitride layer and the floating gate material layer and extends into the semiconductor substrate;
step S4: forming an isolation layer, wherein the isolation layer fills the shallow trench and extends to cover the top surface of the pad nitride layer;
step S5: performing a chemical mechanical polishing process on the isolation layer and the pad nitride layer to remove the isolation layer on the top surface of the pad nitride layer and form a shallow trench isolation structure; wherein, the grinding liquid adopted by the chemical mechanical grinding process comprises cerium oxide;
step S6: removing the remaining pad nitride layer to expose the floating gate material layer;
step S7: the floating gate material layer is etched to form a floating gate having a floating gate tip.
Next, a method for manufacturing a flash memory device according to the present invention will be described in more detail with reference to fig. 2 to 16. Fig. 2 to 16 are schematic structural diagrams of a flash memory device according to an embodiment of the present invention.
First, referring to fig. 2 and 3, step S1 is performed: a semiconductor substrate 100 is provided, and the semiconductor substrate 100 may be a silicon substrate.
Next, a floating gate oxide material layer 110 is formed on the semiconductor substrate 100. The floating gate oxide material layer 110 may be formed by low pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, molecular beam epitaxy, or the like. The floating gate oxide material layer 110 is made of silicon oxide, such as silicon dioxide, preferably silicon dioxide, so as to enhance the interface adhesion between layers. The floating gate oxide material layer 110 is used to isolate a subsequently formed floating gate material layer 120 from the semiconductor substrate 100.
Next, step S2 is performed, where a floating gate material layer 120 and a pad nitride layer 130 are sequentially formed on the semiconductor substrate 100, the floating gate material layer 120 has a first thickness, the pad nitride layer 130 has a second thickness, and the total thickness of the pad nitride layer 130 and the floating gate material layer 120 is within a preset thickness; the floating gate material layer 120 covers the floating gate oxide material layer 110.
Since the floating gate material layer 110 has the first thickness, it is ensured that the floating gate material layer 110 has a certain thickness, so that the height and sharpness of the floating gate tip formed later are improved, and the problems of too low height and too blunting of the floating gate tip caused by too thin floating gate material layer 120 are avoided, thereby improving the erase performance of the flash memory device.
Further, by making the total thickness of the pad nitride layer 130 and the floating gate material layer 120 within a predetermined thickness, the problem of excessively large aspect ratio of the shallow trench isolation structure can be avoided when the shallow trench isolation structure is formed later.
Specifically, the forming method of the floating gate material layer 120 and the pad oxide layer 130 includes: first, a floating gate material layer 120 is formed, and the floating gate material layer 120 covers the floating gate oxide material layer 110; then, a pad nitride layer 130 is formed according to the thickness (i.e., the first thickness) of the floating gate material layer 120, such that the total thickness of the pad nitride layer 130 and the floating gate material layer 120 is within a predetermined thickness. The floating gate material layer 120 may be polysilicon, for example. The pad nitride layer 130 may be formed by a low pressure chemical vapor deposition process, including but not limited to silicon nitride, preferably silicon nitride, as a stop layer for a subsequent shallow trench isolation structure planarization process.
Wherein the predetermined thickness is less than or equal to 1700 angstroms, the first thickness is 700 angstroms to 900 angstroms, for example, 800 angstroms, 850 angstroms, or 900 angstroms, and the second thickness is 800 angstroms to 1000 angstroms, for example, 800 angstroms.
If the thickness of both the pad nitride layer 130 and the floating gate material layer 120 is too thick (e.g., the total thickness of both is greater than 1700 a), the aspect ratio of the shallow trench 140 formed after the shallow trench 140 is formed is too large, which is unfavorable for filling the isolation layer 150 in the shallow trench, and even causes voids to occur in the isolation layer 150 during filling, and if the thickness is too thin, the process requirements cannot be satisfied.
Next, referring to fig. 3 to 6, step S3 is performed to etch the pad nitride layer 130, the floating gate material layer 120 and a portion of the thickness of the semiconductor substrate 100 to form a shallow trench 140, wherein the shallow trench 140 penetrates the pad nitride layer 130 and the floating gate material layer 120 and extends into the semiconductor substrate 100; wherein the pad nitride layer 130, the floating gate material layer 120, and a portion of the thickness of the semiconductor substrate 100 may be etched using a dry etching process.
Next, step S4 is performed to form an isolation layer 150, where the isolation layer 150 fills the shallow trench 140 and extends to cover the top surface of the pad nitride layer 130. The isolation layer 150 may be formed by high density plasma deposition (HDPCVD), low Pressure Chemical Vapor Deposition (LPCVD) or enhanced plasma chemical vapor deposition (PECVD), and the isolation layer 150 is made of an insulating material.
In addition, a thermal oxidation process may be used to grow a liner oxide layer (which may be silicon dioxide) on the surface of the shallow trench 140 before forming the isolation layer 150, so as to enhance the adhesion of the isolation layer 150 to be filled later.
Next, step S5 is performed to perform a chemical mechanical polishing process on the isolation layer 150 and the pad nitride layer 130, so as to remove the isolation layer 150 on the top surface of the pad nitride layer 130 and form a shallow trench isolation structure 160. Wherein, the grinding liquid adopted by the chemical mechanical grinding process comprises cerium oxide.
Specifically, the method for performing the cmp process on the isolation layer 150 and the pad nitride layer 130 includes sequentially performing the cmp process on the isolation layer 150 and the pad nitride layer 130 to remove the isolation layer 150 on the top surface of the pad nitride layer 130 and remove a portion of the pad nitride layer 130, where the purpose of performing the cmp process on the pad nitride layer 130 is to avoid the isolation layer 150 on the top surface of the pad nitride layer 130 from remaining.
Since the polishing solution includes ceria when the cmp process is performed on the isolation layer 150 and the pad nitride layer 130, a higher polishing rate ratio between the pad nitride layer 130 and the isolation layer 150 is achieved, so that more pad nitride layer 130 remains when the cmp process is performed, and thus cracks in the floating gate material layer 120 under the pad nitride layer 130 and the semiconductor substrate 100 having the second thickness can be prevented. When the cmp process is performed on the isolation layer 150 and the pad nitride layer 130, the ratio of the polishing rate of the isolation layer to the polishing rate of the pad nitride layer 130 by the cmp process is 20: 1-40:1. If mechanical polishing or other polishing solutions are used in this step, a crack may occur in the bottom of the pad nitride layer 130 having the second thickness, which may result in a crack in the floating gate material layer 120 under the pad nitride layer 130, or a polishing rate of the isolation layer 150 may be small compared to a polishing rate of the pad nitride layer 130, which may result in excessive loss of the pad nitride layer 130, which may damage the floating gate material layer 120 under the pad nitride layer 130. Therefore, in the present embodiment, the polishing liquid used in performing the chemical mechanical polishing process is preferably ceria.
Further, the top surface of the shallow trench isolation structure 160 is flush with the top surface of the pad nitride layer 130, and the method for forming the shallow trench isolation structure 160 includes: the cmp process is performed on the isolation layer 150 and the pad nitride layer 130, so that the top surface of the isolation layer 150 is level with the top surface of the pad nitride layer 130, thereby forming a shallow trench isolation structure 160.
Alternatively, as shown in fig. 6, the top surface of the shallow trench isolation structure 160 is higher than the top surface of the floating gate material layer 120 and lower than the top surface of the pad nitride layer 130, and the forming method of the shallow trench isolation structure 160 includes: performing the chemical mechanical polishing process on the isolation layer 150 and the pad nitride layer 130 to make the top surface of the isolation layer 150 flush with the top surface of the pad nitride layer 130; next, as shown in fig. 6, the remaining portion of the thickness of the isolation layer 150 is removed, so that the top surface of the isolation layer 150 is lower than the top surface of the pad nitride layer 130, to form a shallow trench isolation structure 160, wherein a dry etching process may be used to remove a portion of the thickness of the isolation layer 150, and the etching gas used in the dry etching process may be a fluorine-containing gas or a chlorine-containing gas. Of course, a wet etching method may be also used, and preferably, an acid solution may be used to perform a wet etching process to remove a portion of the thickness of the isolation layer, where the acid solution may be hydrofluoric acid, for example.
Next, referring to fig. 7, step S6 is performed to remove the pad nitride layer 130 and expose the floating gate material layer 120. Preferably, the pad nitride 130 is removed by a wet etching process to expose the top surface of the floating gate material layer 120. Specifically, a phosphoric acid solution with a concentration of 40% -90% may be used to remove the pad nitride layer, so as to avoid the pad nitride layer 130 from remaining.
Next, step S7 is performed: referring to fig. 8-16, the floating gate material 120 is etched to form a floating gate 194, the floating gate 194 having a floating gate tip 194a. The top surface of the floating gate 194 is concave, and a part of the top surface and a side surface of the floating gate 194 form the floating gate tip 194a, when the flash memory device is erased, the floating gate tip 194a reduces the channel voltage of the tunneling effect by the tip discharge principle, so that electrons can be more easily pulled away from the floating gate tip 194a and flow into a word line, compared with the prior art, the thickness of the floating gate material layer 120 is ensured when the floating gate material layer 120 is formed, therefore, after the floating gate 194 is formed, the height and the sharpness of the formed floating gate tip 194a of the floating gate 194 can be improved, the problem that the height of the floating gate tip 194a is too low or too blunt is avoided, the electric field strength of the floating gate tip 194a can be improved, and the erasing performance of the flash memory device can be improved.
Specifically, the method for forming the floating gate 194 includes: first, referring to fig. 8, a mask layer 170 is formed on the floating gate material layer 120; the mask layer 170 may be made of silicon nitride, silicon oxynitride, or a stacked structure of silicon nitride and silicon oxynitride, and may be formed by a deposition process, such as a chemical vapor deposition process.
Then, referring to fig. 9, a first opening 180 is formed in the mask layer 170, the first opening 180 exposing a portion of the floating gate material layer 120; next, referring to fig. 10, the exposed floating gate material layer 120 is etched to have a partial thickness such that the top surface of the floating gate material layer 120 is concave; here, an isotropic dry etching process is employed.
Next, referring to fig. 11, a first sidewall 190 is formed, and the first sidewall 190 covers the sidewall of the first opening 180. The first sidewall 190 may be an oxide layer, such as silicon oxide. The first sidewall 190 may be subjected to a rapid anneal after the deposition of the first sidewall 190 to improve step coverage and compactness of the first sidewall 190. The process temperature for depositing the first side wall 190 is 300-800 ℃, the annealing temperature is 600-1200 ℃, the annealing time is 30-100 s, and the annealing temperature in the embodiment is 1150 ℃.
Then, referring to fig. 12, the exposed floating gate material layer 120 is etched using the first sidewall 190 and the mask layer 130 as a mask, to form a second opening 191, and the second opening 191 communicates with the first opening 180.
Next, referring to fig. 13, a second side wall 192 is formed, where the second side wall 192 covers a side wall of the second opening; the second sidewall 192 includes, but is not limited to, silicon oxide, for example, silicon nitride.
Next, referring to fig. 14, a word line 193 is formed, the word line 193 filling the first opening 180 and the second opening 191; next, referring to fig. 15, the mask layer 170 is removed, exposing a portion of the floating gate material layer 120, i.e., exposing the floating gate material layer 120 not covered by the first sidewall 190; finally, referring to fig. 16, the exposed floating gate material layer 120 is etched to form a floating gate 194, the floating gate 194 having a floating gate tip 194a, the floating gate tip 194a of the floating gate 194 being located on a side of the floating gate 194 remote from the word line 193.
In addition, after etching the exposed floating gate material layer 120 to form the floating gate 194, it further includes: the floating gate oxide material layer 110 is etched to form a floating gate oxide layer 195. Wherein a dry etching process is used when etching the exposed floating gate material layer 120 and floating gate oxide material layer 110.
In summary, in the method for manufacturing a flash memory device provided by the invention, a semiconductor substrate is provided, and then, a floating gate material layer and a pad nitride layer are sequentially formed on the semiconductor substrate, wherein the floating gate material layer has a first thickness, the pad nitride layer has a second thickness, and the total thickness of the pad nitride layer and the floating gate material layer is within a preset thickness. Furthermore, by making the total thickness of the pad nitride layer and the floating gate material layer within a preset thickness, the problem of overlarge depth-to-width ratio of the shallow trench isolation structure can be avoided when the shallow trench isolation structure is formed later. Furthermore, when the chemical mechanical polishing process is executed, the adopted polishing liquid is cerium dioxide, so that a higher polishing rate ratio between the pad nitride layer and the isolation layer can be realized, more pad nitride layers can be reserved when the chemical mechanical polishing process is executed, and therefore, cracks of the floating gate material layer below the pad nitride layers and the semiconductor substrate can be avoided.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. A method of manufacturing a flash memory device, comprising:
providing a semiconductor substrate;
sequentially forming a floating gate material layer and a pad nitride layer on the semiconductor substrate, wherein the floating gate material layer has a first thickness, the pad nitride layer has a second thickness, and the total thickness of the pad nitride layer and the floating gate material layer is within a preset thickness, wherein the preset thickness is less than or equal to 1700 angstroms, the first thickness is 700-900 angstroms, and the second thickness is 800-1000 angstroms;
etching the pad nitride layer, the floating gate material layer and a part of the thickness of the semiconductor substrate to form a shallow trench, wherein the shallow trench penetrates through the pad nitride layer and the floating gate material layer and extends into the semiconductor substrate;
forming an isolation layer, wherein the isolation layer fills the shallow trench and extends to cover the top surface of the pad nitride layer;
performing a chemical mechanical polishing process on the isolation layer and the pad nitride layer to remove the isolation layer on the top surface of the pad nitride layer and form a shallow trench isolation structure; wherein, the grinding liquid adopted by the chemical mechanical grinding process comprises cerium oxide;
removing the remaining pad nitride layer to expose the floating gate material layer;
the floating gate material layer is etched to form a floating gate having a floating gate tip.
2. The method of manufacturing a flash memory device of claim 1, wherein a top surface of the shallow trench isolation structure is flush with a top surface of the pad nitride layer, the method of forming the shallow trench isolation structure comprising:
and performing the chemical mechanical polishing process on the isolation layer and the pad nitride layer to enable the top surface of the isolation layer to be level with the top surface of the pad nitride layer so as to form a shallow trench isolation structure.
3. The method of manufacturing a flash memory device of claim 1, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the floating gate material layer and lower than a top surface of the pad nitride layer, the method of forming the shallow trench isolation structure comprising:
performing the chemical mechanical polishing process on the isolation layer and the pad nitride layer to enable the top surface of the isolation layer to be level with the top surface of the pad nitride layer;
and removing the remaining part of the isolation layer to make the top surface of the isolation layer lower than the top surface of the pad nitride layer so as to form a shallow trench isolation structure.
4. The method of manufacturing a flash memory device according to claim 2 or 3, wherein when the chemical mechanical polishing process is performed on the isolation layer and the pad nitride layer, a ratio of a polishing rate of the isolation layer to a polishing rate of the pad nitride layer by the chemical mechanical polishing process is 20: 1-40:1.
5. The method of manufacturing a flash memory device of claim 1, wherein the method of etching the floating gate material layer comprises:
forming a mask layer, wherein the mask layer covers the floating gate material layer;
forming a first opening in the mask layer, wherein the first opening exposes part of the floating gate material layer;
etching the exposed floating gate material layer with partial thickness so that the top surface of the floating gate material layer is concave;
forming a first side wall, wherein the first side wall covers the side wall of the first opening;
etching the exposed floating gate material layer by taking the first side wall and the mask layer as masks to form a second opening, wherein the second opening is communicated with the first opening;
forming a second side wall, wherein the second side wall covers the side wall of the second opening;
forming a word line filling the second opening and the first opening;
removing the mask layer to expose part of the floating gate material layer;
and etching the exposed floating gate material layer to form a floating gate, wherein the floating gate tip of the floating gate is positioned on one side surface of the floating gate away from the word line.
6. The method of manufacturing a flash memory device as claimed in claim 5, wherein when the first sidewall and the mask layer are used as masks, etching is performed for 40s to 120s on the exposed floating gate material layer with partial thickness.
7. The method of manufacturing a flash memory device of claim 6, wherein after providing the semiconductor substrate, before sequentially forming the floating gate material layer and the pad nitride layer on the semiconductor substrate, the method of manufacturing a flash memory device further comprises:
and forming a floating gate oxide material layer, wherein the floating gate oxide material layer covers the floating gate oxide material layer after the floating gate material layer and the pad nitride layer are sequentially formed on the semiconductor substrate.
8. The method of manufacturing a flash memory device of claim 7, further etching the floating gate oxide material layer after etching the exposed floating gate material layer with the first sidewall and the mask layer as masks such that the second opening extends through the floating gate oxide material layer;
and after the floating gate is formed, etching the floating gate oxide material layer to form a floating gate oxide layer, wherein the floating gate covers the floating gate oxide layer.
9. The method of manufacturing a flash memory device of claim 1, wherein a top surface of the floating gate is concave, and a portion of the top surface and a side surface of the floating gate form the floating gate tip.
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