KR20100007208A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to increase the width of a contact hole expected area by etching a first spacer with a preset thickness after removing an insulation layer for a second spacer of the memory cell transistor expected area. CONSTITUTION: A gate pattern(210) is formed on a substrate(200). A first spacer(230) is formed. An insulation layer for a second spacer is formed. A first mask is formed on a memory cell transistor-expected area. A second spacer(240A) is formed on a sidewall of the gate pattern by etching the insulation layer for the second spacer. After forming a second mask(270), the insulation layer for the second spacer is removed. The first spacer is etched with the partial thickness. The width(W2) of a contact hole expected area is increased.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.

As the integration of semiconductor devices improves, the cell area continues to decrease. Therefore, there is a need for a technique for forming contact holes with a fine spacing in forming contact holes by a self aligned contact (SAC) process.

In particular, an LDD (lightly doped drain) structure transistor needs to form an additional spacer on the sidewall of the gate pattern to form a high concentration impurity region, which causes a problem in that the contact hole predetermined region width of the cell region is reduced. Hereinafter, a problem according to the prior art will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art. Here, (a) is a region where a memory cell transistor is to be formed, hereinafter referred to as a memory cell transistor predetermined region, and (b) is a region where a transistor of an LDD structure is to be formed, hereinafter referred to as a transistor predetermined region of an LDD structure.

As shown in FIG. 1A, the gate insulating layer 110A, the gate electrode conductive layer 110B, and the hard mask layer 110C are sequentially formed on the substrate 100, and then selectively etched to form the gate pattern 110. ). Subsequently, a low concentration impurity region 120 is formed in the substrate 100 on both sides of the gate pattern 110.

As shown in FIG. 1B, the first spacer 130 is formed on the entire surface of the resultant product in which the low concentration impurity region 120 is formed. Here, the first spacer 130 is formed to a minimum thickness to prevent damage to the substrate 100 and the gate pattern 110 when the insulating film for the second spacer is subsequently removed, and is formed of a nitride film.

Subsequently, a second spacer insulating layer 140 made of an oxide film is formed on the entire surface of the resultant in which the first spacer 130 is formed.

As shown in FIG. 1C, after forming the first mask 150 in the predetermined region of the memory cell transistor, the gate pattern 110 is formed by spacer etching the second spacer insulating layer 140 formed in the predetermined region of the transistor having the LDD structure. The second spacer 140A is formed on the sidewall of the second spacer 140A.

Here, since the memory cell transistor predetermined region is covered by the first mask 150, spacer etching is performed only in the transistor predetermined region of the LDD structure, and the substrate 100 on both sides of the gate pattern 110 is exposed.

Subsequently, a high concentration impurity region 160 is formed in the substrate 100 on both sides of the second spacer 140A.

As shown in FIG. 1D, after the second mask 170 is formed in the transistor predetermined region of the LDD structure, the insulating layer 140 for the second spacer formed in the predetermined region of the memory cell transistor is removed. At this time, damage to the gate pattern 110 and the substrate 100 is prevented by the first spacer 130.

Here, the gap region between the first spacers 130 represents a region where a contact hole is to be formed, that is, a region in which a contact hole is to be formed by a subsequent process. Therefore, as the thickness of the first spacer 130 formed on the sidewall of the gate pattern 110 increases, the width W1 of the contact hole predetermined region decreases.

As described above, the first spacer 130 is formed to a minimum thickness to serve as an etch stop layer when the second spacer insulating layer 140 is etched, but after the second spacer insulating layer 140 is removed. Since one spacer 130 remains, the width W1 of the contact hole predetermined area is reduced.

As shown in FIG. 1E, after forming the interlayer insulating layer 180 on the entire structure of the resultant, a photoresist pattern 190 is formed on the interlayer insulating layer 180 to expose the contact hole predetermined region.

Subsequently, the interlayer insulating layer 180 is etched using the photoresist pattern 190 as an etch barrier to form a contact hole T exposing the substrate 100. In this case, the process of forming the contact hole T is performed by a self aligned contact (SAC) process.

However, as described above, since the width W1 of the contact hole T is reduced due to the remaining first spacer 130 after the removal of the second spacer insulating layer 140, the interlayer insulating layer above the limit of the etching process. Since the 180 is not sufficiently etched, a not open phenomenon may occur in which the contact hole T is not formed. In particular, as the integration of semiconductor devices improves, these problems are further exacerbated.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problem, and fabricates a semiconductor device which increases the width of the contact hole predetermined region by removing the second spacer insulating film formed in the predetermined region of the memory cell transistor and etching the first spacer a predetermined thickness. It is an object to provide a method.

Those skilled in the art to which the present invention pertains can easily recognize other objects and advantages of the present invention from the drawings, the detailed description of the invention, and the claims.

The present invention proposed to achieve the above object comprises the steps of: forming a gate pattern on a substrate; Forming a spacer on sidewalls of the gate pattern; And etching the spacers to some thickness to increase the width of the contact hole predetermined area.

According to the present invention, after removing the insulating film for the second spacer formed in the predetermined region of the memory cell transistor, the first spacer is etched by a predetermined thickness to increase the width of the predetermined contact hole region, thereby preventing the contact hole sick opening phenomenon. Therefore, the characteristic of a semiconductor device can be improved and the yield of a semiconductor device manufacturing process can be improved.

In the following, the most preferred embodiment of the present invention is described. In the drawings, thickness and spacing may be exaggerated for convenience of description. In describing the present invention, well-known structures irrelevant to the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Here, (a) is a region where a memory cell transistor is to be formed, hereinafter referred to as a memory cell transistor predetermined region, and may be a cell region. (b) is a region where the transistor of the LDD structure is to be formed, hereinafter referred to as a transistor predetermined region of the LDD structure, and may be a peripheral circuit region.

As shown in FIG. 2A, the gate insulating layer 210A, the gate electrode conductive layer 210B, and the hard mask layer 210C are sequentially formed on the substrate 200, and then selectively etched to form the gate pattern 210. ). Subsequently, the low concentration impurity region 220 is formed in the substrate 200 on both sides of the gate pattern 210.

As shown in FIG. 2B, the first spacer 230 is formed on the entire surface of the resultant product in which the low concentration impurity region 220 is formed. Here, the first spacer 230 is preferably made of a nitride film.

In addition, the first spacer 230 may be formed to a minimum thickness to prevent damage to the substrate 200 and the gate pattern 210 when the second spacer insulation layer 240 is subsequently removed. More preferably, it is formed in thickness of 130 GPa or more.

Subsequently, an insulating film 240 for the second spacer is formed on the entire surface of the resultant product in which the first spacer 230 is formed. Here, the second spacer insulating film 240 is preferably made of an oxide film.

As shown in FIG. 2C, after the first mask 250 is formed on the memory cell transistor predetermined region, the gate spacer 210 is formed by spacer etching the second spacer insulating layer 240 formed on the transistor predetermined region of the LDD structure. The second spacer 240A is formed on the sidewalls of the substrate. Here, the first mask 250 is preferably made of a photoresist.

In this case, since the memory cell transistor predetermined region is covered by the first mask 250, the spacer etching is performed only in the transistor predetermined region of the LDD structure, and the substrate 200 on both sides of the gate pattern 210 is exposed. Next, a high concentration impurity region 260 is formed in the substrate 200 on both sides of the second spacer 240A.

As shown in FIG. 2D, after the second mask 270 is formed in the transistor predetermined region of the LDD structure, the second spacer insulating layer formed in the predetermined region of the memory cell transistor using the first spacer 230 as an etch stop layer. Remove 240. Here, the etching of the second spacer insulating film 240 is preferably performed by a wet etching process.

In this case, damage to the gate pattern 210 and the substrate 200 is prevented by the first spacer 230, where the gap region between the first spacers 230 is a region where a contact hole is to be formed by a subsequent process, that is, A contact hole planned area is shown.

Subsequently, a portion of the first spacer 230 formed on the sidewall of the gate pattern 210 of the predetermined region of the memory cell transistor is etched to increase the width W2 of the predetermined region of the contact hole. Thus, the thickness-adjusted 1st spacer is shown here by 230A.

According to the semiconductor device manufacturing method according to an embodiment of the present invention, by reducing the thickness of the first spacer 230A, as described in Equation 1 below, the width W2 of the contact hole predetermined region is reduced. Can be increased.

The width W1 of the conventional contact hole planning area <the width W2 of the contact hole planning area of the present invention

Here, the etching thickness of the first spacer 230A is determined in consideration of the width W2 of the contact hole predetermined region, the parasitic capacitance, and the like, and the thickness of the first spacer 230A is preferably etched, and thus, the gate pattern 110 is formed on the gate pattern 110. It is preferable to allow the first spacer 230A having a thickness of 50 to 100 microseconds to remain.

Here, the etching process of the first spacer 230A is preferably performed by isotropic etching or isotropic dry etching, for example, using an etching apparatus using plasma gas, under a condition in which a bias voltage is not applied. It is more preferable to isotropically etch the first spacer 230A by performing the etching. Further, the first spacer 230A may be isotropically etched. Further, the first spacer 230A may be isotropically etched by using a fluorine radical activated through a plasma gas generated by a remote plasma source. It is preferable to reactively etch one spacer 230.

In this case, the etching of the first spacer 230A may be performed by using a fluorine-based gas as an etching gas, and more particularly, by using a fluorine-based gas, an O ₂ gas, a He gas, and an N ₂ gas as an etching gas. desirable. Here, the fluorine-based gas may be, for example, C _x F _y , N _x F _y, or C _x H _y F _z gas.

In this case, the etching process of the first spacer 230A is preferably performed at a speed of 100 to 600 kW / min, and the etching speed may be adjusted according to the pressure of the etching equipment or the ratio of the etching gas. For example, it is preferable to adjust the pressure of the etching equipment to 300 to 1000 mTorr, and to adjust the ratio of the fluorine-based gas and the non-reactive gas in the etching gas to 1: 1 to 5: 1. Here, the non-reactive gas is preferably an O ₂ gas, He gas or N ₂ gas.

As shown in FIG. 2E, after forming the interlayer insulating film 280 on the entire structure of the resultant, a photoresist pattern 290 is formed on the interlayer insulating film 280 to expose the contact hole predetermined region.

Subsequently, the interlayer insulating layer 280 is etched using the photoresist pattern 290 as an etch barrier to form a contact hole T exposing the substrate 200. The contact hole T forming process may be performed by a self aligned contact (SAC) process.

According to an embodiment of the present invention as described above, since the first spacer 230A may be partially etched to increase the width W2 of the predetermined area of the contact hole, not open due to the limitation of the etching process. The phenomenon can be improved.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

[Description of Symbols for Main Parts of Drawing]

Reference Signs List 100: substrate, 110A: gate insulating film, 110B: conductive film for gate electrode, 110C: hard mask layer, 110: gate pattern, 120: low concentration impurity region, 130: first spacer, 140: second spacer insulating film, 140A: Second spacer, 150: first mask, 160: high concentration impurity region, 170: second mask, 180: interlayer insulating film, 190: photoresist pattern, T: contact hole, 200: substrate, 210A: gate insulating film, 210B: gate Conductive film for electrode, 210C: hard mask layer, 210: gate pattern, 220: low concentration impurity region, 230: first spacer, 230A: first spacer with controlled thickness, 240: insulating film for second spacer, 240A: second Spacer, 250: first mask, 260: high concentration impurity region, 270: second mask, 280: interlayer insulating film, 290: photoresist pattern

Claims (14)

Forming a gate pattern on the substrate; Forming a spacer on sidewalls of the gate pattern; And Etching a thickness of the spacer to increase a width of a contact hole region; A semiconductor device manufacturing method comprising a. The method of claim 1, The spacer etching step, Performed by isotropic etching Semiconductor device manufacturing method. The method of claim 2, The spacer etching step, Carried out using one or a combination of fluorine-based gas, O ₂ gas, He gas and N ₂ gas. Semiconductor device manufacturing method. The method of claim 2, The spacer etching step, Performed at a rate of 100 to 600 Hz / min Semiconductor device manufacturing method. The method of claim 2, The spacer etching step, Performed at a pressure of 300 to 1000 mTorr Semiconductor device manufacturing method. The method of claim 2, The spacer etching step, It is performed using an etching gas in which the ratio of the fluorine-based gas and the non-reactive gas is 1: 1 to 5: 1. Semiconductor device manufacturing method. The method of claim 1, The spacer etching step, Performed by dry etching Semiconductor device manufacturing method. The method of claim 1, The spacer, Formed to a thickness of 130Å or more Semiconductor device manufacturing method. The method of claim 1, The thickness is 50-100 kPa Semiconductor device manufacturing method. The method of claim 1, The spacer etching step, By etching the spacers in part thickness, the spacers having a thickness of 50 to 100 Å remain Semiconductor device manufacturing method. The method of claim 1, The spacer, It consists of a first spacer and a second spacer, The spacer etching step, Removing the second spacer using the first spacer as an etch stop layer; And Etching the first spacer partially to increase the width of the contact hole region; A semiconductor device manufacturing method comprising a. The method of claim 11, The semiconductor device, A memory cell transistor and an LDD structure transistor, The second spacer, Used to form a high concentration impurity region of the LDD structure transistor Semiconductor device manufacturing method. The method of claim 11, The first spacer is made of a nitride film, The second spacer is made of an oxide film Semiconductor device manufacturing method. The method of claim 11, Part of the thickness etching of the first spacer, Performed by isotropic etching Semiconductor device manufacturing method.

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