KR100636685B1 - Method for fabricating transistor in semiconductor device - Google Patents

Abstract

A method for forming a transistor in a semiconductor device is provided to improve a hump phenomenon by blocking an introduction path of contaminants and hydrogen. A gate oxide layer having a thickness of 50~100 angstroms and a nitride layer pattern for selectively exposing the gate oxide layer are formed on a semiconductor substrate(200). An oxide layer is formed on the semiconductor substrate including the exposure region of the gate oxide layer. The oxide layer is etched to form an inner spacer(214) on both lateral surfaces of the nitride layer pattern. A conductive layer, a metal silicide layer and a nitride layer for a hard mask are sequentially formed on the semiconductor substrate including the inner spacer on both the lateral surfaces of the nitride layer pattern. A mask layer pattern is formed on the nitride layer for the hard mask to define a gate stack formation region. By using the mask layer pattern as a mask, the nitride layer for the hard mask and the metal silicide layer are patterned. The nitride layer pattern is removed by a dry etch method to form a gate stack(228). A gat spacer(230) is disposed on both lateral surfaces of the gate stack.

Description

Method for fabricating transistor in semiconductor device

1 is a view illustrating a short channel hump phenomenon occurring when a semiconductor device is formed according to the related art.

2A to 2H are diagrams illustrating a method of forming a transistor of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200 semiconductor substrate 214 internal spacer

216: conductive film pattern 224: hard mask film pattern

226 tungsten silicide film pattern 228 gate stack

230: Gate spacer

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a transistor of a semiconductor device.

Recently, in manufacturing most semiconductor devices, a gate stack including a stacked structure of a gate insulating film, a gate conductive film, and a hard mask film is used in forming a gate. Here, the hard mask layer serves as a hard mask during etching to form the gate stack, and when forming a landing plug contact hole (LPC) in a subsequent process, self-alignment due to a difference in the etch selectivity of the surrounding oxide layer It is also used as a hard mask film in a contact alignment (SAC) process. In the self-aligned contact (SAC) process, a nitride film is formed as a gate spacer for insulation not only in the hard mask film but also in the self-aligned contact (SAC) process, and a buffer oxide film is used to prevent contact between the nitride film and the semiconductor substrate. . This is to prevent the semiconductor substrate and the nitride film from directly contacting each other, thereby preventing a sudden increase in the sheet resistance (Rs) of the semiconductor substrate due to the tensile stress of the nitride. In addition, when the gate stack is formed, stress can be prevented from being applied to the conductive film pattern.

In more detail, if the semiconductor substrate and the nitride film are in direct contact, the drain saturation current (Idsat) is reduced by about 20% in the PMOS, and the threshold voltage is changed in the NMOS, which affects the reliability of the device. Will receive. Other physical problems may cause deficient voids in the semiconductor substrate. In order to solve this problem, a buffer oxide film is formed. The buffer oxide film acts as an inflow passage for impurities in a subsequent process, causing a short channel hump phenomenon. This will be described in detail with reference to the drawings.

1 is a view illustrating a short channel hump phenomenon occurring when a semiconductor device is formed according to the related art.

Although not shown in the drawings, a gate insulating film and a gate conductive film are deposited on a semiconductor substrate on which a predetermined substructure is formed, and then a hard mask film is formed on the gate conductive film. Next, after forming a photoresist pattern for forming a gate on the hard mask layer, an etching process is performed using the photoresist pattern as a mask, and as shown in FIG. 1, the hard mask layer pattern 140 and the gate conductive layer pattern ( A gate stack 150 including the 130 and the gate insulating layer pattern 120 is formed. Thereafter, a buffer oxide layer 160 is formed to relieve stress caused by the nitride layer during subsequent gate spacer formation. The buffer oxide film 160 may be a high temperature oxide (HTO) or a low press TEOS (LPTEOS) oxide film formed at a high temperature of 685 degrees or more. In addition, a nitride layer (not shown) is deposited on the entire surface of the resultant product of the buffer oxide layer 160, and the gate spacer 170 is disposed on both sidewalls of the gate stack 150.

However, in general, the high temperature oxide film or the LPTEOS oxide film is inferior to the insulating and barrier properties compared to the nitride. Therefore, hydrogen (H ₂ ) ions and impurities penetrate through the buffer oxide film 160 and accumulate at the interface of the gate insulating film 110 during the subsequent process (A). At this time, the hydrogen (H ₂ ) ion has a problem in that a short channel hump phenomenon occurs by rapidly acting as a carrier due to rapid mobility and rapidly reducing the threshold voltage. In addition, the conventional gate stack has the same area of the conductive film and the tungsten silicide (WSix) film. However, there is a problem in that the resistance Rs of the gate increases as the degree of integration of the DRAM technology is improved.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming a spacer of a semiconductor device in which a hump phenomenon may be blocked by blocking an inflow path of contaminants and hydrogen, which cause the hump phenomenon, and a gate sheet resistance may be reduced.

In order to achieve the above technical problem, a method of forming a transistor of a semiconductor device according to the present invention, forming a nitride film pattern for selectively exposing the gate oxide film and the gate oxide film on the entire surface of the semiconductor substrate; Forming an oxide film on an entire surface of the semiconductor substrate including an exposed region of the gate oxide film; Etching the oxide layer to form internal spacers on both sides of the nitride layer pattern; Sequentially forming a conductive film, a metal silicide film, and a hard mask nitride film on the entire surface of the semiconductor substrate having internal spacers formed on both sides of the nitride film pattern; Forming a mask layer pattern defining a gate stack forming region on the hard mask nitride layer; Patterning a hard mask nitride layer and a metal silicide layer using the mask layer pattern as a mask; Removing the nitride layer pattern to form a gate stack; And forming gate spacers disposed at both sides of the gate stack.

In this invention, it is preferable to form in thickness of 50-100 kPa.

In addition, it is preferable to form a conductive film not lower than the height of the inner spacers.

The metal silicide layer may include tungsten silicide (WSix).

The nitride layer pattern may use dry etching.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2A to 2H are views illustrating a method of forming a spacer of a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 2A, an oxide process is performed on a semiconductor substrate 200 in which an active region and an isolation region are defined as the isolation layer 202, thereby forming a gate oxide layer 204. The gate oxide film 204 serves as a buffer oxide film to prevent the gate spacer to be formed later from coming into direct contact with the semiconductor substrate 200, and at the same time serves as an insulating film of the gate stack. In this case, the gate oxide film 204 is formed to be thick enough to serve as a barrier film even after the nitride film of the spacer formation and the landing plug contact hole forming region is removed, and is preferably formed to have a thickness of 50-100 GPa. Next, a nitride film 206 is formed on the gate oxide film 204, a photoresist film is applied on the nitride film 206, and then a photosensitive film pattern 208 exposing a predetermined region of the nitride film 206 by performing exposure and development processes. To form.

Next, referring to FIG. 2B, the nitride film 206 is etched using the photoresist pattern 208 as a mask to form a nitride film pattern 210 for selectively exposing the gate oxide film 204. The nitride film pattern 210 is formed at the same height as the internal spacers to be formed in a subsequent process. That is, the height of the internal spacers may be adjusted by adjusting the height of the nitride film pattern 210.

Next, referring to FIG. 2C, the oxide film 212 is formed by performing an oxidation process on the entire surface of the semiconductor substrate 200 including the exposed region of the gate oxide film 204 and the nitride film pattern 210. Here, the oxide film 212 is formed of a high density plasma (HDP) oxide film formed by loading the structure into the high density plasma apparatus, supplying the silica (SiH ₄ ) as a source gas, and supplying an appropriate bias power. You may.

Next, referring to FIG. 2D, an internal spacer 214 is formed by performing an etching process on the oxide film 212 so that a predetermined thickness remains on both sides of the nitride film pattern 210. The inner spacer 214 serves as a buffer film that can prevent penetration of hydrogen (H ₂ ) ions and impurities that may occur in a subsequent process. Here, the etching process may be performed by wet etching, and by controlling the etching selectivity of the oxide layer, the thickness of the oxide layer 212 remaining on both sides of the nitride layer pattern 210 may be adjusted, and the gate may be formed according to the internal spacers 214 formed as described above. The channel length of the stack can be adjusted.

Next, referring to FIG. 2E, a conductive film 216, a tungsten silicide (WSix) film 218, and a hard mask are disposed on the entire surface of the semiconductor substrate 200 including the nitride film pattern 210 and the internal spacers 214. The nitride film 220 is formed sequentially. The conductive film 216 may be formed by applying a conductive material such as polysilicon, and the tungsten silicide (WSix) film 218 may be formed by chemical vapor phase using tungsten hexafluoride (WF ₆ ) gas and xylene (SiH₄) gas. It may be formed using a chemical vapor deposition (CVD) method. In some cases, a metal silicide film forming process, that is, a metal film may be formed, a thermal process may be performed to form a metal silicide film, and an unreacted metal film that has not reacted in the thermal process may be formed. . In this case, the height of the conductive film 216 may be adjusted by using the deposition thickness of the nitride film pattern 210. Preferably, the conductive film is formed so as not to be lower than the height of the inner spacer 214, and more preferably, the inner spacer ( It is formed at the same height as 214). Next, a photoresist film is coated on the hard mask nitride film 220 and patterned to form a mask film pattern 222 defining a gate formation region.

Next, referring to FIG. 2F, an etching process using the mask layer pattern 222 as a mask is performed to etch the hard mask nitride layer 220 to form a hard mask layer pattern 224, thereby forming a mask layer pattern 222. Remove. Next, the tungsten silicide (Wsix) layer 218 is etched using the hard mask layer pattern 224 as a mask to form a tungsten silicide (WSix) layer pattern 226.

Next, referring to FIG. 2G, the nitride film pattern 210 is removed, and the hard mask film pattern 224, the tungsten silicide (WSix) film pattern 226, and the internal spacer 214 are disposed on both sides of the conductive film pattern. A gate stack 228 including a 216 and a gate oxide film 204 is formed. The nitride layer pattern 210 may be removed by dry etching using methane (CH ₄ ) gas or trifluoromethane (CHF ₃ ) gas. In this case, the area of the tungsten silicide (WSsix) film pattern 226 having low resistance is increased to lower the gate resistance Rs, thereby improving device characteristics. In addition, since the internal spacers 214 are disposed on both side surfaces of the conductive film pattern 216, the conductive film pattern 216 may be prevented from being stressed by an etching process or the like when the gate stack 228 is formed.

Next, referring to FIG. 2H, after a nitride film (not shown) is deposited on the front surface of the structure including the gate stack 228, gate spacers disposed on both sides of the gate stack 228 may be further processed by spacer etching. To form 230. In this case, while the gate oxide layer 204 serves as a buffer oxide layer under the gate spacer 230, an increase in resistance may be prevented while the nitride layer is in direct contact with the semiconductor substrate 200.

According to the present invention, when the spacer of the semiconductor device is formed, the inner spacer 214 remains only on the sidewall of the conductive film pattern 216, and the sidewalls of the tungsten silicide (WSix) film pattern 226 and the hard mask film pattern 224. As the nitride film remains as the gate spacer 230, a gate capping effect may be obtained. In addition, in the related art, a path through which the hydrogen (H ₂ ) and impurities penetrate (A, FIG. 1) through the buffer oxide layer 160 (see FIG. 1) may be removed at its source to prevent the short channel hump phenomenon.

As described above, according to the spacer forming method of the semiconductor device according to the present invention, the internal spacers are formed on the sidewalls of the conductive film pattern to form only the gate spacers on the sidewalls of the tungsten silicide (WSix) film pattern and the hard mask film pattern. As a result, a path through which hydrogen (H ₂ ) and impurities can penetrate at least may be removed to prevent short channel hump. In addition, the area of the tungsten silicide film pattern is increased to prevent the gate resistance from increasing.

Claims (5)

Forming a gate oxide film and a nitride film pattern selectively exposing the gate oxide film on the entire surface of the semiconductor substrate; Forming an oxide film on an entire surface of the semiconductor substrate including an exposed region of the gate oxide film; Etching the oxide layer to form internal spacers on both sides of the nitride layer pattern; Sequentially forming a conductive film, a metal silicide film, and a hard mask nitride film on the entire surface of the semiconductor substrate having internal spacers formed on both sides of the nitride film pattern; Forming a mask layer pattern defining a gate stack forming region on the hard mask nitride layer; Patterning a hard mask nitride layer and a metal silicide layer using the mask layer pattern as a mask; Removing the nitride layer pattern to form a gate stack; And And forming gate spacers disposed on both sides of the gate stack. The method of claim 1, And the gate oxide film is formed to a thickness of 50-100 kHz. The method of claim 1, And forming a conductive film not lower than the height of the internal spacers. The method of claim 1, The metal silicide layer includes tungsten silicide (WSix). The method of claim 1, And the nitride layer pattern is removed by dry etching.

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